JPS6466955A - Semiconductor integrated circuit - Google Patents

Semiconductor integrated circuit

Info

Publication number
JPS6466955A
JPS6466955A JP22465087A JP22465087A JPS6466955A JP S6466955 A JPS6466955 A JP S6466955A JP 22465087 A JP22465087 A JP 22465087A JP 22465087 A JP22465087 A JP 22465087A JP S6466955 A JPS6466955 A JP S6466955A
Authority
JP
Japan
Prior art keywords
layer
tungsten silicide
opening section
wirings
section
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP22465087A
Other languages
Japanese (ja)
Inventor
Shigeru Takahashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP22465087A priority Critical patent/JPS6466955A/en
Publication of JPS6466955A publication Critical patent/JPS6466955A/en
Pending legal-status Critical Current

Links

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To prevent a cross section by migration of an aluminum layer by using wirings having two layer structure formed by superposing the aluminum layer and a tungsten silicide layer as multilayer interconnections for a semiconductor integrated circuit. CONSTITUTION:An silicon oxide film 2 and an N-type diffusion region 3 are shaped onto the surface of a P-type silicon substrate 1, a PSG film 4 is deposited, and the upper section of the region 3 is etched selectively to form a first opening section. A tungsten silicide layer 5 and an aluminum layer 6 are deposited onto the surface in succession, and lower layer wirings having two layer structure connect ed to the N-type diffusion region in the first opening section are shaped. An aluminum layer 8 and a tungsten silicide layer 9 are deposited successively onto the surface including a second opening section, and upper layer wirings having two layer structure connected to the lower layer wiring in the second opening section are formed. Molybdenum silicide may be employed in place of tungsten silicide.
JP22465087A 1987-09-07 1987-09-07 Semiconductor integrated circuit Pending JPS6466955A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP22465087A JPS6466955A (en) 1987-09-07 1987-09-07 Semiconductor integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP22465087A JPS6466955A (en) 1987-09-07 1987-09-07 Semiconductor integrated circuit

Publications (1)

Publication Number Publication Date
JPS6466955A true JPS6466955A (en) 1989-03-13

Family

ID=16817047

Family Applications (1)

Application Number Title Priority Date Filing Date
JP22465087A Pending JPS6466955A (en) 1987-09-07 1987-09-07 Semiconductor integrated circuit

Country Status (1)

Country Link
JP (1) JPS6466955A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5202579A (en) * 1991-01-30 1993-04-13 Mitsubishi Denki Kabushiki Kaisha Semiconductor device having multilayer interconnection structure
JP2004063610A (en) * 2002-07-26 2004-02-26 Seiko Instruments Inc Manufacturing method of semiconductor device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5202579A (en) * 1991-01-30 1993-04-13 Mitsubishi Denki Kabushiki Kaisha Semiconductor device having multilayer interconnection structure
US5312775A (en) * 1991-01-30 1994-05-17 Mitsubishi Denki Kabushiki Kaisha Method of manufacturing semiconductor device having multilayer interconnection structure
JP2004063610A (en) * 2002-07-26 2004-02-26 Seiko Instruments Inc Manufacturing method of semiconductor device

Similar Documents

Publication Publication Date Title
JPS6466955A (en) Semiconductor integrated circuit
JPS57139939A (en) Semiconductor device
JPS6441240A (en) Semiconductor integrated circuit device
JPS6482653A (en) Semiconductor integrated circuit
JPS59144171A (en) Semiconductor integrated circuit device
JPS54139493A (en) Manufacture of semiconductor device containing poly-crystal silicon layer
JPS5766673A (en) Manufacture of mos type semiconductor device
JPS5789239A (en) Semiconductor integrated circuit
JPS56108242A (en) Master slice semiconductor device
JPS55113344A (en) Electrode wiring and its manufacture
JPS60227469A (en) Semiconductor device
JPS6074658A (en) Semiconductor ic device
JPS57202776A (en) Semiconductor device
JPS647550A (en) Semiconductor device
JPH0153512B2 (en)
JP2947800B2 (en) Semiconductor device
JPS554965A (en) Semiconductor
JPS6419759A (en) Semiconductor integrated circuit
JPS6459939A (en) Semiconductor device
JPS5459078A (en) Manufacture of semiconductor device
JPS56110260A (en) Semiconductor device
JPS6235540A (en) Semiconductor device
JPS59208856A (en) Multilayer interconnection
JPS57160156A (en) Semiconductor device
JPS58191449A (en) Multilayer wiring structure