JPS6235540A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS6235540A JPS6235540A JP17480485A JP17480485A JPS6235540A JP S6235540 A JPS6235540 A JP S6235540A JP 17480485 A JP17480485 A JP 17480485A JP 17480485 A JP17480485 A JP 17480485A JP S6235540 A JPS6235540 A JP S6235540A
- Authority
- JP
- Japan
- Prior art keywords
- melting point
- high melting
- point metal
- wiring
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Electrodes Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、ＬＳＩの高集積化及び高信頼性を可能にする
半導体装置に関する。特に微細パターニング配線や多層
配線を持つＬＳＩにおいて有効である。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device that enables high integration and high reliability of LSI. This is particularly effective in LSIs having fine patterned wiring or multilayer wiring.
本発明け、半導体素子を接続する配線が、ルま几はＡＬ
−ｓｆｆｌからなり該ＡＬまたはＡＬ−８ｉ上には高融
照会Ｍが形成され、コンタクトホール及びスルーホール
には高融点金属ｈｔ埋め込まれてなる半導体装置に関す
る。According to the present invention, the wiring connecting semiconductor elements is AL
-sffl, a high melting point metal M is formed on the AL or AL-8i, and a high melting point metal HT is embedded in the contact hole and through hole.
従来のＬＳＩにおいて、半導体を接続する配線はＡＬま
次けＡＬ−Ｆ３ｉの単層構造で形成されてい友。In conventional LSIs, wiring connecting semiconductors is formed in a single layer structure of AL-F3i followed by AL.
しかしながらＬ１２工の高集積化に伴い、配線及びコン
タクト穴が微細化されるため、特ＫＭ差部でのＡＬ配線
の断面積（幅×厚さ）が小さくなり、従来技術では断線
やエレクトロマイグレーションによる配線不良が増加す
るという欠点があっ之。However, as the integration of L12 becomes higher, the wiring and contact holes become finer, so the cross-sectional area (width x thickness) of the AL wiring at the special KM difference becomes smaller, and conventional technology The drawback is that wiring defects increase.
〔発明が解決しようとする問題点及び目的〕本発明は、
このような従来の欠点を解決するもので、その目的とす
るところは、微細パターニングからなるＶＬＳＩにおい
て、断線がなく、耐エレクトーマイグレーシ冒ンに優れ
之配線を持つ半導体装置を提供することである。[Problems and objects to be solved by the invention] The present invention has the following problems:
This method solves these conventional drawbacks, and its purpose is to provide a semiconductor device that has interconnects that are free from disconnection and have excellent resistance to electromigration in VLSIs that are made of fine patterning. .
本発明の半導体装置は、コンタクトま友はスルー・ホー
ルだけ高融点金属ｈｔ埋め込まれ、配線がＡＬまたけＡ
Ｌ−８？：と高融点金属の２層構造を持つことを特徴と
する。In the semiconductor device of the present invention, only the through hole of the contact is filled with high melting point metal, and the wiring straddles the AL.
L-8? : It is characterized by having a two-layer structure of high melting point metal.
本発明の作用を述べれば、コンタクトオよびスルーφホ
ールに埋め込まれる高融点金属は、微細パターニングの
表面が最も急激に変化する断差部領域のコンタクトおよ
びスルー・ホールを平坦にする効果を持つ。まｔ配線の
下層部のＡＬま几はＡＩＪ −ｓｉは、配線の下地Ｓ＜
Ｏ２との密着性に優れ、低い比抵抗を持つため、下地
との密着性に優れ、かつ低抵抗の配線を提供する。配線
の上層部の高融点金属は、耐エレクトロ・マイグレーシ
ョンに優れ、配線のマイグレーションを防ぐ。To describe the effect of the present invention, the high melting point metal embedded in the contact holes and through holes has the effect of flattening the contacts and through holes in the gap region where the fine patterning surface changes most rapidly. The AL layer of the lower layer of the wiring is AIJ-si, the wiring base S<
Since it has excellent adhesion with O2 and low specific resistance, it provides wiring with excellent adhesion to the base and low resistance. The high melting point metal in the upper layer of the wiring has excellent electromigration resistance and prevents wiring migration.
第１図は１本発明の実施例における半導体装置の断面図
である。シリコン基板１の不純物拡散層３と眉間絶縁膜
２を形成後、コンタクト・ホールを形成し、該コンタク
ト・ホールを選択的にＷなどの高融点金属４で埋め込ん
だ後、肚層５と高融点金属層６から成る配線を形成して
いる。FIG. 1 is a sectional view of a semiconductor device according to an embodiment of the present invention. After forming the impurity diffusion layer 3 and the glabellar insulating film 2 of the silicon substrate 1, a contact hole is formed, and the contact hole is selectively filled with a high melting point metal 4 such as W. A wiring made of metal layer 6 is formed.
本発明の半導体装置によれば、コンタクト・ホールの断
差部は、高融点金属で埋め込まれ平坦化されている几め
配線が細らない。ま念、下地の眉間絶縁膜と配線下層の
ＡＬの密着性は良好で、耐エレクトロ・マイグレーグ１
ンについては配線上層の高融点金属により配線のマイグ
レーションを防ぐことｈ″−可能になる。従って、本発
明によれば断線Ｍなく耐エレクトロマイグレーションに
優れ之配線を持つ半導体装置を提供する。According to the semiconductor device of the present invention, the narrowed interconnection, which is filled with a high melting point metal and flattened, does not become narrow in the gap of the contact hole. Please note that the adhesion between the underlying glabellar insulating film and the underlying wiring layer is good, making it resistant to electro-migration 1.
Regarding the wiring, migration of the wiring can be prevented by using the high melting point metal in the upper layer of the wiring. Therefore, according to the present invention, a semiconductor device having wiring which is free from disconnection M and has excellent electromigration resistance is provided.
第１図・・本発明による配線構造を持つ半導体装置の２
Ｆ１面図。
１・・・・・・シリコン基板
２・・・・・・眉間絶縁膜
３・・・・・・不純物拡散層
４・・・・・・高融点金属
５・・・・・・ＡＬまたけＡＬ−Ｂｉ
６・・・・・・高融点金属
以 上Figure 1: 2 of a semiconductor device having a wiring structure according to the present invention
F1 view. 1... Silicon substrate 2... Glabella insulating film 3... Impurity diffusion layer 4... High melting point metal 5... AL straddling AL -Bi 6...High melting point metal or higher
Claims (1)
層がＡＬまたはＡＬ−Ｓｉからなり、該ＡＬまたはＡＬ
−Ｓｉ上には高融点金属が形成された２層構造を持ち、
層間絶縁膜を通して配線を接続するコンタクトホール及
びスルーホールには高融点金属が埋め込まれていること
を特徴とする半導体装置。In an integrated circuit, the wiring connecting semiconductor elements has a bottom layer made of AL or AL-Si;
-Has a two-layer structure with high melting point metal formed on Si,
A semiconductor device characterized in that contact holes and through holes for connecting wiring through an interlayer insulating film are filled with a high melting point metal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17480485A JPS6235540A (en) | 1985-08-08 | 1985-08-08 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17480485A JPS6235540A (en) | 1985-08-08 | 1985-08-08 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6235540A true JPS6235540A (en) | 1987-02-16 |
Family
ID=15984952
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17480485A Pending JPS6235540A (en) | 1985-08-08 | 1985-08-08 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6235540A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01161735A (en) * | 1987-12-18 | 1989-06-26 | Toshiba Corp | Semiconductor device |
| JP2008078396A (en) * | 2006-09-21 | 2008-04-03 | Nec Electronics Corp | Semiconductor device |
-
1985
- 1985-08-08 JP JP17480485A patent/JPS6235540A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01161735A (en) * | 1987-12-18 | 1989-06-26 | Toshiba Corp | Semiconductor device |
| JP2008078396A (en) * | 2006-09-21 | 2008-04-03 | Nec Electronics Corp | Semiconductor device |
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