JPS554965A - Semiconductor - Google Patents

Abstract

PURPOSE: To make the first layer of the multi-layer wiring to be formed on a semiconductor, of the polycrystalline Si layer on which impurity is doped and a high- melting-point metal or a silicide thereof deposited on said Si layer for raising the voltage resistance of the interface thereof with the second layer to be formed thereon.

CONSTITUTION: SiO₂ film 8 is fitted on the surface of the P-type Si substrate 1 on which an N⁺-type bury range 2, an N-type layer 3 which serves as collector, a P-type base range 4, an N⁺-type emitter range 5, an N⁺-type collector take-out range 6, and a P⁺-type separation range 7, and openings are provided at said ranges 4W6. Next, the polycrystalline Si layer 9 which makes first layer wiring is deposited over the whole surface of said substrate 1, and PSG layer 10 is formed only at said ranges 5 and 6. Thereafter, the whole surface of said substrate 1 is covered with BSG layer 11, the impurity in said layers 10 and 11 is diffused through heat-treatment, and the required portions of said pollycrystalline layer 9 are made of N- and P-type respectively. Next, said layers 10 and 11 are removed, MoSi layer 12 is deposited on said layer 9, covering is made with SiO₂ film 13, openings are provided, and Al second wiring layer 14 is deposited.

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