JPS5648164A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS5648164A
JPS5648164A JP12358679A JP12358679A JPS5648164A JP S5648164 A JPS5648164 A JP S5648164A JP 12358679 A JP12358679 A JP 12358679A JP 12358679 A JP12358679 A JP 12358679A JP S5648164 A JPS5648164 A JP S5648164A
Authority
JP
Japan
Prior art keywords
region
type
resistance
polycrystalline silicon
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12358679A
Other languages
Japanese (ja)
Inventor
Naotoshi Higashiyama
Koichi Fukaya
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP12358679A priority Critical patent/JPS5648164A/en
Publication of JPS5648164A publication Critical patent/JPS5648164A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0688Integrated circuits having a three-dimensional layout

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Non-Adjustable Resistors (AREA)

Abstract

PURPOSE:To conform the temperature coefficient of a resistance element to that of an external metal coating resistor connected to it, when forming the resistance ele- ment consisting of polycrystalline silicon on the same semiconductor substrate on which an IC is provided, by controlling the temperature coefficient of the resistance value of the element with the value of the layer resistance of the polycrystalline silicon. CONSTITUTION:On a P type silicon substrate 1, an N type buried region 2 is diffu- sion formed, and all over the surface including the region, an N type layer 3 is epitaxially grown, and the layer 3 is divided into islands with plural P<+> type insulating and separating regions 4. Next, in an island region including the region 2, a P type base region 5 is diffusion formed, and in the region, an N<+> type emitter region 6 is formed, and neighboring the region 5, an N<+> type ohmic connecting region 7 is diffusion formed. Then the entire surface is covered with an insulating film 10, and above another island region, a polycrystalline silicon resistance element 8 is grown via the film 10 and connected to the region 6 with aluminum wiring 9. In this construction, the layer resistance of the polycrystalline silicon is selected to 70- 150OMEGA/square to match with an external resistor.
JP12358679A 1979-09-26 1979-09-26 Semiconductor device Pending JPS5648164A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12358679A JPS5648164A (en) 1979-09-26 1979-09-26 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12358679A JPS5648164A (en) 1979-09-26 1979-09-26 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS5648164A true JPS5648164A (en) 1981-05-01

Family

ID=14864252

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12358679A Pending JPS5648164A (en) 1979-09-26 1979-09-26 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS5648164A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06507107A (en) * 1992-03-19 1994-08-11 サムソナイト コーポレイション Luggage bag with intelligent opening mechanism

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS503793A (en) * 1973-05-15 1975-01-16

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS503793A (en) * 1973-05-15 1975-01-16

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06507107A (en) * 1992-03-19 1994-08-11 サムソナイト コーポレイション Luggage bag with intelligent opening mechanism

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