JP2004063610A - Manufacturing method of semiconductor device - Google Patents

Manufacturing method of semiconductor device Download PDF

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Publication number
JP2004063610A
JP2004063610A JP2002217632A JP2002217632A JP2004063610A JP 2004063610 A JP2004063610 A JP 2004063610A JP 2002217632 A JP2002217632 A JP 2002217632A JP 2002217632 A JP2002217632 A JP 2002217632A JP 2004063610 A JP2004063610 A JP 2004063610A
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Japan
Prior art keywords
film
layer
aluminum wiring
aluminum
interlayer insulating
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JP2002217632A
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Japanese (ja)
Inventor
Yoshitaka Sone
曽根　義隆
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Seiko Instruments Inc
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Seiko Instruments Inc
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Publication of JP2004063610A publication Critical patent/JP2004063610A/en
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Abstract

<P>PROBLEM TO BE SOLVED: To prevent factors of causing wiring crack, void and broken line in the formation of a wiring at an upper layer part of metallic wires by eliminating a step difference of an inter-layer insulation film covering the metallic wires in the case of forming the metallic wires made of a thick aluminum film on a semiconductor substrate. <P>SOLUTION: A barrier metallic layer and an aluminum film are formed as a first layer on the semiconductor substrate by sputtering or CVD to form aluminum wires through selective etching by using a resist mask and a reactant gas. The inter-layer insulation film is formed on the aluminum wires, an embedding film is coated on a step difference to fill in the step difference, and etch-back is applied to them by using the reactant gas to expose the upper part of the first layer aluminum wires. The aluminum film is similarly formed as second layer aluminum wires in this state, the resist is drawn in a way that the second layer aluminum wires are overlapped on the first layer aluminum wires by using a resist film for a mask, and the first layer aluminum wires and the second layer aluminum wires are joined at the same time the second layer aluminum wires are formed through selective etching by using the reactant gas. <P>COPYRIGHT: (C)2004,JPO

Description

【０００１】
【発明の属する技術分野】
本発明は、半導体装置においてアルミ配線とその上に形成される層間絶縁膜を平坦性良く加工する方法で、特に加工したアルミ配線のアルミ膜厚が厚くても平坦性を損なわずに形成され、配線の信頼性向上を目的とした形成方法に関するものである。
【０００２】
【従来の技術】
従来、半導体装置の製造工程において、半導体基板１０３上にレイアウトの異なる膜厚１００００Å程度のアルミ配線を多層配線で形成する場合を以下に説明する。半導体基板１０３上にバリアメタル１０１を介して形成された下層（第１層目の）アルミ配線１０２上と、その上に形成された層間絶縁膜１０４を平坦化してスルーホールを介して層間絶縁膜上に形成された上層（第２層の）アルミ配線１０６と接続する。
【０００３】
しかしながら、図１に示す様に下層アルミ配線１０２のアルミ膜厚を２００００Å以上に厚くし、アスペクト比（膜厚／配線幅）が高い（２以上）アルミ配線であった場合、下層アルミ配線１０２を被覆する層間絶縁膜１０４は下層アルミ配線１０２のアスペクト比が高いために段差Ｂが生じてしまう。
【０００４】
このような状態で上層アルミ配線１０６を形成すると、上層アルミ配線１０６は層間絶縁膜１０４に生じた段差Ｂによって、アルミカバレッジの悪い事による配線クラックＡ、ボイド、断線等が生じ、配線の信頼性低下の大きな要因となっていた。
【０００５】
【発明が解決しようとする課題】
本発明は、半導体基板上に厚い第一層目アルミニウム膜（２００００Å以上）を金属配線として形成した際、その段差により被覆される層間絶縁膜の段差を取り除く事で、その上層部での配線形成における配線クラック、ボイド、断線の要因を取り除き、高信頼性を有する平坦化配線加工プロセスを提供することである。
【０００６】
【課題を解決するための手段】
本発明は、（１）半導体基板上の１層目にバリアメタル層及びアルミニウムまたはアルミニウム合金をスパッタもしくはＣＶＤで成膜し、レジストマスクにてＣｌ２系反応ガスを用いて選択エッチングでアルミ配線形成する工程と、（２）前記アルミ配線上に層間絶縁膜を成膜し、段差部分を埋め込み膜（ＳＯＧ膜）で塗布して段差を埋める工程と、（３）前記層間絶縁膜と前記埋め込み膜（ＳＯＧ膜）をＣＦ４系反応ガスを用いてエッチバックし１層目アルミ配線上部を露出させる工程と、（４）前記３、１層目アルミ配線上部が露出した状態で、２層目にアルミニウムまたはアルミニウム合金をスパッタもしくはＣＶＤで成膜し、レジスト膜をマスクとして２層目アルミ配線が１層目アルミ配線と重ね合わさる様にする描画工程と、（５）前記４、ＣＬ２系反応ガスを用いて選択エッチングで２層目アルミ配線形成する工程と同時に１層目アルミ配線と２層目アルミ配線が接続する工程と、（６）前記５、２層目アルミ配線上に層間絶縁膜を成膜し、また、段差部分を埋め込み膜（ＳＯＧ膜）で塗布して段差を埋める工程とを含むことを特徴とする半導体装置の製造方法に関する。
【０００７】
さらに本発明は、前記（２）〜（６）から工程を繰り返し行い、請求項１記載よりもアルミ配線を積層に形成する事でアルミ配線の膜厚を厚くさせることと同時にアルミ配線のアルミ膜厚が厚くなっても層間絶縁膜の平坦性を損なわずに形成可能を特徴とする半導体装置の製造方法に関する。
【０００８】
【実施例】
次に本発明について図面を用いて説明する。図２及び図３は、半導体基板２０３上に形成されたアルミ配線のアルミ膜厚を厚くしても、段差が平坦な状態で形成可能な製造工程の工程断面図を示すものである。
【０００９】
図２（ａ）は、半導体基板２０３上に、バリアメタル層２０２（ａ）を形成し、その上部にアルミニウム膜２０２（ｂ）を成膜する。バリアメタル層２０２（ａ）及びアルミニウム膜２０２（ｂ）はスパッタ法もしくはＣＶＤ法を用いて順次成膜し、第１のレジスト２０１をマスクとしてＣｌ２系反応ガスを用いた選択ドライエッチングによりアルミ配線２０２を形成した段階における構造断面図である。Ｃｌ２系の反応ガスとしては、例えばＣｌ２、ＢＣｌ３等がある。バリアメタル層２０２（ａ）は、半導体基板３０２側に密着層層としてのＴｉ５００Å膜の上に形成されている。バリアメタル層２０２（ａ）として、ＴｉＮ１０００Åが形成される。その上のアルミニウム膜２０２（ｂ）の膜厚は１００００Åである。それらを第１層目アルミ配線２０２とする。
【００１０】
図２（ｂ）は、第１層目アルミ配線２０２をパターニングした後、レジストアッシング装置を用いて、酸素プラズマによりレジストを灰化処理して、第１のレジストを除去した後の構造断面図である。
【００１１】
図２（ｃ）は、半導体基板２０３及び図２（ａ）で形成されたアルミ配線２０２を被覆する様に第１の層間絶縁膜２０４（ａ）をＣＶＤ法を用いて成膜した構造断面図である。第１の層間絶縁膜２０４（ａ）については、通常用いられるＳｉＯ２膜、ＢＰＳＧ膜またはＰＳＧ膜等が挙げられ、膜厚は８０００Å程度である。更に、ＴＥＯＳ膜も用いられる。
【００１２】
図２（ｄ）は、図２（ｃ）で成膜した層間絶縁膜２０４（ａ）の段差部分を埋め込む様にスピンコートで第１の埋め込み膜（ＳＯＧ膜）２０４（ｂ）を塗布した構造断面図である。第１の埋め込み膜（ＳＯＧ膜）２０４（ｂ）の膜厚は６０００Å程度である。
【００１３】
図２（ｅ）は、層間絶縁膜２０４（ａ）と段差埋め込み用に使用した第１の埋め込み膜（ＳＯＧ膜）２０４（ｂ）は、ＣＦ４系反応ガスを用いて全面エッチバックを行い、図２（ａ）で形成されたアルミ配線２０２の上部Ｃだけ露出させた状態の構造断面図である。この際、アルミ配線２０２の上部は露出させるが、層間絶縁膜２０４（ａ）の段差部分（凹部）を埋め込んだ第１の埋め込み膜（ＳＯＧ膜）２０４（ｂ）がこのエッチバックにより、再度段差（凹部）が発生しない様に、エッチング装置のＲＦパワーや圧力を低く設定する必要がある。
【００１４】
図２（ｆ）は、図２（ａ）から図２（ｅ）で形成されたアルミ配線２０２及び層間絶縁膜２０４（ａ）と埋め込み膜２０４（ｂ）上に第２層目アルミニウム膜２０５をスパッタ法もしくはＣＶＤ法を用いて成膜し、同時に下層のアルミ配線２０２と接続した構造断面図である。この第２層目アルミニウム膜２０５の膜厚は、１００００Å程度である。
【００１５】
図２（ｇ）は、第１層目（下層）のアルミ配線２０２とレジスト２０６が重ね合うように描画し、第２のレジスト２０６をマスクとして、Ｃｌ２系反応ガスを用いた選択ドライエッチングにより第１層目（下層）のアルミ配線２０２と第２層目（上層）のアルミ配線２０７が上下で接続した事により、アルミ配線のトータル膜厚は２００００Åとなり、同じ配線幅で厚いアルミ配線が形成される。この時レジスト２０６の現像時における線幅は、重ね合わせ誤差も考慮に入れ、第１層目（下層）のアルミ配線２０２より少し線幅を太くした方が望ましい。
【００１６】
図２（ｈ）は、図２（ｉ）でアルミ配線を形成した後、レジストアッシング装置を用いて、酸素プラズマによりレジストを灰化処理した後の構造断面図である。
【００１７】
図３（ｉ）は、図２（ｈ）で形成されたアルミ配線２０７を被覆する様に第２の層間絶縁膜２０８（ａ）をＣＶＤ法を用いて成膜した構造断面図である。
【００１８】
図３（ｊ）は、図３（ｉ）で成膜した第２の層間絶縁膜２０８（ａ）の段差部分を埋め込むようにスピンコートでＳＯＧ膜２０８（ｂ）を塗布した構造断面図である。この第２の埋め込み膜（ＳＯＧ膜）２０８（ｂ）の膜厚は６０００Å程度である。
【００１９】
図３（ｋ）は、層間絶縁膜２０８（ａ）と段差埋め込み用に使用した埋め込み膜（ＳＯＧ膜）２０８（ｂ）は、ＣＦ４系反応ガスを用いて全面エッチバックを行い、図３（ｊ）で形成された第２層目アルミ配線の上部だけ露出させた状態の構造断面図である。
【００２０】
図３（ｌ）は、図３（ｋ）で段差が極めて少なくなった第２の層間絶縁膜２０８（ａ）と第２の埋め込み膜（ＳＯＧ膜）２０８（ｂ）の上部に第３の層間絶縁膜２０９をＣＶＤ法で成膜した構造断面図である。
【００２１】
図３（ｍ）は、図３（ｌ）で成膜された層間絶縁膜上に第３のアルミニウム膜２０９を成膜した構造断面図である。図３（ｍ）に示す様に、図２（ａ）〜（ｈ）と図３（ｉ）〜（ｍ）の方法を用いて層間絶縁膜の段差を減らす事で、膜厚の厚いアルミ配線においても平坦性が良好に確保でき、その上部の形成される第３のアルミニウム膜２０９を形成した場合、クラック、ボイド、断線が起きない多層配線が可能である。
【００２２】
【発明の効果】
以上説明したように、本発明の特徴は半導体基板上に１００００Å厚のアルミ配線を形成し、そのアルミ配線を層間絶縁膜と埋め込み膜（ＳＯＧ膜）で被覆し、ドライエッチングにてエッチバックを行い、層間絶縁膜の段差を無くすと同時に下層のアルミ配線の上部を露出させ、更に上層の１００００Åアルミ配線を下層のアルミ配線とが重なり合う様に配線加工及び金属接続させ、その上層のアルミ配線を再度、層間絶縁膜と埋め込み膜（ＳＯＧ膜）で被覆し、ドライエッチングにてエッチバックを行う事で膜厚が厚いアルミ配線においても、それを被覆する層間絶縁膜の段差を取り除かれる。
【００２３】
したがって、本発明を利用すれば厚膜アルミ配線上部に形成されるアルミ配線の信頼性の向上を図ることができる。
【図面の簡単な説明】
【図１】従来工法による半導体装置のアルミニウム配線部分の断面図である。
【図２】本発明の実施形態にかかるアルミニウム配線における平坦化製造工程の工程の断面図である。
【図３】図２に示した工程に引き続く工程の断面図である。本発明の実施形態にかかるアルミニウム配線における平坦化製造工程の工程断面図である。[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention is a method of processing an aluminum wiring and an interlayer insulating film formed thereon with good flatness in a semiconductor device, and is particularly formed without impairing the flatness even if the processed aluminum wiring has a large aluminum film thickness. The present invention relates to a forming method for improving the reliability of wiring.
[0002]
[Prior art]
Conventionally, in a manufacturing process of a semiconductor device, a case in which aluminum wirings having different layouts and a thickness of about 10,000 ° are formed as multilayer wirings on a semiconductor substrate 103 will be described below. A lower layer (first layer) aluminum wiring 102 formed on a semiconductor substrate 103 via a barrier metal 101 and an interlayer insulating film 104 formed thereon are planarized to form an interlayer insulating film via a through hole. It is connected to an upper layer (second layer) aluminum wiring 106 formed thereon.
[0003]
However, as shown in FIG. 1, when the aluminum film thickness of the lower aluminum wiring 102 is increased to 20,000 ° or more and the aluminum wiring has a high aspect ratio (film thickness / wiring width) (2 or more), the lower aluminum wiring 102 is In the interlayer insulating film 104 to be covered, a step B occurs because the aspect ratio of the lower aluminum wiring 102 is high.
[0004]
When the upper aluminum wiring 106 is formed in such a state, the upper aluminum wiring 106 has wiring cracks A, voids, disconnections, etc. due to poor aluminum coverage due to steps B formed in the interlayer insulating film 104, and the reliability of the wiring is reduced. This was a major factor in the decline.
[0005]
[Problems to be solved by the invention]
According to the present invention, when a thick first-layer aluminum film (20,000 ° or more) is formed as a metal wiring on a semiconductor substrate, the wiring is formed in the upper layer by removing the step of the interlayer insulating film covered by the step. And to provide a highly reliable flattened wiring processing process by removing the causes of wiring cracks, voids, and disconnections.
[0006]
[Means for Solving the Problems]
According to the present invention, (1) a barrier metal layer and aluminum or an aluminum alloy are formed as a first layer on a semiconductor substrate by sputtering or CVD, and aluminum wiring is formed by selective etching using a Cl 2 -based reaction gas with a resist mask. (2) a step of forming an interlayer insulating film on the aluminum wiring and applying a step portion with a filling film (SOG film) to fill the step; and (3) a step of filling the step with the interlayer insulating film and the filling film ( Etching back the SOG film using a CF 4 -based reaction gas to expose the upper part of the first layer aluminum wiring; and (4) aluminum or aluminum in the second layer with the upper part of the third layer aluminum wiring exposed. A drawing step in which an aluminum alloy is formed by sputtering or CVD, and the second layer aluminum wiring is overlapped with the first layer aluminum wiring using a resist film as a mask; (4) the step of connecting the first-layer aluminum wiring and the second-layer aluminum wiring simultaneously with the step of forming the second-layer aluminum wiring by selective etching using the CL2-based reaction gas; and (6) the fifth- and second-layer aluminum wiring. Forming an interlayer insulating film on the wiring and applying a step portion with a filling film (SOG film) to fill the step.
[0007]
Further, in the present invention, the steps from (2) to (6) are repeated, and the thickness of the aluminum wiring is increased by forming the aluminum wiring in a laminated manner as compared with claim 1, and at the same time, the aluminum film of the aluminum wiring is formed. The present invention relates to a method for manufacturing a semiconductor device, which can be formed without deteriorating the flatness of an interlayer insulating film even when the thickness increases.
[0008]
【Example】
Next, the present invention will be described with reference to the drawings. FIGS. 2 and 3 are process cross-sectional views of a manufacturing process in which even if the aluminum film thickness of the aluminum wiring formed on the semiconductor substrate 203 is increased, a step can be formed in a flat state.
[0009]
2A, a barrier metal layer 202 (a) is formed on a semiconductor substrate 203, and an aluminum film 202 (b) is formed thereon. The barrier metal layer 202 (a) and the aluminum film 202 (b) are sequentially formed by a sputtering method or a CVD method, and aluminum wiring is formed by selective dry etching using a first resist 201 as a mask and a Cl 2 -based reaction gas. FIG. 4 is a structural cross-sectional view at a stage when a 202 is formed. Examples of the Cl 2 -based reaction gas include Cl 2 and BCl 3 . The barrier metal layer 202 (a) is formed on the Ti500 film as an adhesion layer on the semiconductor substrate 302 side. TiN 1000 # is formed as barrier metal layer 202 (a). The film thickness of the aluminum film 202 (b) thereon is 10,000 °. These are referred to as first-layer aluminum wiring 202.
[0010]
FIG. 2B is a cross-sectional view of the structure after the first layer aluminum wiring 202 is patterned, the resist is ashed by oxygen plasma using a resist ashing apparatus, and the first resist is removed. is there.
[0011]
FIG. 2C is a cross-sectional view showing a structure in which a first interlayer insulating film 204 (a) is formed by a CVD method so as to cover the semiconductor substrate 203 and the aluminum wiring 202 formed in FIG. 2A. It is. As the first interlayer insulating film 204 (a), a SiO 2 film, a BPSG film, a PSG film, or the like, which is generally used, may be used, and the film thickness is about 8000 °. Further, a TEOS film is also used.
[0012]
FIG. 2D shows a structure in which a first buried film (SOG film) 204 (b) is applied by spin coating so as to bury a step portion of the interlayer insulating film 204 (a) formed in FIG. 2 (c). It is sectional drawing. The thickness of the first buried film (SOG film) 204 (b) is about 6000 °.
[0013]
FIG. 2E shows that the entire surface of the interlayer insulating film 204 (a) and the first buried film (SOG film) 204 (b) used for filling the step are etched back using a CF 4 -based reaction gas. FIG. 3 is a structural sectional view showing a state in which only an upper part C of an aluminum wiring 202 formed in FIG. 2A is exposed. At this time, the upper portion of the aluminum wiring 202 is exposed, but the first buried film (SOG film) 204 (b) in which the step portion (concave portion) of the interlayer insulating film 204 (a) is buried is formed again by this etch back. It is necessary to set the RF power and pressure of the etching apparatus low so that (recess) does not occur.
[0014]
FIG. 2F shows a second-layer aluminum film 205 formed on the aluminum wiring 202, the interlayer insulating film 204 (a), and the buried film 204 (b) formed in FIGS. 2A to 2E. FIG. 4 is a structural cross-sectional view in which a film is formed by a sputtering method or a CVD method and is simultaneously connected to an aluminum wiring 202 in a lower layer. The thickness of the second aluminum film 205 is about 10000 °.
[0015]
In FIG. 2G, the first layer (lower layer) aluminum wiring 202 and the resist 206 are drawn so as to overlap with each other, and the second resist 206 is used as a mask for selective dry etching using a Cl 2 -based reaction gas. Since the aluminum wiring 202 of the first layer (lower layer) and the aluminum wiring 207 of the second layer (upper layer) are connected vertically, the total thickness of the aluminum wiring becomes 20000 mm, and a thick aluminum wiring having the same wiring width is formed. You. At this time, it is preferable that the line width at the time of development of the resist 206 is slightly larger than the aluminum wiring 202 of the first layer (lower layer) in consideration of the overlay error.
[0016]
FIG. 2H is a structural cross-sectional view after the aluminum wiring is formed in FIG. 2I and the resist is ashed by oxygen plasma using a resist ashing apparatus.
[0017]
FIG. 3I is a structural cross-sectional view in which a second interlayer insulating film 208 (a) is formed by a CVD method so as to cover the aluminum wiring 207 formed in FIG. 2H.
[0018]
FIG. 3J is a structural cross-sectional view in which the SOG film 208 (b) is applied by spin coating so as to fill a step portion of the second interlayer insulating film 208 (a) formed in FIG. 3 (i). . The thickness of the second buried film (SOG film) 208 (b) is about 6000 °.
[0019]
FIG. 3 (k) shows that the interlayer insulating film 208 (a) and the buried film (SOG film) 208 (b) used for filling the step are etched back over the entire surface using a CF 4 -based reaction gas. FIG. 10 is a structural cross-sectional view showing a state where only an upper portion of a second-layer aluminum wiring formed in j) is exposed.
[0020]
FIG. 3 (l) shows a third interlayer insulating film 208 (a) and a second buried film (SOG film) 208 (b) on which the steps are extremely reduced in FIG. 3 (k). FIG. 4 is a structural cross-sectional view in which an insulating film 209 is formed by a CVD method.
[0021]
FIG. 3M is a cross-sectional view showing a structure in which a third aluminum film 209 is formed on the interlayer insulating film formed in FIG. As shown in FIG. 3 (m), by using the method of FIGS. 2 (a) to 2 (h) and FIGS. 3 (i) to 3 (m) to reduce the step of the interlayer insulating film, a thick aluminum wiring In this case, good flatness can be ensured, and when the third aluminum film 209 formed on the top is formed, a multilayer wiring free from cracks, voids, and disconnections can be obtained.
[0022]
【The invention's effect】
As described above, the feature of the present invention is that an aluminum wiring having a thickness of 10,000 mm is formed on a semiconductor substrate, the aluminum wiring is covered with an interlayer insulating film and a buried film (SOG film), and etched back by dry etching. At the same time, removing the step in the interlayer insulating film, exposing the upper part of the lower aluminum wiring, making the upper 10000 mm aluminum wiring wiring and metal connection so that the lower aluminum wiring overlaps, and reconnecting the upper aluminum wiring again By covering with an interlayer insulating film and a buried film (SOG film) and performing etch-back by dry etching, a step of the interlayer insulating film covering the thick aluminum wiring is removed.
[0023]
Therefore, by using the present invention, the reliability of the aluminum wiring formed above the thick film aluminum wiring can be improved.
[Brief description of the drawings]
FIG. 1 is a sectional view of an aluminum wiring portion of a semiconductor device manufactured by a conventional method.
FIG. 2 is a cross-sectional view of a flattening manufacturing process of the aluminum wiring according to the embodiment of the present invention.
FIG. 3 is a sectional view of a step that follows the step of FIG. 2; FIG. 6 is a process cross-sectional view of a flattening manufacturing process for the aluminum wiring according to the embodiment of the present invention.

Claims (6)

半導体基板上に第１層アルミ配線としてバリアメタル層及びアルミニウムまたはアルミニウム合金をスパッタもしくはＣＶＤで成膜し、レジストマスクにてＣｌ２系反応ガスを用いて選択エッチングでアルミ配線形成する第１工程と、
前記第一層目アルミ配線上に層間絶縁膜を成膜し、段差部分を埋め込み膜（ＳＯＧ膜）で塗布して段差を埋める第２工程と、
前記層間絶縁膜と前記埋め込み膜（ＳＯＧ膜）をＣＦ４系反応ガスを用いてエッチバックし、前記１層目アルミ配線上部を露出させる第３工程と、
前記１層目アルミ配線上部が露出した状態で、２層目にアルミニウムまたはアルミニウム合金をスパッタもしくはＣＶＤで成膜し、レジスト膜をマスクとして２層目アルミ配線が１層目アルミ配線と重ね合わさる様にする描画の第４工程と、
ＣＬ２系反応ガスを用いて選択エッチングで前記２層目アルミ配線形成する工程と同時に前記１層目アルミ配線と前記２層目アルミ配線が接続する第５工程と、
前記２層目アルミ配線上に層間絶縁膜を成膜し、また、段差部分を埋め込み膜（ＳＯＧ膜）で塗布して段差を埋める第６工程とを含むことを特徴とする半導体装置の製造方法。A first step of forming a barrier metal layer and aluminum or an aluminum alloy as a first layer aluminum wiring on a semiconductor substrate by sputtering or CVD, and forming an aluminum wiring by selective etching using a Cl 2 -based reaction gas with a resist mask; ,
A second step of forming an interlayer insulating film on the first-layer aluminum wiring and filling a step portion with a filling film (SOG film) to fill the step;
A third step of etching back the interlayer insulating film and the buried film (SOG film) using a CF 4 -based reaction gas to expose an upper portion of the first-layer aluminum wiring;
With the upper portion of the first layer aluminum wiring exposed, aluminum or an aluminum alloy is formed as a second layer by sputtering or CVD, and the second layer aluminum wiring is overlapped with the first layer aluminum wiring using a resist film as a mask. A fourth step of drawing,
A fifth step of connecting the first layer aluminum wiring and the second layer aluminum wiring simultaneously with the step of forming the second layer aluminum wiring by selective etching using a CL2-based reaction gas;
Forming a interlayer insulating film on the second-level aluminum wiring, and filling the step with a buried film (SOG film) to fill the step. . 前記第２工程〜第６工程を繰り返し行い、前記アルミ配線を積層に形成する事でアルミ配線の膜厚を厚くさせることと同時に前記アルミ配線のアルミ膜厚が厚くなっても層間絶縁膜の平坦性を損なわずに形成可能を特徴とする請求項１記載の半導体装置の製造方法。The second to sixth steps are repeated to increase the thickness of the aluminum wiring by forming the aluminum wiring in a laminated manner, and at the same time, even if the aluminum thickness of the aluminum wiring increases, the interlayer insulating film becomes flat. 2. The method for manufacturing a semiconductor device according to claim 1, wherein the semiconductor device can be formed without impairing the performance. 前記第１工程のバリアメタル層がＴｉＮ／Ｔｉ膜であることを特徴とする請求項１記載の半導体装置の製造方法。2. The method according to claim 1, wherein the barrier metal layer in the first step is a TiN / Ti film. 前記工程２の層間絶縁膜が、ＳｉＯ２膜、ＳｉＯＮ膜、ＢＰＳＧ膜、又はＴＥＯＳ膜であることを特徴とする請求項１記載の半導体装置の製造方法。2. The method according to claim 1, wherein the interlayer insulating film in the step 2 is a SiO2 film, a SiON film, a BPSG film, or a TEOS film. 前記工程３及び工程６の層間絶縁膜上に埋める膜が、埋め込み膜はＳＯＧ膜であることを特徴とする請求項１記載の半導体装置の製造方法。2. The method of manufacturing a semiconductor device according to claim 1, wherein the film to be buried on the interlayer insulating film in the step 3 and the step 6 is an SOG film. 前記工程６の層間絶縁膜が、ＳｉＯ２膜、ＳｉＯＮ膜、ＢＰＳＧ膜、又はＴＥＯＳ膜のいずれかの上もしくは最終保護膜にＳｉＮ膜が積層された構造となっていることを特徴とする請求項１記載の半導体装置の製造方法。7. The method according to claim 6, wherein the interlayer insulating film in the step 6 has a structure in which a SiN film is laminated on any one of a SiO 2 film, a SiON film, a BPSG film, and a TEOS film or on a final protective film. 2. The method for manufacturing a semiconductor device according to item 1.
JP2002217632A 2002-07-26 2002-07-26 Manufacturing method of semiconductor device Pending JP2004063610A (en)

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JPH04196486A (en) * 1990-11-28 1992-07-16 Toshiba Corp Semiconductor device
JPH0964039A (en) * 1995-08-24 1997-03-07 Sony Corp Wiring forming method
JPH1041299A (en) * 1996-07-25 1998-02-13 Nec Corp Manufacturing semiconductor device
JPH11251321A (en) * 1998-01-05 1999-09-17 Texas Instr Inc <Ti> Manufacture of conducting path between electronic components inside integrated circuit and integrated circuit

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6466955A (en) * 1987-09-07 1989-03-13 Nec Corp Semiconductor integrated circuit
JPH01140644A (en) * 1987-11-26 1989-06-01 Fujitsu Ltd Manufacture of semiconductor device
JPH04196486A (en) * 1990-11-28 1992-07-16 Toshiba Corp Semiconductor device
JPH0964039A (en) * 1995-08-24 1997-03-07 Sony Corp Wiring forming method
JPH1041299A (en) * 1996-07-25 1998-02-13 Nec Corp Manufacturing semiconductor device
JPH11251321A (en) * 1998-01-05 1999-09-17 Texas Instr Inc <Ti> Manufacture of conducting path between electronic components inside integrated circuit and integrated circuit

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