JPH0831930A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To manufacture, with good efficiency and simply, a semiconductor device whose step coverage of an interconnection at an upper layer than a connecting hole is excellent and whose reliability is high. CONSTITUTION:A Ti/TiN layer 14 and a W layer 15 are deposited, and the W layer 15 is etched wholly. A connecting hole 13 is buried with the Ti/TiN layer 14 and the W layer 15. The Ti/TiN layer 14 and the W layer 15 on an SiO2 layer 12 are overetched by an etching operation having a sputtering effect. As a result, the SiO2 layer 12 in the opening part of the connecting hole 13 is etched at higher speed due to the angle dependence of a sputtering speed, and the opening part of the connecting hole 13 is changed into a taper shape.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device in which a connection hole is filled with a metal plug.

[0002]

2. Description of the Related Art Although design rules have been reduced for higher integration and higher speed of semiconductor devices, the opening diameter of connection holes has been reduced accordingly. When the aperture diameter becomes smaller,
The aspect ratio of the connection hole increases, and the step coverage of the wiring above the connection hole deteriorates. Therefore, a structure has been considered in which the connection hole is filled with a metal plug.

3 and 4 show a conventional example of a method of manufacturing a semiconductor device in which the connection hole is filled with a metal plug in this way. In this conventional example, as shown in FIG.
Over the entire surface of the Si substrate 11 by depositing a dielectric layer such as SiO ₂ layer 12, by anisotropic etching using a patterned resist (not shown) a reactive ion etching using a mask, connected to the SiO ₂ layer 12 hole 13 To form.

In the reactive ion etching at this time, CF ₄ , CHF ₃ and Ar are supplied as etching gas at ₄ sccm, 25 sccm and 80 sccm, respectively, and high frequency power 400 W, magnetic flux 6 mT, pressure 17 Pa.
And

Next, as shown in FIG. 3B, a Ti / TiN layer 14 as an adhesion layer which also serves as a barrier metal is deposited on the entire surface. When depositing the Ti / TiN layer 14, S
The temperature of the i substrate 11 is set to 200 ° C. and Ar is set to 100 sccc.
First, a Ti film having a film thickness of 30 nm is deposited by sputtering at a pressure of 0.5 Pa and a DC power of 2 kW.

Then, the temperature of the Si substrate 11 is set to 200 ° C., N ₂ is supplied at 100 sccm, the pressure is 1 Pa, and the direct current power is 6 kW.
Of TiN film is deposited on the Ti film. After that, rapid heat treatment is performed at a temperature of 650 ° C. for the Si substrate 11 and a heating time of 30 seconds.

Next, 40 sc of WF ₆ , H ₂ and Ar are respectively added.
cm, 400 sccm, 2250 sccm, and by CVD at a pressure of 10.66 kPa, a W layer 15 having a film thickness of 600 nm is deposited on the entire surface as shown in FIG. fill in.

Next, the W layer 15 is formed by reactive ion etching.
And anisotropically etching the entire surface of the Ti / TiN layer 14,
As shown in FIG. 3D, the W layer 15 and the Ti / TiN layer 14 on the SiO ₂ layer 12 are removed, and the connection hole 13 is filled with a plug including the W layer 15 and the Ti / TiN layer 14. .

Next, as shown in FIG. 4A, a Ti layer 16 as an adhesion layer and an Al layer 17 are sequentially deposited on the entire surface, and the Al layer 17 and the Ti layer 16 are patterned, Wirings electrically connected to the Si substrate 11 via the W layer 15 in the connection hole 13 are formed.

Next, as shown in FIG. 4B, the TiN / Ti layer 21 and S serving as an antireflection film also serving as a barrier metal are formed.
sequentially depositing on the entire surface of the insulating layer of the iO such _two layers 22, by anisotropic etching using a patterned resist (not shown) reactive ion etching with a mask, the upper SiO ₂ layer of the connection hole 13 22 A connection hole 23 is formed in the.

Then, a TiN layer 2 as a barrier metal
4 and the W layer 25 are sequentially deposited on the entire surface, and the entire surface of the W layer 25 and the TiN layer 24 are anisotropically etched by reactive ion etching to form the W layer 25 and the TiN layer on the SiO ₂ layer 22.
Layer 24 is removed to remove these W layer 25 and TiN layer 24.
The connection hole 23 is filled with a plug made of. Thereafter, the conventionally known process is further executed to complete this semiconductor device.

[0012]

By the way, when anisotropically etching the entire surfaces of the W layer 15 and the Ti / TiN layer 14 by reactive ion etching, these W layers 15 are used.
And the Ti / TiN layer 14 is overetched. Therefore, as shown in FIG. 3D, the W layer 1 in the connection hole 13 is
5 and the surface of the Ti / TiN layer 14 is lower than the surface of the SiO ₂ layer 12, a plug loss occurs. Moreover, as is clear from FIG. 3 (d), the connection hole 13 has a cone-like shape whose inner peripheral wall is nearly vertical.

As a result of these, as shown in FIG.
The shape of the recess of the Al layer 17 on the connection hole 13 was steep, the step coverage of the Al layer 17 was not good, and the reliability of this semiconductor device was not high.

Further, as shown in FIG. 4B, the connection hole 13
In the case of a so-called stack contact structure in which the connection hole 23 is provided above, if the shape of the recess of the Al layer 17 on the connection hole 13 is steep, a mask alignment shift may occur during patterning of the resist for forming the connection hole 23. Halation occurs. Therefore, the shape of the connection hole 23 is not stable, and the W layer 25 and the SiO ₂ layer 22 in the connection hole 23 are not stable.
The step coverage of the wiring formed above was not good, and the reliability of the semiconductor device was not high.

[0015]

According to a first aspect of the present invention, there is provided a method of manufacturing a semiconductor device, wherein metal layers 14 and 15 are deposited on the entire surface, and a contact hole 13 provided in an insulating layer 12 is formed in the metal layer 1.
The metal layer 1 on the insulating layer 12 is formed by the steps of filling with 4 and 15 and etching having a sputtering effect.
4 and 15 are removed.

A method of manufacturing a semiconductor device according to a second aspect is the method of manufacturing a semiconductor device according to the first aspect, wherein the metal layer 1 is used.
It is characterized in that 4 and 15 are single-layer films only of a tungsten layer or laminated films including a tungsten layer.

The method of manufacturing a semiconductor device according to claim 3 is the first
And the second metal layers 14 and 15 are sequentially deposited on the entire surface to form the connection hole 13 provided in the insulating layer 12 with the first hole.
And a step of filling with the second metal layers 14 and 15, and the first
Removing the second metal layer 15 until the metal layer 14 is exposed, and forming a compound layer of the first metal layer 14 on the exposed surface of the first metal layer 14.
And a step of removing the compound layer by etching having a sputtering effect.

A method of manufacturing a semiconductor device according to a fourth aspect is the method of manufacturing a semiconductor device according to the third aspect, characterized in that the second metal layer 15 is a tungsten layer.

[0019]

In the method of manufacturing a semiconductor device according to the first aspect of the present invention, the insulating layer 12 at the opening of the connection hole 13 is formed at the same time as the etching for forming the metal plugs 14 and 15 filling the connection hole 13 due to the angular dependence of the sputtering rate. Is acceleratedly etched, and the opening of the connection hole 13 filled with the metal plugs 14 and 15 is tapered.

In the method of manufacturing a semiconductor device according to a third aspect of the present invention, at the same time as the etching for forming the metal plugs 14 and 15 filling the connection hole 13, the first metal in the upper portion of the connection hole 13 is formed due to the angular dependence of the sputtering rate. Layer 14
Is accelerated and the metal layer 14 in the upper portion of the connection hole 13 filled with the metal plugs 14 and 15 is tapered.

Moreover, the first metal layer 14 is used for etching.
Since the compound layer of 1 is removed, the surface of the first metal layer 14 on the insulating layer 12 can be maintained in a good state.

[0022]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS First Embodiment of the Invention of the Present Application Applied to Manufacturing of a Semiconductor Device Having a Connection Hole for Connecting a Semiconductor Substrate and Wiring
A second embodiment will be described with reference to FIGS.
It should be noted that, in the embodiment, components corresponding to the conventional example shown in FIGS. 3 and 4 are designated by the same reference numerals.

FIG. 1 shows a first embodiment. Also in this first embodiment, as shown in FIG. 1A, substantially the same steps as those of the conventional example shown in FIGS. 3 and 4 are executed until the W layer 15 is deposited. However, in the first embodiment, thereafter, as shown in FIG.
Anisotropic etching by reactive ion etching is performed on the entire surface of.

At this time, in the reactive ion etching, SF ₆ and Ar are used as etching gases at 110% respectively.
Supply at sccm, 90sccm, high frequency power 275
W and pressure are 46.55 kPa. At this time, S
From the back surface side of the i substrate 11, 5 sc of He is used as a cooling gas.
Supply in cm.

Next, as shown in FIG. 1 (c), Ti / Ti
Anisotropic etching by reactive ion etching is performed on the entire surface of the W layer 15 until the N layer 14 is exposed. At the time of reactive ion etching at this time, SF ₆ and Ar are used as etching gases at 40 sccm and 20 s, respectively.
Supply at ccm, high frequency power 100W, pressure 30kP
a. At this time, He is supplied as a cooling gas at 10 sccm from the back surface side of the Si substrate 11.

The reactive ion etching of FIG. 1 (b) has a relatively high etching rate and high throughput, and the reactive ion etching of FIG. 1 (c) has a relatively low etching rate and good controllability. By combining these, etching with good controllability can be performed with high throughput. Since the reactive ion etching of FIG. 1C is just etching up to the interface with the Ti / TiN layer 14, as shown in FIG. 1C, the W layer 15 is formed on the Ti / TiN layer 14. Residue remains.

Next, Cl ₂ and Ar are used as etching gases.
Is supplied at 5 sccm and 75 sccm, respectively, and anisotropic etching with a high frequency power of 250 W and a pressure of 7 kPa is performed.
This is performed on the entire surface of the W layer 15 and the Ti / TiN layer 14. In this case, even after the SiO ₂ layer 12 is exposed the SiO ₂ layer 12
Is over-etched by etching over a thickness of about 30 nm. Since Cl ₂ has selectivity with respect to the Ti / TiN layer 14, this Ti / TiN layer 14 is uniformly removed as shown in FIG. 1 (d).

However, for the SiO ₂ layer 12, Cl ₂
Has no selectivity, so sputtering by Ar becomes dominant. Then, the SiO ₂ layer 12 in the opening portion of the connection hole 13 is acceleratedly etched due to the angular dependence of the sputtering rate, and as shown in FIG.
The opening of the connection hole 13 is tapered. After that, conventionally known processes are executed to complete this semiconductor device.

FIG. 2 shows a second embodiment. Also in this second embodiment, as shown in FIGS. 2A to 2C, Ti /
Until the TiN layer 14 is exposed and until anisotropic etching by reactive ion etching is performed on the entire surface of the W layer 15, substantially the same steps as those in the first embodiment shown in FIG. 1 are performed.

The same applies to the first embodiment shown in FIG. 1, but the reactive ion etching for the W layer 15 is dominated by the reaction by the fluorine radicals, so that Ti / TiN is used.
When the etching of the W layer 15 up to the interface with the layer 14 is completed, a TiF layer (not shown) is attached to the surface of the TiN layer on the upper side of the Ti / TiN layer 14. The phenomenon in which the TiF layer adheres in this way is not limited to the TiN layer,
It also occurs in other metal layers containing i.

In the second embodiment, thereafter, O ₂ and Ar are used as etching gases at 5 sccm and 75 sccm, respectively.
Then, anisotropic etching with a high frequency power of 250 W and a pressure of 7 kPa is performed on the entire surfaces of the W layer 15 and the TiF layer. At this time, over-etching for etching the Ti / TiN layer 14 is performed even after the Ti / TiN layer 14 is exposed. Since O ₂ has a selectivity with respect to the TiF layer, this TiF layer is uniformly removed.

However, for the Ti / TiN layer 14, O
_{Since 2} has no selectivity, sputtering by Ar becomes dominant. Then, due to the angle dependence of the sputtering rate, Ti / Ti in the upper portion of the connection hole 13
The N layer 14 is acceleratedly etched, and the Ti / TiN layer 14 in the upper portion of the connection hole 13 is tapered as shown in FIG. After that, execute the conventionally known process,
This semiconductor device is completed.

In any of the above first and second embodiments, the metal plug filling the connection hole 13 is made of Ti / Ti.
Although the three-layer film of the N layer 14 and the W layer 15 is used, the metal plug may be formed of a two-layer film of the TiN layer and the W layer. Instead of the TiN layer in these two-layer film or three-layer film, ,
A TiSi layer, a TiW layer, a TiON layer, a Ti layer formed by sputtering, or the like may be used. Further, the metal plug may be composed of a single layer film having only the W layer.

In each of the above-mentioned first and second embodiments, the invention of the present application is applied to the manufacture of the semiconductor device having the connection hole for connecting the semiconductor substrate and the wiring. The invention of the present application can naturally be applied to the manufacture of a semiconductor device having a connection hole for connecting wirings.

[0035]

In the method of manufacturing a semiconductor device according to the first and third aspects of the present invention, the opening of the connection hole filled with the metal plug or the metal layer at the upper portion of the connection hole filled with the metal plug is tapered. As a result, it is possible to manufacture a highly reliable semiconductor device in which the step coverage of the wiring above the connection hole is excellent.

Moreover, since the above-described taper is performed at the same time as the etching for forming the metal plug filling the connection hole, a separate step for tapering is not necessary, and the wiring of the layer above the connection hole is not required. A highly reliable semiconductor device having excellent step coverage can be efficiently and simply manufactured.

In the method of manufacturing a semiconductor device according to the third aspect, since the surface of the metal layer on the insulating layer can be maintained in a good state, the wiring above the connection hole can be a good laminated wiring. Thus, a semiconductor device having higher reliability can be simply manufactured.

[Brief description of drawings]

FIG. 1 is a side sectional view showing a first embodiment of the present invention in the order of steps.

FIG. 2 is a side sectional view showing a second embodiment of the invention of the present application in the order of steps.

FIG. 3 is a side sectional view showing the first half of a conventional example of the invention of the present application in the order of steps.

FIG. 4 is a side sectional view showing the latter half of a conventional example in the order of steps.

[Explanation of symbols]

12 SiO ₂ layer 13 Connection hole 14 Ti / TiN layer 15 W layer

Claims (4)

[Claims] 1. A step of depositing a metal layer on the entire surface and filling a connection hole provided in an insulating layer with the metal layer, and removing the metal layer on the insulating layer by etching having a sputtering effect. A method of manufacturing a semiconductor device, comprising: 2. The method for manufacturing a semiconductor device according to claim 1, wherein the metal layer is a single layer film including only a tungsten layer or a laminated film including a tungsten layer. 3. A step of sequentially depositing first and second metal layers on the entire surface to fill the connection holes provided in the insulating layer with the first and second metal layers, Removing the second metal layer until the metal layer is exposed, and forming a compound layer of the first metal layer on the exposed surface of the first metal layer; and etching by a sputtering effect. And a step of removing the compound layer, the method for manufacturing a semiconductor device. 4. The method of manufacturing a semiconductor device according to claim 3, wherein the second metal layer is a tungsten layer.