KR100399602B1 - Method for manufacturing metal line of semiconductor device - Google Patents
Method for manufacturing metal line of semiconductor device Download PDFInfo
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- KR100399602B1 KR100399602B1 KR10-2001-0001840A KR20010001840A KR100399602B1 KR 100399602 B1 KR100399602 B1 KR 100399602B1 KR 20010001840 A KR20010001840 A KR 20010001840A KR 100399602 B1 KR100399602 B1 KR 100399602B1
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- metal wiring
- layer
- interlayer insulating
- insulating layer
- metal
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/7684—Smoothing; Planarisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
Abstract
본 발명은 반도체 디바이스용 금속 배선에 관한 것으로써, 반도체 기판의 층간 절연층 상부에 다층으로 된 금속 배선을 제조하는 방법에 있어서, 먼저 기판 상부에 층간 절연층을 형성하고 금속 배선이 형성될 부위를 트렌치로 식각하고, 식각된 층간 절연층의 상부에 접합층 및 금속층을 순차적으로 증착하고, 증착된 접합층과 금속층을 소정의 두께로 평탄화 하여 금속 배선을 형성함으로써, 금속 배선의 제조 공정을 간편화시킴과 아울러 안정된 금속 배선을 형성할 수 있는 효과가 있다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a metal wiring for a semiconductor device, the method of manufacturing a multilayered metal wiring on an interlayer insulating layer of a semiconductor substrate, the method comprising first forming an interlayer insulating layer on an upper portion of the substrate and forming a portion where the metal wiring is to be formed Etching with a trench, sequentially depositing a bonding layer and a metal layer on the etched interlayer insulating layer, and simplifying the manufacturing process of the metal wiring by forming a metal wiring by planarizing the deposited bonding layer and the metal layer to a predetermined thickness. In addition, there is an effect that can form a stable metal wiring.
또한, 안정된 금속 배선을 형성함으로써, 반도체 디바이스용 집적도에 따른 금속 배선의 임계 치수(CD : Critical Dimension)의 감소에 의한 영향을 받지 않는 효과가 있다.In addition, by forming a stable metal wiring, there is an effect that is not affected by the reduction of the critical dimension (CD) of the metal wiring according to the degree of integration for semiconductor devices.
Description
본 발명은 반도체 제조 방법에 관한 것으로서, 더욱 상세하게는 안정된 반도체 디바이스용 금속 배선을 제조하는 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor, and more particularly, to a method for producing a metal wiring for a stable semiconductor device.
최근 들어, 반도체 다바이스가 대용량화 및 고집적화 됨에 따라 반도체 디바이스의 면적은 점진적으로 축소되고 있으며, 그에 따라 반도체 디바이스 및 금속 배선의 임계 치수가 감소된다.In recent years, as semiconductor devices become larger and more integrated, the area of a semiconductor device is gradually reduced, thereby reducing the critical dimensions of the semiconductor device and the metal wiring.
도 1a 내지 도 1f는 종래 기술에 따른 반도체 디바이스용 금속 배선 제조 공정을 도시한 단면도들로써, 이를 참조하면, 종래의 금속 배선은 실리콘 기판(10)의 층간 절연층(20)의 상부에 확산 장벽층(30), 금속층(40) 및 반사 방지층(50)이 순차적으로 적층되는 구조를 갖는다.1A to 1F are cross-sectional views illustrating a metal wiring manufacturing process for a semiconductor device according to the prior art. Referring to this, the conventional metal wiring is a diffusion barrier layer on an interlayer insulating layer 20 of a silicon substrate 10. 30, the metal layer 40, and the antireflection layer 50 are sequentially stacked.
도 1a를 참조하면, 반도체 기판으로서 실리콘 기판(10)에 소정의 소자 공정을 실시하고, 실리콘 기판(10) 전면에 층간 절연층(20)을 증착한다. 증착된 층간 절연층(20)은 실리콘 기판(10)과 금속 배선 사이의 절연하는 역할을 한다. 실리콘 기판(10)의 상부에 증착된 층간 절연층(20)은 하부층의 굴곡(topology)에 의해서 단차가 많이 생긴다.Referring to FIG. 1A, a predetermined device process is performed on a silicon substrate 10 as a semiconductor substrate, and an interlayer insulating layer 20 is deposited on the entire surface of the silicon substrate 10. The deposited interlayer insulating layer 20 serves to insulate between the silicon substrate 10 and the metal wires. The interlayer insulating layer 20 deposited on the silicon substrate 10 has many steps due to the topology of the lower layer.
도 1b에 도시된 바와 같이, 이러한 단차를 없애기 위하여 CMP(Chemical Mechanical Polishing) 기술을 이용하여 금속 배선이 형성될 층간 절연층(20)의 표면을 평탄하게 해준다.As shown in FIG. 1B, in order to eliminate such a step, the surface of the interlayer insulating layer 20 on which the metal wiring is to be formed is formed by using a chemical mechanical polishing (CMP) technique.
도 1c를 참조하면, 평탄화된 층간 절연층(20) 상부에 확산 장벽층(30)을 증착한다.Referring to FIG. 1C, a diffusion barrier layer 30 is deposited on the planarized interlayer insulating layer 20.
그리고, 확산 장벽층(30) 상부에 금속층(40)을 증착한 후 반사 방지층(50)을 증착하는데, 반사 방지층(50)은 금속 배선의 패턴 형성을 하기 위한 포토 마스킹공정 시에 플라스마 난반사를 막는 역할을 한다.The metal layer 40 is deposited on the diffusion barrier layer 30 and then the anti-reflection layer 50 is deposited. The anti-reflection layer 50 prevents plasma diffuse reflection during a photomasking process for forming a pattern of metal wiring. Play a role.
그 다음, 도 1d에 도시된 바와 같이, 금속 배선이 형성될 부분의 패턴을 형성하기 위하여, 포토레지스트를 반사 방지층(50)의 표면에 도포하고, 일정한 시간 동안의 노광 및 현상 공정을 통하여 금속 배선이 형성될 부분의 반사 방지층(50) 상부에 포토레지스트 패턴(60)을 형성한다.Then, as shown in Fig. 1D, in order to form a pattern of the portion where the metal wiring is to be formed, the photoresist is applied to the surface of the antireflection layer 50, and the metal wiring is subjected to exposure and development processes for a predetermined time. The photoresist pattern 60 is formed on the anti-reflection layer 50 of the portion to be formed.
포토 마스킹 공정에 의해서 생성된 포토레지스트 패턴(60)을 이용하여, 도 1e에 도시된 바와 같이, 플라즈마 식각 공정으로 금속층(40)을 식각해서 금속 배선(70)을 형성한다.Using the photoresist pattern 60 generated by the photo masking process, as shown in FIG. 1E, the metal layer 40 is etched by the plasma etching process to form the metal wiring 70.
플라스마 식각 이후에, 반사 방지층(50)에 도포 되었던 포토레지스트 패턴(60)을 제거한 후, 솔벤트와 같은 화합물을 이용하여 클린징 공정으로 오염 물질을 제거하여 금속 배선(70) 제조 공정을 완료한다.After the plasma etching, the photoresist pattern 60 applied to the anti-reflection layer 50 is removed, and then a contaminant is removed by a cleaning process using a compound such as a solvent to complete the manufacturing process of the metal wiring 70.
전술한 바와 같은 종래의 금속 배선 제조 공정은 층간 절연층 증착, CMP 공정, 확산 장벽층 증착, 금속층 증착, 패턴 형성 및 금속 배선 형성 등과 같은 복잡한 과정을 거쳐야하고, 반도체 디바이스의 집적도가 높아질수록 금속 배선의 임계 치수(CD : Critical Dimension)가 작아져 금속 배선 제조 공정 시에 불량이 발생하는 문제점이 있다.The conventional metal wiring manufacturing process as described above has to go through complicated processes such as interlayer insulation layer deposition, CMP process, diffusion barrier layer deposition, metal layer deposition, pattern formation, and metal wiring formation, and the higher the degree of integration of semiconductor devices, the more metal wiring. The critical dimension (CD) is reduced, there is a problem that a defect occurs during the metal wiring manufacturing process.
만약 종래 기술에서 CMP 공정을 생략할 경우에, 금속 배선을 위한 포토 마스킹 공정시 층간 절연층의 굴곡에 의해서 양호한 금속 배선의 패턴을 얻는데 어려움이 있다.If the CMP process is omitted in the prior art, it is difficult to obtain a good pattern of the metal wiring by bending the interlayer insulating layer during the photomasking process for the metal wiring.
본 발명의 목적은 상기와 같은 종래 기술의 문제점을 해결하기 위한 것으로서, 금속 배선 형성 공정을 단순화시킴과 아울러 안정된 금속 배선을 형성할 수 있는 반도체 디바이스용 금속 배선 제조 방법을 제공하고자 한다.SUMMARY OF THE INVENTION An object of the present invention is to solve the problems of the prior art as described above, and to provide a method for manufacturing a metal wiring for a semiconductor device capable of simplifying a metal wiring forming process and forming a stable metal wiring.
상기와 같은 본 발명의 목적을 달성하기 위한 본 발명은, 반도체 기판의 층간 절연층 상부에 금속 배선을 제조하는 방법에 있어서, 상기 기판 상부에 상기 층간 절연층을 형성하는 단계와, 반응 이온 식각 장치를 통해 상기 층간 절연층 표면에서부터 소정 깊이로 식각하여 금속 배선이 형성될 부위인 트렌치를 형성하는 단계와, 상기 트렌치가 형성된 층간 절연층 상부에 접합층을 증착하는 단계와, 상기 접합층 상부에 트렌치가 매립되도록 금속층을 증착하는 단계 및 상기 접합층 및 금속층을 평탄화 하여 트렌치내에 금속 배선을 형성하는 단계로 이루어진 것을 특징으로 하는 반도체 디바이스용 금속 배선 제조 방법을 제공한다.The present invention for achieving the above object of the present invention, in the method of manufacturing a metal wiring on the interlayer insulating layer of the semiconductor substrate, the step of forming the interlayer insulating layer on the substrate, the reaction ion etching apparatus Forming a trench, which is a portion where the metal wiring is to be formed, by etching to a predetermined depth from the surface of the interlayer insulating layer, depositing a bonding layer on the interlayer insulating layer on which the trench is formed, and forming a trench on the bonding layer. And depositing a metal layer such that the metal layer is buried, and forming a metal wiring in the trench by planarizing the junction layer and the metal layer.
도 1a 내지 도 1f는 종래에 따른 반도체 디바이스용 금속 배선의 제조 공정을 나타내는 단면도,1A to 1F are cross-sectional views illustrating a conventional step for manufacturing a metal wiring for a semiconductor device;
도 2는 본 발명에 따른 반도체 디바이스용 금속 배선을 나타내는 측면도,2 is a side view showing a metal wiring for a semiconductor device according to the present invention;
도 3a 내지 도 3d는 본 발명에 따른 반도체 디바이스용 금속 배선의 제조 공정 과정을 나타내는 구성도이다.3A to 3D are block diagrams illustrating a process for manufacturing a metal wiring for a semiconductor device according to the present invention.
＜도면의 주요부분에 대한 부호의 설명＞<Description of the code | symbol about the principal part of drawing>
5, 101 : 소자 10, 100 : 실리콘 기판5, 101: device 10, 100: silicon substrate
20, 102 : 층간 절연층 30 : 확산 방지층20, 102: interlayer insulation layer 30: diffusion barrier layer
40, 106 : 금속층 50 : 반사 방지층40, 106: metal layer 50: antireflection layer
105 : 트렌치 60, 250 : 포토레지스트 패턴105: trench 60, 250: photoresist pattern
200, 70 : 금속 배선 104 : 접합층200, 70: metal wiring 104: bonding layer
이하 첨부된 도면을 참조하여 본 발명의 바람직한 실시예에 대해 설명하고자 한다.Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.
먼저, 본 발명의 기술요지는 반도체 기판(예를 들면, 실리콘 기판)의 층간 절연층 상부에 다층으로 된 금속 배선을 제조하는 방법을 기판 상부에 상기 층간 절연층을 형성하고 금속 배선이 형성될 부위를 트렌치로 식각하고, 식각된 층간 절연층의 상부에 접합층 및 금속층을 순차적으로 증착하여, 층간 절연층에 증착된 접합층과 금속층으로 이루어진 다층을 일정한 두께로 평탄화 함으로써, 종래의 금속 배선을 형성하는 제조 방법을 단순화함과 아울러 안정된 금속 배선을 형성할 수 있는데 있다.First, the technical aspect of the present invention is a method of manufacturing a multi-layered metal wiring on an interlayer insulating layer of a semiconductor substrate (for example, a silicon substrate), the site where the interlayer insulating layer is formed on the substrate and the metal wiring is to be formed. Is etched in a trench, and a junction layer and a metal layer are sequentially deposited on the etched interlayer insulating layer, thereby forming a conventional metal wiring by planarizing a multilayer of the junction layer and the metal layer deposited on the interlayer insulating layer to a predetermined thickness. In addition to simplifying the manufacturing method, it is possible to form a stable metal wiring.
도 2는 본 발명에 따른 반도체 디바이스용 금속 배선을 나타내는 측면도이다.2 is a side view showing a metal wiring for a semiconductor device according to the present invention.
도 2에 도시된 바와 같이, 본 발명의 반도체 디바이스용 금속 배선(200)의 일 예는 층간 절연층(102)의 트렌치에 매립된 접합층(104) 및 금속층(106)으로 이루어지고, 접합층(104)의 일 예는 질화 티타늄(TiN) 또는 티타늄(Ti)이 단층 및 복층으로 되고, 금속층(106)은 알루미늄-구리 합금(Al-Cu Alloy) 또는 구리(Cu) 등으로 되어 있다. 또한 금속 배선(200)은 층간 절연층(102)을 트렌치로 식각한 후 트렌치에 매립된 금속층(106)과 접합층(104)을 포함한다.As shown in FIG. 2, an example of the metal wiring 200 for a semiconductor device of the present invention includes a bonding layer 104 and a metal layer 106 embedded in a trench of an interlayer insulating layer 102, and a bonding layer. In one example of 104, titanium nitride (TiN) or titanium (Ti) is formed into a single layer and a multilayer, and the metal layer 106 is made of aluminum-copper alloy (Al-Cu Alloy), copper (Cu), or the like. In addition, the metal wire 200 includes a metal layer 106 and a bonding layer 104 embedded in the trench after etching the interlayer insulating layer 102 with a trench.
이때, 열처리 공정시에 7000() 두께의 알루미늄-구리 합금 또는 구리로 된 금속층(106)과 산화막인 층간 절연층(100)의 접촉을 원활히 하기 위하여 티타늄(Ti) 및 질화 티타늄(TiN) 물질로 이루어진 접합층(104)을 금속층(106)의 하부측에 두께 2000()으로 식각한다.At this time, 7000 ( In order to facilitate contact between the metal layer 106 of aluminum-copper alloy or copper having a thick thickness and the interlayer insulating layer 100 which is an oxide film, a bonding layer 104 made of titanium (Ti) and titanium nitride (TiN) materials is used. On the lower side of 106, thickness 2000 ( Etch with).
이러한 구조를 갖는 본 발명의 반도체 디바이스용 금속 배선 제조 공정은 도 3a 내지 도 3d를 참조한다.The metal wiring manufacturing process for a semiconductor device of the present invention having such a structure is referred to FIGS. 3A to 3D.
도 3a에 도시된 바와 같이, 반도체 기판으로서 실리콘 기판(100)에 소정의 소자(예컨데, 트랜지스터(103)) 공정을 실시하고, 실리콘 기판(100)의 전면에 층간 절연층(102)으로서 두께 10000()으로 증착한다.As shown in FIG. 3A, a predetermined element (for example, transistor 103) process is performed on a silicon substrate 100 as a semiconductor substrate, and a thickness 10000 is provided as an interlayer insulating layer 102 on the entire surface of the silicon substrate 100. ( To be deposited).
포토 마스킹 공정으로, 포토레지스트를 층간 절연층(102)의 표면에 도포하고, 일정한 시간 동안의 노광 및 현상 공정을 통하여 금속 배선이 형성될 부분의층간 절연층(102) 상부에 포토레지스트 패턴(250)을 형성한다.In the photo masking process, a photoresist is applied to the surface of the interlayer insulating layer 102, and the photoresist pattern 250 is formed on the interlayer insulating layer 102 of the portion where the metal wiring is to be formed through the exposure and development processes for a predetermined time. ).
도 3b에 도시된 바와 같이, 포토 마스킹 공정에 의해서 형성된 포토레지스트 패턴(250) 부분을 제외한 층간 절연층(102)을 식각하여 트렌치(105)를 형성될 부분이다.As shown in FIG. 3B, the trench 105 may be formed by etching the interlayer insulating layer 102 except for the photoresist pattern 250 formed by the photo masking process.
트렌치(105) 식각 공정은 산화물 반응 이온 식각 장치(RIE : Reactive Ion Etcher)를 이용하여 층간 절연층(102) 표면에서부터 약 7000() 깊이로 식각된다.The trench 105 etching process uses an oxide reactive ion etchant (RIE) to remove the trench 105 from the surface of the interlayer dielectric layer 102. ) Is etched to depth.
여기서, 반응 이온 식각 장치는, 건식 식각의 한 종류로써, 플라스마 식각과 같은 원리를 이용하여 활성화된 이온을 화학적 및 물리적 반응에 의해 층간 절연층(102)을 식각 하는 것이다.Here, the reactive ion etching apparatus is a type of dry etching, in which the interlayer insulating layer 102 is etched by chemical and physical reactions of activated ions using the same principle as plasma etching.
상세한 식각 조건은, 반응 이온 식각 장치에 이온 가스 CF4 50 ∼200sccm(standard cubic centimeter per minute)와 CHF3 20 ∼ 100sccm(혹은, C4F8 이온 가스 10 ∼ 50sccm)를 주입하고, 반응 이온 식각 장치에 전력 1000 ∼ 2000watts의 에너지와 50 ∼ 100mT의 압력을 가함으로써 금속 배선(200)이 형성될 부분의 층간 절연층(102)이 트렌치로 식각된다.For detailed etching conditions, ion gas CF4 50 to 200 sccm (standard cubic centimeter per minute) and CHF3 20 to 100 sccm (or C4F8 ion gas 10 to 50 sccm) are injected into the reaction ion etching apparatus, and the power is applied to the reactive ion etching apparatus. By applying an energy of 2000 watts and a pressure of 50-100 mT, the interlayer insulating layer 102 of the portion where the metal wiring 200 is to be formed is etched into the trench.
트렌치 식각 공정이 끝난 후에, 에싱 공정을 실시하여 층간 절연층(102)에 도포 되었던 포토레지스트 패턴(250)을 제거한다.After the trench etching process is finished, an ashing process is performed to remove the photoresist pattern 250 applied to the interlayer insulating layer 102.
도 3c를 참조하면, 금속층(106)과 층간 절연층(102)의 접촉을 원활히 하기 위하여 티타늄 타켓을 이용하는 반응성 스퍼터링에 의한 물리 기상 증착법(PVD : Physical Vapor Deposition)을 통해 티타늄(Ti) 또는 질화 티타늄(TiN)으로 된 두게 2000() 정도의 접합층(104)을 형성한다. 그리고 접합층(104)의 상부에 알루미늄-구리 합금, 구리 등으로 된 두께 7000() 정도의 금속층(106)을 증착한다. 이때, 반응성 스퍼터링에 의한 접합층(104) 증착은 티타늄 타켓을 이용하여 챔버 내에서 아르곤 가스(Ar) 분위기 또는 아르곤(Ar)과 질소(N2) 가스 분위기에서 수행된다.Referring to FIG. 3C, titanium (Ti) or titanium nitride is formed through physical vapor deposition (PVD) by reactive sputtering using a titanium target to facilitate contact between the metal layer 106 and the interlayer insulating layer 102. Thick 2000 in (TiN) A bonding layer 104 of about) is formed. The thickness of the bonding layer 104 is made of aluminum-copper alloy, copper, and the like 7000 (thickness). A metal layer 106 is deposited. In this case, the deposition of the bonding layer 104 by reactive sputtering is performed in an argon gas (Ar) atmosphere or an argon (Ar) and nitrogen (N 2) gas atmosphere in the chamber using a titanium target.
접합층(104)과 금속층(106)의 증착이 완료되면, 도 3d에 도시된 바와 같이, 평탄화 과정을 실시한다.When deposition of the bonding layer 104 and the metal layer 106 is completed, as shown in Figure 3d, the planarization process is performed.
평탄화 과정은 화학적·기계적 연마(CMP : Chemical Mechanical Polishing) 공정에 의해서 수행되는데, 트렌치(105) 부위를 제외한 층간 절연체(102) 표면이 드러날 때까지 진행한다.The planarization process is performed by a chemical mechanical polishing (CMP) process until the surface of the interlayer insulator 102 is exposed except for the trench 105.
그러므로, CMP 공정에 의해 트렌치(105)에만 접합층(104) 및 금속층(106)이 되어, 본 발명의 금속 배선(200)이 얻어진다.Therefore, the junction layer 104 and the metal layer 106 are formed only in the trench 105 by the CMP process, and the metal wiring 200 of this invention is obtained.
이상 설명한 바와 같이, 본 발명은 반도체 기판의 층간 절연층 상부에 다층으로 된 금속 배선을 제조하는 방법에 있어서, 기판 상부에 층간 절연층을 형성하고 패터닝하여, 금속 배선이 형성될 부위를 트렌치로 식각하고, 층간 절연층 상부에 접합층 및 금속층을 순차적으로 증착하고, 증착된 접합층 및 금속층을 평탄화 하여 트렌치내에 금속 배선을 형성함으로써, 금속 배선의 제조 공정을 간편화시킴과 아울러 안정된 금속 배선을 형성할 수 있는 효과가 있다.As described above, the present invention is a method for manufacturing a multi-layered metal wiring on the interlayer insulating layer of the semiconductor substrate, by forming and patterning the interlayer insulating layer on the substrate, the portion where the metal wiring is to be formed by etching the trench By sequentially depositing a bonding layer and a metal layer on the interlayer insulating layer, and planarizing the deposited bonding layer and the metal layer to form metal wiring in the trench, a process for manufacturing metal wiring can be simplified and a stable metal wiring can be formed. It can be effective.
또한, 안정된 금속 배선을 형성함으로써, 반도체 디바이스용 집적도에 따른 금속 배선의 임계 치수의 감소에 의한 영향을 받지 않는 효과가 있다.In addition, by forming a stable metal wiring, there is an effect that is not affected by the reduction of the critical dimension of the metal wiring according to the degree of integration for semiconductor devices.
한편, 본 발명은 상술한 실시예에 국한되는 것이 아니라 후술되는 청구범위에 기재된 본 발명의 기술적 사상과 범주내에서 당업자에 의해 여러 가지 변형이 가능하다.On the other hand, the present invention is not limited to the above-described embodiment, various modifications are possible by those skilled in the art within the spirit and scope of the present invention described in the claims to be described later.
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0969522A (en) * | 1995-09-01 | 1997-03-11 | Fujitsu Ltd | Formation of buried conductive layer |
| US5824599A (en) * | 1996-01-16 | 1998-10-20 | Cornell Research Foundation, Inc. | Protected encapsulation of catalytic layer for electroless copper interconnect |
| KR19990081775A (en) * | 1998-04-09 | 1999-11-15 | 아끼구사 나오유끼 | Semiconductor device and manufacturing method thereof |
| KR20000002767A (en) * | 1998-06-23 | 2000-01-15 | 김영환 | Conductor plug forming method for wiring multi-layer of semiconductor device |
| KR20000026376A (en) * | 1998-10-20 | 2000-05-15 | 윤종용 | Damascene method for forming multilayer interconnections |
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Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0969522A (en) * | 1995-09-01 | 1997-03-11 | Fujitsu Ltd | Formation of buried conductive layer |
| US5824599A (en) * | 1996-01-16 | 1998-10-20 | Cornell Research Foundation, Inc. | Protected encapsulation of catalytic layer for electroless copper interconnect |
| KR19990081775A (en) * | 1998-04-09 | 1999-11-15 | 아끼구사 나오유끼 | Semiconductor device and manufacturing method thereof |
| KR20000002767A (en) * | 1998-06-23 | 2000-01-15 | 김영환 | Conductor plug forming method for wiring multi-layer of semiconductor device |
| KR20000026376A (en) * | 1998-10-20 | 2000-05-15 | 윤종용 | Damascene method for forming multilayer interconnections |
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