JPH0969522A - Formation of buried conductive layer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To increase the growth rate of Cu layer while improving step coverage at the time of forming a buried Cu layer in a recess. SOLUTION: A barrier metal layer 6 is formed in a recess 5 made in an insulation layer 4 and a thin seed layer 7 of Cu is formed thereon by coating the barrier metal layer 6 with independently diffused ultrafine particles of Cu. The surface of Cu is then reduced through oxygen reduction and the recess 5 is filled with a Cu layer 8 deposited by CVD. Finally, the unnecessary parts of barrier metal layer 6, thin seed layer 7 and Cu layer 8 are removed by mechano chemical polishing.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a buried conductive layer, and more particularly to a method for forming a buried wiring layer using Cu having high electromigration resistance.

[0002]

2. Description of the Related Art In recent years, high integration of semiconductor devices, or
With the increase in speed, it is required to reduce the resistance of the wiring layer in order to reduce the signal delay. As an alternative to the conventional Al wiring layer, the resistivity is lower than that of Al, and the electromigration resistance is about the same as that of Al. The use of twice as much Cu is being considered.

However, dry etching is generally required to form a fine wiring layer, but in the case of Cu, the vapor pressure of the halide of Cu is low, so that conventional RIE (reactive ion etching) is required. The method has a problem that a sufficient etching rate cannot be obtained at a low temperature, and that anisotropic etching is difficult.

In order to solve such a problem, a damascene using a self-alignment technique is used.
A method called the law is being studied. The damascene method is a method in which a Cu layer is deposited on a groove along a wiring pattern provided in an insulating layer and a contact hole, and then unnecessary portions on the upper portion are subjected to chemical mechanical polishing (Chemical Mechanical Polishing).
It is a method of forming a buried conductive layer by removing it by means of chemical polishing (CMP).

In this case, as a method of depositing Cu in the groove or the contact hole, a CVD (chemical vapor deposition) method which is excellent in step coverage (step coverage) or a step coverage is inferior. A combination of sputtering method and subsequent reflow is used, in particular,
Since the former CVD method is superior in step coverage to the latter sputtering method, it is expected as a method for forming a Cu wiring layer in a semiconductor device in the future, which is becoming more and more miniaturized.

When a Cu wiring layer is formed by the damascene method, Cu easily diffuses in SiO ₂ and forms a deep level in the silicon semiconductor to shorten the life of minority carriers. to prevent, SiO ₂ layer and the C
A barrier metal layer such as a TiN layer is interposed between the u layers, and a Cu layer is grown directly on the barrier metal layer such as the TiN layer.

[0007]

When the Cu layer is grown on the barrier metal layer such as the TiN layer by the CVD method, the growth rate is slow and the barrier metal layer may hardly grow. It has been confirmed that even when a barrier metal layer that grows is used, the Cu layer hardly grows in the recesses such as contact holes.

On the other hand, after a Cu thin film is formed on the barrier metal layer by the sputtering method, the CVD method is performed.
Although the growth rate is increased when the Cu layer is grown by the method, when the trench or the contact hole for forming the wiring is filled, the coverage is limited by the usual sputtering method, and the effect cannot be expected so much.

Therefore, the present invention increases the growth rate of the Cu layer when forming the embedded Cu layer in the recess,
Moreover, it is intended to improve the step coverage.

[0010]

FIG. 1 is an explanatory view of the principle configuration of the present invention, and means for solving the problems in the present invention will be described with reference to FIG. In addition, reference numerals 1, 2, and 3 in FIG. 1 represent a semiconductor substrate, a base insulating layer, and a wiring layer, respectively.

FIG. 1 (1) The present invention relates to a method of forming a buried conductive layer,
On the barrier metal layer 6 formed in the recess 5 provided in the insulating layer 4, Cu independent dispersion ultrafine particles are applied to form a seed layer 7 made of a Cu thin film, and then the surface of the Cu thin film is reduced by hydrogen reduction. Then, C is formed by chemical vapor deposition.
After the u layer 8 is deposited to fill the concave portion 5, unnecessary portions of the barrier metal layer 6, the seed layer 7 and the Cu layer 8 are removed by chemical mechanical polishing.

(2) According to the present invention, in the method for forming a buried conductive layer, independent dispersed ultrafine particles of Au are applied to the barrier metal layer 6 formed in the recess 5 provided in the insulating layer 4 to form an Au thin film. After the seed layer 7 is formed, a Cu layer 8 is deposited by chemical vapor deposition to fill the recess 5, and then the barrier metal layer 6, the seed layer 7, and
It is characterized in that unnecessary portions of the Cu layer 8 are removed by chemical mechanical polishing.

(3) In the method of forming a buried conductive layer according to the present invention, a Cu thin film or an Au thin film is formed on the barrier metal layer 6 formed in the recess 5 provided in the insulating layer 4 by the collimation sputtering method. Seed layer 7
After the formation, the Cu layer 8 is deposited by the chemical vapor deposition method to fill the recess 5, and then the barrier metal layer 6, the seed layer 7, and unnecessary portions of the Cu layer 8 are removed by chemical mechanical polishing. It is characterized by

(4) According to the present invention, in the method for forming a buried conductive layer, the distance between the target and the substrate to be processed is 10 cm or more on the barrier metal layer 6 formed in the recess 5 provided in the insulating layer 4. After the seed layer 7 made of a Cu thin film or an Au thin film is formed by the slow sputtering method, the Cu layer 8 is deposited by the chemical vapor deposition method to fill the concave portion 5, and then the barrier metal layer 6, the seed layer 7, and the , Cu layers 8 are removed by chemical mechanical polishing.

(5) Further, in the present invention, in any one of the above (1) to (4), the seed layer 7 has a thickness of 50 to 50.
The feature is that it is set to 200Å.

Such a seed layer 7 acts as a so-called Lewis base to become an electron donor, and a Cu-containing precursor (precursor) in the CVD method.
Electrons are emitted to form a bond orbit.

On the precursor side, the so-called Lewis acid (L
It acts as an electron acceptor and becomes an electron acceptor, and an anti-bonding orbital is generated to break the bond in the molecular structure of the precursor, resulting in the deposition of the Cu layer.

The more electrons are supplied from the seed layer 7, that is, the stronger the metallicity of the seed layer 7, the more the incubation time (delay time from the start of the deposition process to the actual deposition of the film). However, the growth rate of the Cu layer is high.

In the present invention, the seed layer 7 is made of Cu.
Cu thin film formed by coating the above independent dispersion ultrafine particles, Au
Au thin film formed by applying the independent dispersion ultrafine particles of Cu, or Cu thin film formed by the collimation sputtering method or long throw sputtering method or A
By using the u thin film, the step coverage is superior to that obtained by using a normal sputtering method, and the Cu layer 8 is formed in the recess 5 such as a groove or contact hole for forming a wiring layer with good reproducibility and large size. It can be formed at a growth rate.

[0020]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The manufacturing process of the first embodiment of the present invention will be described with reference to FIGS. In addition,
The internal volume of each reactor used in the practice of the present invention is 40-
It is 80 liters.

Referring to FIG. 2A, first, on a silicon substrate 11 having a 6-inch (about 15 cm) (100) plane as a main surface, SiO _{2 serving as} a base insulating layer is formed.
After depositing a 600 nm SiO ₂ layer 12 using the plasma CVD method through the layer 12 and the W wiring layer 13,
Apply 0.6 μm thick photoresist, then
A contact hole 15 having a width of 0.5 μm and a depth of 1 μm and an aspect ratio of 2 reaches the W wiring layer 13 by etching using a photoresist pattern formed by exposure and patterning using an i-line (365 nm) as a mask. To form.

In this case, the SiO ₂ layer 12 is made of TE
OS (Tetra-Ethyl-Ortho-Sili
Cate) -SiO ₂ layer, SOG (Spin-on G)
(lass) layer or PSG (Phospho-Si)
A lithic glass layer may be used, or the surface of the silicon substrate 11 may be thermally oxidized.

The wiring layer is not limited to the W wiring layer, and Al or TiN may be used. Furthermore, TiN / W / TiN or TiN / A may be used.
It is also possible to use a three-layer wiring layer made of 1 / TiN.

Next, referring to FIG. 2B, TiCl ₄ is added in an amount of 10 to 20 sccm, preferably 1
0 sccm, He 40 to 80 sccm, preferably 50
sccm, 0.4 to 0.8 scc of methylhydrazine
m, preferably 0.7 sccm, and NH ₃ of 400 to
800 sccm, preferably 500 sccm, the growth chamber pressure is 50 to 200 mTorr, preferably 100 mT
orr and the substrate temperature is 500 to 600 ° C., preferably 6
100 to 5 by depositing at 00 ° C for about 90 seconds
00Å, preferably 500Å C as a barrier metal layer
The VD-TiN layer 16 is deposited.

The CVD-TiN layer 16 may be replaced by a PVD-TiN layer formed by sputtering.
Although it is inferior to the CVD-TiN layer 16 in terms of step coverage,
The barrier properties are superior to the CVD-TiN layer 16.

Next, referring to FIG. 2 (c), Cu ultrafine particles independently dispersed in a kiresin solvent are applied using a spin coater to form contact holes 15.
After forming a uniform Cu ultrafine particle coating film having a thickness of 50 to 200Å, preferably 100Å, inside the
The Cu thin film 17 is formed by heat treatment at 10 ° C. for 10 to 15 minutes, preferably at 300 ° C. for 15 minutes.

The ultrafine particles in this case have a diameter of 5
0 to 200Å, preferably about 100Å fine particles,
The thickness of the Cu thin film 17 serving as the seed layer changes according to the diameter of the ultrafine particles.

See FIG. 3 (d). Then, in a hydrogen atmosphere in which H ₂ was flowed at 500 sccm to 1 Torr, at 350 to 400 ° C. for 3 to 4 minutes,
By heat treatment preferably at 400 ° C. for 3 minutes,
The surface of the oxidized Cu thin film 17 is reduced to form the Cu thin film 18. The Cu thin film 18 is CVD-C.
It functions as a seed layer for supplying electrons to the precursor when forming the u layer.

See FIG. 3E. Next, without exposing the silicon substrate 11 on which the Cu thin film 18 is formed to the atmosphere, the flow rate of H ₂ as a carrier gas is 100 to 1000 sccm, preferably 500 sccm, and hexafluoroacetylacetonate. Trimethylvinylsilane copper [hexafluoroacetylac
Etonate-trimethylvinylsila
neCu: Cu (hfac) TMVS] 0.1-1.
Supply 0 g / min, preferably 0.3 g / min, substrate temperature 1
20 to 220 ° C., preferably 160 ° C., growth chamber pressure 100 to 500 mTorr, preferably 200 mTorr
20 minutes by CVD-Cu layer 1
The contact hole 15 is filled by depositing 9.

See FIG. 3 (f). Then, using a chemical mechanical polishing method based on alumina powder as the slurry, the polishing pressure is 200 to 300 g / cm ² , preferably 250 g / cm ² , and the number of revolutions is 50 to 10
0 revolutions / minute (rpm), preferably 50 revolutions / minute,
Polishing for 2 minutes removes unnecessary portions of the CVD-Cu layer 19 to the TiN layer 16, that is, the CVD-Cu layer 19 to the TiN layer 16 deposited above the height of the contact hole 15 provided in the SiO ₂ layer 14. Embedded Cu contact electrode 2
Form 0.

According to the first embodiment, since the seed layer is formed by applying Cu ultrafine particles independently dispersed in the solvent, the Cu thin film 18 having a uniform thickness is formed inside the contact hole 15. Can be coated with CV
It is possible to grow the D-Cu layer 19 with good reproducibility.

Further, since it is not necessary to pattern the CVD-Cu layer 19, no problem occurs in microfabrication even when Cu which does not have an appropriate selective etching gas is used.

Next, the manufacturing process of the second embodiment of the present invention will be described with reference to FIGS. 4A and 4B. First, similarly to the first embodiment of the present invention, the thickness deposited on the silicon substrate 11 via the SiO ₂ layer 12 and the W wiring layer 13 which will be the base insulating layer. 600 nm SiO ₂ layer 1
4, a contact hole 15 having a width of 0.5 μm and a depth of 1 μm is formed so as to reach the W wiring layer 13, and then C
The TiN layer 16 as a barrier metal layer is 100 to 500 Å, preferably 50 by VD method or sputtering method.
Deposit 0Å.

Next, referring to FIG. 4C, Au ultrafine particles independently dispersed in a kiresin-based solvent are applied to the inside of the contact hole 15 to a thickness of 50 to 20.
After forming a uniform Au ultrafine particle coating film of 0 Å, preferably 100 Å, heat treatment is carried out at 250 to 300 ° C. for 10 to 15 minutes, preferably at 300 ° C. for 15 minutes to form the Au thin film 21.
To form In this case, the Au ultrafine particles also mean fine particles having a diameter of 50 to 200Å, preferably about 100Å, and the Au thin film 21 emits electrons to the precursor when forming the CVD-Cu layer. Functions as a seed layer to be supplied.

Next, as shown in FIG. 5D, the flow rate of H ₂ as a carrier gas is set to 100-1.
Cu as 000 sccm, preferably 500 sccm
(Hfac) TMVS is supplied at 0.1 to 1.0 g / min, preferably 0.3 g / min, and the substrate temperature is 120 to 220 ° C.
It is preferably 160 ° C. and the pressure in the growth chamber is 100 to 500.
The contact hole 15 is filled by depositing the CVD-Cu layer 19 for about 20 minutes by the CVD method with mTorr, preferably 200 mTorr.

5E, using a chemical mechanical polishing method based on alumina powder as a slurry, at a polishing pressure of 200 to 300 g / cm ² , preferably 250 g / cm ² , and a rotation speed of 50 to 10
0 revolutions / minute (rpm), preferably 50 revolutions / minute,
Polishing for 2 minutes removes unnecessary portions of the CVD-Cu layer 19 to the TiN layer 16, that is, the CVD-Cu layer 19 to the TiN layer 16 deposited above the height of the contact hole 15 provided in the SiO ₂ layer 14. Embedded Cu contact electrode 2
Form 0.

In this second embodiment, since Au ultrafine particles are used instead of Cu ultrafine particles, the first embodiment
Compared with the embodiment described above, the reduction step is not necessary, and thus there is an advantage that the manufacturing process is simplified. The other effects are substantially the same as those of the first embodiment.

Next, the manufacturing process of the third embodiment of the present invention will be described with reference to FIGS. 6 (a) and 6 (b) First, similarly to the first embodiment of the present invention, the thickness deposited on the silicon substrate 11 via the SiO ₂ layer 12 and the W wiring layer 13 which will be the underlying insulating layer. 600 nm SiO ₂ layer 1
4, a wiring layer groove 22 having a width of 0.3 μm and a depth of 0.5 μm is formed so as not to reach the W wiring layer 13, and then C
The TiN layer 16 as a barrier metal layer is 100 to 500 Å, preferably 50 by VD method or sputtering method.
Deposit 0Å.

Next, referring to FIG. 6C, Cu is formed by the collimation sputtering method.
The thin film 17 is deposited to a thickness of 100 to 300Å, preferably 100Å to form a seed layer. The collimation sputtering method is a method in which a collimator having a honeycomb-shaped passage is arranged between the target and the substrate to be processed.
Since the collimator is used to deposit only the sputter atomic components relatively parallel to each other, that is, the sputter atomic components relatively perpendicular to the substrate to be processed, it is inferior to the case of using ultrafine particles, but the normal sputtering method is used. The step coverage is improved as compared with the case where it is used, and the surface of the SiO ₂ layer 14 provided with the wiring layer groove 22 can be covered with a film having a relatively uniform film thickness.

See FIG. 7D. Then, without exposing the silicon substrate 11 on which the Cu thin film 17 is formed to the atmosphere, the flow rate of H ₂ as a carrier gas is set to 100 to 1000 sccm, preferably 500 sccm to Cu (hfac) TMVS. 0.1 to 1.0 g /
Minute, preferably 0.3 g / min, and the substrate temperature is 120 to
220 ° C., preferably 160 ° C., and the pressure in the growth chamber at 10
The wiring layer groove 22 is filled by depositing the CVD-Cu layer 19 for about 20 minutes by the CVD method at 0 to 500 mTorr, preferably 200 mTorr.

Then, referring to FIG. 7 (e), a chemical mechanical polishing method based on alumina powder as the slurry is used, and the polishing pressure is 200 to 300 g / cm ² , preferably 250 g / cm ² , and the number of revolutions is 50 to 10
0 revolutions / minute (rpm), preferably 50 revolutions / minute,
After polishing for 2 minutes, an unnecessary portion of the CVD-Cu layer 19 to the TiN layer 16, that is, the wiring layer groove 2 provided in the SiO ₂ layer 14 is formed.
CVD-Cu layer 19 to TiN deposited to a height of 2 or more
The layer 16 is removed and the Cu-embedded wiring layer 23 is formed.

In the third embodiment, the Cu thin film 17 to be the seed layer is formed by the sputtering method, and a wet process such as coating film formation is not used in the seed layer forming process. Is shortened.

Further, Cu in the third embodiment is also used.
Since the embedded wiring layer 23 has a smaller specific resistance than the Al wiring layer, the signal delay is small, and the disconnection time of the wiring layer due to electromigration is about twice as long as that of the Al wiring layer. Improves reliability.

Further, in the third embodiment,
It is also possible to use a long throw sputtering method instead of the collimation sputtering method, and this long throw sputtering method allows only relatively parallel sputtered atomic components by increasing the distance between the target and the substrate to be processed. Is used to deposit,
In the present specification, the case where the distance between the target and the substrate to be processed is 10 cm or more is defined as the long throw sputtering method. The step coverage is improved as compared with the case where it is used.

Although the seed layers are formed by different methods in the above embodiments of the invention,
When the Cu contact electrode 20 is formed in the contact hole 15, a collimation sputtering method or a long throw sputtering method may be used, and when the Cu embedded wiring layer 23 is formed in the wiring layer groove 22, It is also possible to form a coating film of ultrafine particles of Cu or Au.

Further, in the above-described embodiments of the invention, the aspect ratio of the cross section of the contact hole 15 or the wiring layer groove 22 is set to 2 or 5/3, but this ratio is arbitrary and is required. It may be appropriately determined based on the thickness of the interlayer insulating film or the design rule of the wiring layer.

Although Cu (hfac) TMVS is used as a precursor (precursor) for depositing the CVD-Cu layer 19 in the above-described embodiments of the invention, it is limited to Cu (hfac) TMVS. But other precursors such as hexafluoroacetylacetonate copper [hexafluoroacetyla
Cetonate-Cu: Cu (HFA) ₂ ] or the like may be used.

[0048]

According to the present invention, when a Cu layer is deposited by the CVD method, a seed layer composed of a Cu thin film or an Au thin film functioning as a Lewis base is formed on the barrier metal layer for preventing the diffusion of Cu. Since it is formed by using the independent dispersed ultrafine particles, or the collimation sputtering method or the long throw sputtering method, it is possible to form a seed layer having excellent step coverage and a short incubation time, and a Cu-embedded wiring with low resistance. The reliability of a semiconductor device provided with a layer or a Cu contact electrode can be improved and throughput can be improved.

[Brief description of drawings]

FIG. 1 is an explanatory diagram of a principle configuration of the present invention.

FIG. 2 is an explanatory diagram of a manufacturing process partway through the first embodiment of the present invention.

FIG. 3 is an explanatory view of a manufacturing process of the first embodiment of the present invention after FIG. 2;

FIG. 4 is an explanatory diagram of a manufacturing process partway through a second embodiment of the present invention.

FIG. 5 is an explanatory diagram of a manufacturing process after FIG. 4 according to the second embodiment of the present invention.

FIG. 6 is an explanatory diagram of a manufacturing process up to the middle of the third embodiment of the present invention.

FIG. 7 is an explanatory diagram of the manufacturing process after FIG. 6 according to the third embodiment of the present invention.

[Explanation of symbols]

1 Semiconductor Substrate 2 Base Insulating Layer 3 Wiring Layer 4 Insulating Layer 5 Recess 6 Barrier Metal Layer 7 Seed Layer 8 Cu Layer 11 Silicon Substrate 12 SiO ₂ Layer 13 W Wiring Layer 14 SiO ₂ Layer 15 Contact Hole 16 TiN Film 17 Cu Thin Film 18 Cu Thin film 19 CVD-Cu layer 20 Cu contact electrode 21 Au thin film 22 Wiring layer groove 23 Cu embedded wiring layer

Claims (5)

[Claims] 1. A Cu metal thin film seed layer is formed by coating Cu independent dispersion ultrafine particles on a barrier metal layer formed in a recess provided in an insulating layer, and then the Cu thin film surface is reduced by hydrogen reduction. Then, a Cu layer is deposited by a chemical vapor deposition method to fill the recesses, and then the barrier metal layer, the seed layer, and the C layer are formed.
A method for forming a buried conductive layer, which comprises removing unnecessary portions of the u layer by chemical mechanical polishing. 2. A Cu metal layer is deposited by chemical vapor deposition after forming a seed layer of Au thin film by coating Au independent dispersed ultrafine particles on a barrier metal layer formed in a recess provided in an insulating layer. To fill the recess, and then to form the barrier metal layer, the seed layer, and the C
A method for forming a buried conductive layer, which comprises removing unnecessary portions of the u layer by chemical mechanical polishing. 3. A seed layer made of a Cu thin film or an Au thin film is formed on the barrier metal layer formed in the recess provided in the insulating layer by a collimation sputtering method, and then a Cu layer is deposited by a chemical vapor deposition method. The recessed portion is filled with the barrier metal layer, and then unnecessary portions of the barrier metal layer, the seed layer, and the Cu layer are removed by chemical mechanical polishing, thereby forming a buried conductive layer. 4. The distance between the target and the substrate to be processed is 10c on the barrier metal layer formed in the recess provided in the insulating layer.
After forming a seed layer composed of a Cu thin film or an Au thin film by a long throw sputtering method of m or more, a Cu layer is deposited by a chemical vapor deposition method to fill the recess, and then the barrier metal layer, the seed layer, And a method for forming a buried conductive layer, characterized in that unnecessary portions of the Cu layer are removed by chemical mechanical polishing. 5. The seed layer has a thickness of 50 to 200Å
5. The method for forming a buried conductive layer according to claim 1, wherein: