KR100284139B1 - Tungsten plug formation method of semiconductor device - Google Patents

Tungsten plug formation method of semiconductor device Download PDF

Info

Publication number
KR100284139B1
KR100284139B1 KR1019980061450A KR19980061450A KR100284139B1 KR 100284139 B1 KR100284139 B1 KR 100284139B1 KR 1019980061450 A KR1019980061450 A KR 1019980061450A KR 19980061450 A KR19980061450 A KR 19980061450A KR 100284139 B1 KR100284139 B1 KR 100284139B1
Authority
KR
South Korea
Prior art keywords
forming
tungsten
titanium
film
titanium nitride
Prior art date
Application number
KR1019980061450A
Other languages
Korean (ko)
Other versions
KR20000044947A (en
Inventor
윤종원
고성한
Original Assignee
김영환
현대전자산업주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김영환, 현대전자산업주식회사 filed Critical 김영환
Priority to KR1019980061450A priority Critical patent/KR100284139B1/en
Publication of KR20000044947A publication Critical patent/KR20000044947A/en
Application granted granted Critical
Publication of KR100284139B1 publication Critical patent/KR100284139B1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/2855—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by physical means, e.g. sputtering, evaporation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/32115—Planarisation
    • H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/7684—Smoothing; Planarisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H01L21/76846—Layer combinations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
    • H01L21/76855—After-treatment introducing at least one additional element into the layer
    • H01L21/76856—After-treatment introducing at least one additional element into the layer by treatment in plasmas or gaseous environments, e.g. nitriding a refractory metal liner

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Plasma & Fusion (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

본 발명은 반도체 소자의 텅스텐 플러그 형성 방법에 관한 것으로, 하부 도전층이 형성된 기판 상부에 층간 절연막을 형성하고 하부 도전층 상부의 일부가 노출되는 콘택 홀을 형성하는 단계와, 상기 콘택 홀을 포함하는 전체 구조 상부에 배리어 메탈을 형성하는 단계와, 전체 구조 상부에 텅스텐을 증착하는 단계와, 화학적 기계적 연마 공정에 의해 상기 텅스텐 및 배리어 메탈을 제거하는 단계로 이루어지는 반도체 소자의 텅스텐 플러그 형성 방법이 개시된다.The present invention relates to a method for forming a tungsten plug of a semiconductor device, the method comprising: forming an interlayer insulating film on a substrate on which a lower conductive layer is formed, and forming a contact hole through which a portion of the lower conductive layer is exposed; A method of forming a tungsten plug in a semiconductor device, the method comprising forming a barrier metal over an entire structure, depositing tungsten over the entire structure, and removing the tungsten and the barrier metal by a chemical mechanical polishing process. .

Description

반도체 소자의 텅스텐 플러그 형성 방법Tungsten plug formation method of semiconductor device

본 발명은 반도체 소자의 텅스텐 플러그 형성 방법에 관한 것으로, 텅스텐 플러그 형성 후 웨이퍼의 표면 거칠기를 개선하여 후속 공정을 안정화할 수 있는 반도체 소자의 텅스텐 플러그 형성 방법에 관한 것이다.The present invention relates to a method for forming a tungsten plug of a semiconductor device, and to a method for forming a tungsten plug of a semiconductor device capable of stabilizing a subsequent process by improving the surface roughness of a wafer after forming the tungsten plug.

반도체 소자의 고집적화에 따라 콘택 홀은 0.30㎛ 정도의 크기를 갖으며, 이에 따라 금속 배선의 형성은 텅스텐 등을 이용한 플러그 공정과 알루미늄 등의 주 배선재료를 이용한 배선 공정으로 나뉘어진다.According to the high integration of semiconductor devices, the contact hole has a size of about 0.30 μm, and accordingly, the metal wiring is divided into a plug process using tungsten or the like and a wiring process using a main wiring material such as aluminum.

도 1(a) 내지 1(c)는 종래 반도체 소자의 텅스텐 플러그 형성 방법을 설명하기 위해 도시한 소자의 단면도이다.1 (a) to 1 (c) are cross-sectional views of a device for explaining a method of forming a tungsten plug of a conventional semiconductor device.

도 1(a)에 도시된 바와 같이, 도전층(12) 등의 하부구조가 형성된 반도체 기판(11) 상부에 층간 절연막(13)을 형성하고, 메탈 콘택 마스크를 이용한 식각 공정으로 콘택 홀을 형성한다. 이후, 콘택 홀을 포함하는 전체 구조 상부에 티타늄(Ti)막(14) 및 티타늄 나이트라이드(TiN)막(15)을 순차적으로 형성하므로써 배리어 금속층을 형성한다. 다음에, 콘택 홀이 매립되도록 전체 구조 상부에 텅스텐(W)층을 형성하고 블랭킷 식각 공정으로 층간 절연막(13) 상의 텅스텐층 및 티타늄 나이트라이드층를 제거하여, 텅스텐 플러그(16)를 형성한다.As shown in FIG. 1A, an interlayer insulating layer 13 is formed on a semiconductor substrate 11 on which a lower structure such as the conductive layer 12 is formed, and a contact hole is formed by an etching process using a metal contact mask. do. Thereafter, the barrier metal layer is formed by sequentially forming the titanium (Ti) film 14 and the titanium nitride (TiN) film 15 on the entire structure including the contact hole. Next, a tungsten (W) layer is formed over the entire structure to fill the contact hole, and the tungsten layer and the titanium nitride layer on the interlayer insulating layer 13 are removed by a blanket etching process to form a tungsten plug 16.

이와 같은 블랭킷 식각 공정 후에는 식각 공정시 발생하는 폴리머(polymer) 등의 부산물을 제거하기 위하여 세정 공정을 실시한다. 이 세정 공정에 사용되는 화학물질에는 폴리머 제거 능력이 우수한 것으로 알려진 수산화아민(hydroxylamin) 계열(예를 들어, ACT)이 보편적으로 이용되고 있다. 이러한 화학물질은 세정 공정시 티타늄막(14)을 식각 또는 어택(attack)하여 표면이 거칠어지게 되고, 이러한 표면 거칠기는 후속 금속배선 형성 공정에서 볼록한 형태의 결함(defect)을 발생시켜 패일을 유발하게 한다. 도 1(b) 및 1(c)는 각각 텅스텐층을 식각하기 전과 후의 웨이퍼 표면을 나타낸다.After the blanket etching process, a cleaning process is performed to remove by-products such as polymer generated during the etching process. Chemicals used in this cleaning process are commonly used hydroxylamin series (eg, ACT), which are known for their excellent polymer removal capability. These chemicals etch or attack the titanium film 14 during the cleaning process, resulting in a rough surface. Such surface roughness causes convex defects in the subsequent metallization process, causing defects. do. 1 (b) and 1 (c) show the wafer surface before and after etching the tungsten layer, respectively.

따라서, 본 발명은 텅스텐 플러그 형성후 실시하는 세정 공정시의 화학 용액에 의해 웨이퍼 표면이 거칠어지는 것을 방지하여, 후속 금속 배선 형성 공정을 안정하게 진행할 수 있는 반도체 소자의 텅스텐 플러그 형성 방법을 제공하는데 그 목적이 있다.Accordingly, the present invention provides a method for forming a tungsten plug of a semiconductor device which can prevent the surface of the wafer from being roughened by the chemical solution during the cleaning process performed after the formation of the tungsten plug, and can proceed the subsequent metal wiring forming process stably. There is a purpose.

상술한 목적을 달성하기 위한 본 발명의 제 1 실시 예에 따른 반도체 소자의 텅스텐 플러그 형성 방법은 하부 도전층이 형성된 기판 상부에 층간 절연막을 형성하고 하부 도전층 상부의 일부가 노출되는 콘택 홀을 형성하는 단계와, 상기 콘택 홀을 포함하는 전체 구조 상부에 배리어 메탈을 형성하는 단계와, 전체 구조 상부에 텅스텐을 증착하는 단계와, 화학적 기계적 연마 공정에 의해 상기 텅스텐 및 배리어 메탈을 제거하는 단계를 포함하여 이루어지는 것을 특징으로 한다.In the method of forming a tungsten plug of a semiconductor device according to the first embodiment of the present invention for achieving the above object, an interlayer insulating layer is formed on a substrate on which a lower conductive layer is formed, and a contact hole is formed in which a portion of the upper portion of the lower conductive layer is exposed. Forming a barrier metal over the entire structure including the contact hole, depositing tungsten over the entire structure, and removing the tungsten and barrier metal by a chemical mechanical polishing process. Characterized in that made.

또한, 상술한 목적을 달성하기 위한 본 발명의 제 2 실시 예에 따른 반도체 소자의 텅스텐 플러그 형성 방법은 하부 도전층이 형성된 기판 상부에 층간 절연막을 형성하고 하부 도전층 상부의 일부가 노출되는 콘택 홀을 형성하는 단계와, 상기 콘택 홀을 포함하는 전체 구조 상부에 티타늄/티타늄 나이트라이드의 적층 구조를 갖는 배리어 메탈을 형성하는 단계와, 전체 구조 상부에 텅스텐을 증착하는 단계와, 상기 텅스텐 및 티타늄 나이트라이드막을 제거하여 상기 티타늄막을 노출시키는 단계와, 산소 플라즈마 처리를 실시하여 상기 노출된 티타늄막 표면을 티타늄 옥사이드막으로 변화시키는 단계를 포함하여 이루어지는 것을 특징으로 한다.In addition, in the method of forming a tungsten plug of a semiconductor device according to the second embodiment of the present invention for achieving the above object, a contact hole in which an interlayer insulating film is formed on a substrate on which a lower conductive layer is formed and a portion of an upper portion of the lower conductive layer is exposed. Forming a barrier metal having a laminated structure of titanium / titanium nitride on the entire structure including the contact hole, depositing tungsten on the entire structure, and forming the tungsten and titanium nitrate. And removing the ride film to expose the titanium film, and performing oxygen plasma treatment to change the exposed surface of the titanium film to a titanium oxide film.

마지막으로, 상술한 목적을 달성하기 위한 본 발명의 제 3 실시 예에 따른 반도체 소자의 텅스텐 플러그 형성 방법은 하부 도전층이 형성된 기판 상부에 층간 절연막을 형성하고 하부 도전층 상부의 일부가 노출되는 콘택 홀을 형성하는 단계와, 상기 콘택 홀을 포함하는 전체 구조 상부에 티타늄/티타늄 나이트라이드의 적층 구조를 갖는 배리어 메탈을 형성하는 단계와, 전체 구조 상부에 텅스텐을 증착하는 단계와, 상기 텅스텐 및 티타늄 나이트라이드막의 일부를 제거하는 단계를 포함하여 이루어지는 것을 특징으로 한다.Finally, in the method of forming a tungsten plug of a semiconductor device according to the third embodiment of the present invention for achieving the above object, a contact is formed in which an interlayer insulating film is formed on a substrate on which a lower conductive layer is formed, and a portion of the upper portion of the lower conductive layer is exposed. Forming a hole, forming a barrier metal having a laminated structure of titanium / titanium nitride on the entire structure including the contact hole, depositing tungsten on the entire structure, and forming the tungsten and titanium And removing a part of the nitride film.

도 1(a) 내지 1(c)는 종래 반도체 소자의 텅스텐 플러그 형성 방법을 설명하기 위한 도면.1 (a) to 1 (c) are views for explaining a method of forming a tungsten plug of a conventional semiconductor device.

도 2(a) 내지 2(c)는 본 발명의 제 1 실시 예에 따른 반도체 소자의 텅스텐 플러그 형성 방법을 설명하기 위한 소자의 단면도.2 (a) to 2 (c) are cross-sectional views of a device for explaining a method of forming a tungsten plug of a semiconductor device according to a first embodiment of the present invention.

도 3(a) 및 3(b)는 본 발명의 제 2 실시 예에 따른 반도체 소자의 텅스텐 플러그 형성 방법을 설명하기 위한 소자의 단면도.3 (a) and 3 (b) are cross-sectional views of a device for explaining a method of forming a tungsten plug of a semiconductor device according to a second embodiment of the present invention.

〈도면의 주요 부분에 대한 부호 설명〉<Description of Signs of Major Parts of Drawings>

21, 31, 41 : 반도체 기판 22, 32, 42 : 도전층21, 31, 41: semiconductor substrate 22, 32, 42: conductive layer

23, 33, 43 : 층간 절연막 24, 34, 44, : 티타늄막23, 33, 43: interlayer insulating film 24, 34, 44, titanium film

25, 35, 45 : 티타늄 나이트라이드막25, 35, 45: titanium nitride film

26, 36, 46 : 텅스텐층(텅스텐 플러그) 27, 37 : 티타늄 옥사이드(TixOy)26, 36, 46: tungsten layer (tungsten plug) 27, 37: titanium oxide (Ti x O y )

이하, 첨부된 도면을 참조하여 본 발며을 상세히 설명하기로 한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

도 2(a) 내지 2(c)는 본 발명의 제 1 실시 예에 따른 반도체 소자의 텅스텐 플러그 형성 방법을 설명하기 위한 소자의 단면도이다.2 (a) to 2 (c) are cross-sectional views of devices for explaining a method of forming a tungsten plug in a semiconductor device according to a first embodiment of the present invention.

도 2(a)에 도시된 바와 같이, 도전층(22) 등의 하부구조가 형성된 반도체 기판(21) 상부에 층간 절연막(23)을 형성하고, 메탈 콘택 마스크를 이용한 식각 공정으로 콘택 홀을 형성한다. 이후, 콘택 홀을 포함하는 전체 구조 상부에 티타늄(Ti)막(24) 및 티타늄 나이트라이드(TiN)막(25)을 순차적으로 형성하므로써 배리어 금속층을 형성한다. 이때, 티타늄막(24)은 500Å의 두께로 형성하고, 티타늄 나이트라이드막(25)은 CVD 방법을 이용하여 200Å의 두께로 형성한다. 다음에, 콘택 홀이 매립되도록 전체 구조 상부에 텅스텐(W)층을 형성한다.As shown in FIG. 2A, an interlayer insulating film 23 is formed on a semiconductor substrate 21 on which a lower structure such as the conductive layer 22 is formed, and a contact hole is formed by an etching process using a metal contact mask. do. Thereafter, the barrier metal layer is formed by sequentially forming the titanium (Ti) film 24 and the titanium nitride (TiN) film 25 on the entire structure including the contact hole. At this time, the titanium film 24 is formed to a thickness of 500 kPa, and the titanium nitride film 25 is formed to a thickness of 200 kPa using the CVD method. Next, a tungsten (W) layer is formed on the entire structure so that the contact holes are filled.

도 2(b)에 도시된 바와 같이, 층간 절연막(23) 상의 텅스텐(26), 티타늄 나이트라이드막(25) 및 티타늄막(24)을 제거하여, 텅스텐 플러그(26)를 형성한다. 이때, 텅스텐(26), 티타늄 나이트라이드막(25) 및 티타늄막(24)은 화학적 기계적 연마(CMP) 공정을 이용하여 제거한다. 텅스텐(26), 티타늄 나이트라이드막(25) 및 티타늄막(26)을 CMP공정으로 제거하므로 인하여, 텅스텐 플러그(26)의 손실을 감소시킬 수 있고, 가우징(gouging) 효과를 제거할 수 있으며, 웨이퍼 표면을 균일하게 할 수 있다. 또한, 티타늄막(24)을 제거하므로 인하여 층간절연막(23)이 노출되므로, 후속 금속배선 형성 공정시 금속 배선 패터닝을 위한 식각 타겟을 감소시킬 수 있는 효과가 있다.As shown in FIG. 2B, the tungsten 26, the titanium nitride film 25, and the titanium film 24 on the interlayer insulating film 23 are removed to form a tungsten plug 26. At this time, tungsten 26, titanium nitride film 25 and titanium film 24 are removed using a chemical mechanical polishing (CMP) process. By removing the tungsten 26, the titanium nitride film 25 and the titanium film 26 by the CMP process, the loss of the tungsten plug 26 can be reduced, and the gouging effect can be eliminated. The wafer surface can be made uniform. In addition, since the interlayer insulating film 23 is exposed by removing the titanium film 24, there is an effect that the etching target for metal wiring patterning may be reduced during the subsequent metal wiring forming process.

도 2(c)는 도 2(a)의 상태에서 층간 절연막(23) 상의 텅스텐(26) 및 티타늄 나이트라이드막(25)을 제거하여, 티타늄막(24)을 노출시킨 상태의 단면도이다. 이때, 텅스텐(26) 및 티타늄 나이트라이드막(25)은 CMP 공정 및 에치백 공정 중 어느 하나를 이용하여 제거한다. CMP 공정을 이용하는 경우에는 텅스텐 플러그(26)의 손실을 감소시킬 수 있고, 가우징(gouging) 효과를 제거할 수 있으며, 웨이퍼 표면을 더욱 균일하게 할 수 있다. 에치백 공정은 C-5300 DSP 장비를 사용하며 ECR, 헬리콘 및 ICP 에처 중 어느 하나를 사용한다.FIG. 2C is a cross-sectional view of the titanium film 24 exposed by removing the tungsten 26 and the titanium nitride film 25 on the interlayer insulating film 23 in the state of FIG. 2A. At this time, the tungsten 26 and the titanium nitride film 25 are removed using any one of a CMP process and an etch back process. When using the CMP process, the loss of the tungsten plug 26 can be reduced, the gouging effect can be eliminated, and the wafer surface can be made more even. The etch back process uses C-5300 DSP equipment and uses either ECR, Helicon or ICP Etchers.

이후, 후속 세정 공정시의 화학물질과 티타늄이 반응하여 표면이 거칠어지는 문제점을 해결하기 위하여, 산소 플라즈마 처리를 실시하여 티타늄막(24) 표면을 티타늄 옥사이드막(TixOy; 27)으로 변화시킨다. 티타늄 옥사이드막(27)은 수산화아민 계열을 이용하는 세정용액에 영향을 받지 않기 때문에, 후속 세정 단계에서 수산화아민 계열을 포함하는 ACT 화학 물질을 사용하더라도 티타늄에 가해지는 어택을 방지할 수 있고 웨이퍼 표면을 균일한 상태로 유지할 수 있게 된다. 또한, 티타늄 옥사이드막927)은 후속 금속 배선을 스퍼터 방식으로 증착할 때 용이하게 제거되므로 메탈 콘택 저항에 영향을 미치지 않는다.Subsequently, in order to solve the problem that the surface of the titanium chemical reacts with the titanium during the subsequent cleaning process, the surface of the titanium film 24 is changed to a titanium oxide film (Ti x O y ; 27) by performing oxygen plasma treatment. Let's do it. Since the titanium oxide film 27 is not affected by the cleaning solution using the amine hydroxide series, even if ACT chemicals including the amine hydroxide series are used in the subsequent cleaning step, the attack on titanium can be prevented and the wafer surface is prevented. It can be kept in a uniform state. In addition, the titanium oxide film 927 is easily removed when the subsequent metal wiring is deposited by the sputtering method and thus does not affect the metal contact resistance.

한편, 텅스텐(26) 및 티타늄 나이트라이드막(25)을 CMP 공정으로 제거하는 경우에는 폴리머 등의 부산물이 발생하지 않기 때문에 티타늄 옥사이드막(27) 형성과정을 생략할 수도 있다.In the case where the tungsten 26 and the titanium nitride film 25 are removed by the CMP process, by-products such as polymers do not occur, and thus the process of forming the titanium oxide film 27 may be omitted.

도 3(a) 및 3(b)는 본 발명의 제 2 실시 예에 따른 반도체 소자의 텅스텐 플러그 형성 방법을 설명하기 위한 소자의 단면도이다.3A and 3B are cross-sectional views of devices for describing a method of forming a tungsten plug in a semiconductor device according to a second embodiment of the present invention.

도 3(a)에 도시된 바와 같이, 도전층(32) 등의 하부구조가 형성된 반도체 기판(31) 상부에 층간 절연막(33)을 형성하고, 메탈 콘택 마스크를 이용한 식각 공정으로 콘택 홀을 형성한다. 이후, 콘택 홀을 포함하는 전체 구조 상부에 티타늄(Ti)막(34) 및 티타늄 나이트라이드(TiN)막(35)을 순차적으로 형성하므로써 배리어 금속층을 형성한다. 이때, 티타늄 나이트라이드막(35)은 PVD 방법을 이용하여 형성한다. PVD 방식은 CVD 방식에 비해 스텝 커버리지 특성이 낮으므로 콘택 홀 내부에는 CVD 방식으로 증착한 것과 거의 동일한 두께의 티타늄 나이트라이드막(25)이 형성되지만, 웨이퍼 표면인 층간 절연막(33) 상부에는 두꺼운 티타늄 나이트라이드막(25)이 형성되게 된다. 다음에, 콘택 홀이 매립되도록 전체 구조 상부에 텅스텐(W)층을 형성한다.As shown in FIG. 3A, an interlayer insulating layer 33 is formed on a semiconductor substrate 31 on which a substructure such as the conductive layer 32 is formed, and a contact hole is formed by an etching process using a metal contact mask. do. Thereafter, the barrier metal layer is formed by sequentially forming the titanium (Ti) film 34 and the titanium nitride (TiN) film 35 on the entire structure including the contact hole. At this time, the titanium nitride film 35 is formed using the PVD method. Since the PVD method has a lower step coverage characteristic than the CVD method, a titanium nitride film 25 having a thickness almost the same as that deposited by the CVD method is formed inside the contact hole, but a thick titanium is formed on the interlayer insulating film 33 on the wafer surface. The nitride film 25 is formed. Next, a tungsten (W) layer is formed on the entire structure so that the contact holes are filled.

도 3(b)에 도시된 바와 같이, 에치백 공정을 실시하여 층간 절연막(33) 상의 텅스텐(36) 및 티타늄 나이트라이드막(35)의 일부를 제거한다. 에치백 공정시 층간 절연막(33) 상에 두껍게 형성된 티타늄 나이트라이드막(35)이 식각 정지층으로 작용하여 티타늄막(24)이 노출되는 것을 방지할 수 있게 된다. 즉, 후속 세정 공정시 세정용액과 티타늄막(24)이 반응하는 것을 방지하는 보호막으로 작용하여, 티타늄의 어택을 억제하게 된다. 이에 따라 표면 거칠기가 개선된 텅스텐 플러그를 형성할 수 있다.As shown in FIG. 3B, an etch back process is performed to remove a part of the tungsten 36 and the titanium nitride film 35 on the interlayer insulating film 33. During the etch back process, the titanium nitride film 35 thickly formed on the interlayer insulating film 33 serves as an etch stop layer, thereby preventing the titanium film 24 from being exposed. That is, it acts as a protective film to prevent the cleaning solution from reacting with the titanium film 24 during the subsequent cleaning process, thereby suppressing the attack of titanium. As a result, it is possible to form a tungsten plug having improved surface roughness.

상술한 바와 같이 본 발명에 따르면 새로운 기술의 도입하거나 공정을 추가하지 않고도 텅스텐 플러그 형성 후의 웨이퍼 표면을 매끄럽게 제어할 수 있으므로, 후속 금속 배선 형성 공정의 안정화를 이룰 수 있고, 이에 따라 소자의 특성이 개선되고 수율이 증가되는 효과가 있다.As described above, according to the present invention, the surface of the wafer after tungsten plug formation can be smoothly controlled without introducing a new technology or adding a process, so that the subsequent metallization process can be stabilized, thereby improving device characteristics. And the yield is increased.

Claims (5)

하부 도전층이 형성된 기판 상부에 층간 절연막을 형성하고 하부 도전층 상부의 일부가 노출되는 콘택 홀을 형성하는 단계와,Forming an interlayer insulating film on the substrate on which the lower conductive layer is formed and forming a contact hole exposing a portion of the upper portion of the lower conductive layer; 상기 콘택 홀을 포함하는 전체 구조 상부에 티타늄/티타늄 나이트라이드의 적층 구조를 갖는 배리어 메탈을 형성하는 단계와,Forming a barrier metal having a stacked structure of titanium / titanium nitride on the entire structure including the contact hole; 전체 구조 상부에 텅스텐을 증착하는 단계와,Depositing tungsten over the entire structure, 상기 텅스텐 및 티타늄 나이트라이드막을 제거하여 상기 티타늄막을 노출시키는 단계와,Exposing the titanium film by removing the tungsten and titanium nitride films; 산소 플라즈마 처리를 실시하여 상기 노출된 티타늄막 표면을 티타늄 옥사이드막으로 변화시키는 단계를 포함하여 이루어지는 것을 특징으로 하는 반도체 소자의 텅스텐 플러그 형성 방법.And performing an oxygen plasma treatment to change the exposed titanium film surface to a titanium oxide film. 제 1 항에 있어서,The method of claim 1, 상기 텅스텐 및 티타늄 나이트라이드막은 화학적 기계적 연마 공정 및 에치백 공정 중 어느 하나를 사용하여 제거하는 것을 특징으로 하는 반도체 소자의 텅스텐 플러그 형성 방법.The tungsten and titanium nitride film is removed using any one of a chemical mechanical polishing process and an etch back process. 하부 도전층이 형성된 기판 상부에 층간 절연막을 형성하고 하부 도전층 상부의 일부가 노출되는 콘택 홀을 형성하는 단계와,Forming an interlayer insulating film on the substrate on which the lower conductive layer is formed and forming a contact hole exposing a portion of the upper portion of the lower conductive layer; 상기 콘택 홀을 포함하는 전체 구조 상부에 티타늄/티타늄 나이트라이드의 적층 구조를 갖는 배리어 메탈을 형성하는 단계와,Forming a barrier metal having a stacked structure of titanium / titanium nitride on the entire structure including the contact hole; 전체 구조 상부에 텅스텐을 증착하는 단계와,Depositing tungsten over the entire structure, 상기 텅스텐 및 티타늄 나이트라이드막의 일부를 제거하는 단계를 포함하여 이루어지는 것을 특징으로 하는 반도체 소자의 텅스텐 플러그 형성 방법.And removing a portion of the tungsten and titanium nitride films. 제 3 항에 있어서,The method of claim 3, wherein 상기 티타늄 나이트라이드막은 PVD 방법으로 형성하는 것을 특징으로 하는 반도체 소자의 텅스텐 플러그 형성 방법.The titanium nitride film is a tungsten plug forming method of a semiconductor device, characterized in that formed by the PVD method. 제 3 항에 있어서,The method of claim 3, wherein 상기 텅스텐 및 티타늄 나이트라이드막의 일부는 상기 티타늄 나이트라이드막을 식각 정지층으로 하여 에치백 공정을 사용하여 제거하는 것을 특징으로 하는 반도체 소자의 텅스텐 플러그 형성 방법.A portion of the tungsten and titanium nitride film is removed using an etch back process using the titanium nitride film as an etch stop layer.
KR1019980061450A 1998-12-30 1998-12-30 Tungsten plug formation method of semiconductor device KR100284139B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019980061450A KR100284139B1 (en) 1998-12-30 1998-12-30 Tungsten plug formation method of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019980061450A KR100284139B1 (en) 1998-12-30 1998-12-30 Tungsten plug formation method of semiconductor device

Publications (2)

Publication Number Publication Date
KR20000044947A KR20000044947A (en) 2000-07-15
KR100284139B1 true KR100284139B1 (en) 2001-04-02

Family

ID=19568202

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019980061450A KR100284139B1 (en) 1998-12-30 1998-12-30 Tungsten plug formation method of semiconductor device

Country Status (1)

Country Link
KR (1) KR100284139B1 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100705397B1 (en) * 2005-07-13 2007-04-10 삼성전자주식회사 Method of forming tungsten layer having low resistance

Also Published As

Publication number Publication date
KR20000044947A (en) 2000-07-15

Similar Documents

Publication Publication Date Title
KR101225642B1 (en) Method for formation of contact plug of semiconductor device using Ｈ2 remote plasma treatment
US6379782B2 (en) Semiconductor device formed with metal wiring on a wafer by chemical mechanical polishing, and method of manufacturing the same
US5747383A (en) Method for forming conductive lines and stacked vias
TWI236094B (en) Method for forming multi-layer metal line of semiconductor device
US6812133B2 (en) Fabrication method of semiconductor device
US6645864B1 (en) Physical vapor deposition of an amorphous silicon liner to eliminate resist poisoning
US20020142582A1 (en) Method for forming copper lines for semiconductor devices
US6831007B2 (en) Method for forming metal line of Al/Cu structure
KR100284139B1 (en) Tungsten plug formation method of semiconductor device
JP2008305921A (en) Semiconductor device and manufacturing method therefor
US20070007654A1 (en) Metal line of semiconductor device and method for forming thereof
US6306771B1 (en) Process for preventing the formation of ring defects
KR100190055B1 (en) White electrode manufacturing method of semiconductor device
US7488681B2 (en) Method for fabricating Al metal line
KR100315039B1 (en) Method for forming metal interconnection line of semiconductor device
KR100476707B1 (en) Method of manufacturing a semiconductor device
KR100336837B1 (en) Method of forming a tungsten plug in a semiconductor device
KR20030002119A (en) Method for forming via hole by dual damascene process
KR100552836B1 (en) Semiconductor device and formation method of metal line in the semiconductor device
KR100571677B1 (en) Tungsten deposition method for preventing from key-hole formation
KR100274346B1 (en) Method of forming a metal wiring in a semiconductor device
KR100777365B1 (en) Method for forming a metal line
KR100299380B1 (en) Method of forming metal interconnection for semiconductor device
JPH09237768A (en) Semiconductor device and manufacture thereof
KR100399602B1 (en) Method for manufacturing metal line of semiconductor device

Legal Events

Date Code Title Description
A201 Request for examination
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20081125

Year of fee payment: 9

LAPS Lapse due to unpaid annual fee