JPH04196486A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH04196486A JPH04196486A JP32755390A JP32755390A JPH04196486A JP H04196486 A JPH04196486 A JP H04196486A JP 32755390 A JP32755390 A JP 32755390A JP 32755390 A JP32755390 A JP 32755390A JP H04196486 A JPH04196486 A JP H04196486A
- Authority
- JP
- Japan
- Prior art keywords
- film
- insulating film
- semiconductor device
- barrier
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 43
- 230000004888 barrier function Effects 0.000 claims abstract description 26
- 239000000758 substrate Substances 0.000 claims abstract description 16
- 239000005380 borophosphosilicate glass Substances 0.000 claims abstract description 13
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims abstract description 11
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims abstract description 8
- 229910052796 boron Inorganic materials 0.000 claims abstract description 8
- 229910021332 silicide Inorganic materials 0.000 claims description 6
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 6
- 229910000838 Al alloy Inorganic materials 0.000 claims description 3
- 238000010438 heat treatment Methods 0.000 abstract description 11
- 238000009792 diffusion process Methods 0.000 abstract description 7
- 150000004767 nitrides Chemical class 0.000 abstract description 6
- 150000001875 compounds Chemical class 0.000 abstract description 4
- 238000000059 patterning Methods 0.000 abstract description 2
- 238000009413 insulation Methods 0.000 abstract 5
- 229910004339 Ti-Si Inorganic materials 0.000 abstract 1
- 229910010978 Ti—Si Inorganic materials 0.000 abstract 1
- 238000004519 manufacturing process Methods 0.000 description 5
- 230000000694 effects Effects 0.000 description 4
- 239000002184 metal Substances 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 230000001681 protective effect Effects 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 229910008484 TiSi Inorganic materials 0.000 description 1
- 229910008479 TiSi2 Inorganic materials 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- DFJQEGUNXWZVAH-UHFFFAOYSA-N bis($l^{2}-silanylidene)titanium Chemical compound [Si]=[Ti]=[Si] DFJQEGUNXWZVAH-UHFFFAOYSA-N 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 230000001771 impaired effect Effects 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 238000001556 precipitation Methods 0.000 description 1
- 230000001737 promoting effect Effects 0.000 description 1
- 150000003377 silicon compounds Chemical class 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
Landscapes
- Electrodes Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の目的〕
（産業上の利用分野）
本発明は絶縁膜とＡｇ系配線膜との間にバリアメタルと
してのＴｉＮ膜を有する半導体装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a semiconductor device having a TiN film as a barrier metal between an insulating film and an Ag-based wiring film.
（従来の技術）
従来の半導体装置の断面を第４図に示す。この＋−導体
装置は、半導体基板１上にＢＰＳＧ膜３が形成され、こ
のＢ Ｐ Ｓ （Ｊｋ３には、基板１上に形成された拡
散層２とのコンタクトを取るためのコンタクトホールが
開孔されている。そして、二のコンタ、クトホールが開
孔されたＢＰＳＧ膜３上にＴｉ膜５及びＴｆＮＩ１７か
らなるバリア膜が形成され、このバリア膜上にＡｌｌ又
はＡｌ１合金からなるＡｌｌ系配線膜８が形成されてい
る。上述のバリア膜は、ＡｌとＳｉが反応することによ
って生じる、Ａｆｌ系配線のコンタクト部の接合突き抜
けやＳｉ析出によるコンタクト抵抗増大等を抑制するた
めに設けられるものである。なお、Ｔ ｉ ＠ ５及び
ＴｉＮ膜７からなるバリア膜の形成直後には、コンタク
ト部においてＳｉ表面の薄い酸化物のＴｉによる還元及
びＴｉとＳｉのシリサイプ−ジョンを促進してコンタク
ト抵抗を低減するための熱処理が行われる。この熱処理
によって拡散層２近傍のＴｉ＠はＴｉ−８ｔ化合物６に
嚢化する。(Prior Art) A cross section of a conventional semiconductor device is shown in FIG. This +-conductor device has a BPSG film 3 formed on a semiconductor substrate 1, and a contact hole for making contact with a diffusion layer 2 formed on the substrate 1 is opened in this BPSG film 3. Then, a barrier film made of a Ti film 5 and TfNI 17 is formed on the BPSG film 3 in which the second contact hole is formed, and an All-based wiring film 8 made of All or Al1 alloy is formed on this barrier film. The above-mentioned barrier film is provided to suppress junction penetration of the contact portion of the Afl-based wiring and an increase in contact resistance due to Si precipitation, which are caused by the reaction between Al and Si. Immediately after forming the barrier film consisting of Ti@5 and the TiN film 7, the contact resistance is reduced by promoting the reduction of the thin oxide on the Si surface by Ti and the silicidation of Ti and Si in the contact portion. A heat treatment is performed for this purpose.By this heat treatment, Ti@ in the vicinity of the diffusion layer 2 is encapsulated into a Ti-8t compound 6.
又、図示はしていないが、Ａ４７系配線膜８形成後、こ
のＡＩ系配線７Ｎ！８をバターニングして配線を形成し
、その後に絶縁保護膜を形成してパッド開孔を行う。Although not shown, after the A47-based wiring film 8 is formed, this AI-based wiring 7N! 8 is patterned to form wiring, and then an insulating protective film is formed and pad holes are formed.
（発明が解決しようとする課題）
このような半導体装置においては、パッド部が下地絶縁
膜３との界面近傍で剥離する、すなわち密着性不良が生
じるという問題があった。二の密着性不良′は、バリア
膜形成後の熱処理によって発生するものて、パ、ツド部
ドのＴｉ膜５と下地絶縁膜３とが反応して脆い層が形成
されることによるものである。又、この密着性不良は下
地絶縁膜３の構成成分にも影響され、特にＢ（はう素）
の含有量が高い程発生し品い。(Problems to be Solved by the Invention) Such a semiconductor device has a problem in that the pad portion peels off near the interface with the base insulating film 3, that is, poor adhesion occurs. The second problem, poor adhesion, is caused by the heat treatment after the formation of the barrier film, and is caused by the reaction between the Ti film 5 on the pad and the base insulating film 3, forming a brittle layer. . In addition, this poor adhesion is also affected by the constituent components of the base insulating film 3, especially B (boron).
The higher the content, the higher the quality.
本発明は上記問題点を考慮してなされたものであって、
密着性に対して高い信頼性を有する半導体装置を提供す
ることを目的とする。The present invention has been made in consideration of the above problems, and includes:
An object of the present invention is to provide a semiconductor device having high reliability in terms of adhesion.
Ｃ発明の構成〕
（課題を解決するための手段）
第１の発明の半導体装置は、半導体基板上に形成された
絶縁膜と、この絶縁膜上に形成されるホウ素を含まない
絶縁膜層と、このホウ素を含まない絶縁膜層上に形成さ
れるＴｉ及びＴｉＮからなる２層構造のバリア膜と、こ
のバリア膜上に形成されるＡｇ又はｐ、（ｔ９金からな
るＡｌｌ系配線膜とを備えていることを特徴とする。C Structure of the Invention] (Means for Solving the Problems) The semiconductor device of the first invention includes an insulating film formed on a semiconductor substrate, an insulating film layer not containing boron formed on the insulating film, and an insulating film layer formed on the insulating film. , a two-layer barrier film made of Ti and TiN formed on this boron-free insulating film layer, and an All-based wiring film made of Ag, p, (t9 gold) formed on this barrier film. It is characterized by having
ｍ２の発明の半導体装置は、半導体基板上に形成された
絶縁膜と、この絶縁膜に開孔されたコンタクトホールの
底部の半導体基板表面のみに形成されるＴｉシリサイド
層と、このＴｉシリサイド層及び前記絶縁膜上に形成さ
れるＴｉＮ＠と、このＴｉＮ膜上に形成されるＡＩ！又
はＡｌ合金からなるＡＪ７系配系膜線膜備えていること
を特徴とする。The semiconductor device of the invention of m2 includes an insulating film formed on a semiconductor substrate, a Ti silicide layer formed only on the surface of the semiconductor substrate at the bottom of a contact hole opened in this insulating film, and this Ti silicide layer and TiN@ formed on the insulating film and AI! formed on this TiN film! Alternatively, it is characterized by being equipped with an AJ7 system membrane wire film made of an Al alloy.
（作 用）
二のように構成された第１の発明の半導体装置によれば
、絶縁膜（下地絶縁膜）とバリア膜との間にホウ素を含
まない絶縁膜層が設けられている。(Function) According to the semiconductor device of the first invention configured as in item 2, an insulating film layer that does not contain boron is provided between the insulating film (base insulating film) and the barrier film.
これによ゛リバリア膜の熱処理の温度にががゎらず、下
地絶縁膜とバリア膜との界面近傍での剥離する割合、す
なわち界面はがれ率をほぼ零とすることができ、密着性
に対して高い信頼性を得ることができる。As a result, the temperature of heat treatment of the barrier film does not vary, and the peeling rate near the interface between the base insulating film and the barrier film, that is, the interface peeling rate, can be reduced to almost zero, and the adhesion is reduced. High reliability can be obtained.
上述のように構成された第２の発明の半導体装置によれ
ば、絶縁膜上にはＴｆｆｉではなくてＴ ｉ Ｎ＠が形
成されているため、Ｔｉシリサイド層を形成するに必要
な熱処理が行われても、絶縁膜とＴｉＮｆｉとの界面の
剥離はほとんど生じない。According to the semiconductor device of the second invention configured as described above, since TiN@ instead of Tffi is formed on the insulating film, the heat treatment necessary to form the Ti silicide layer is not performed. Even if the TiNfi film is diluted, peeling at the interface between the insulating film and the TiNfi hardly occurs.
これにより密着性に対して高い信頼性を得ることができ
る。Thereby, high reliability in adhesion can be obtained.
（実施例）
第１の発明による半導体装置の一実施例を第１図を参照
して説明する。第１図は上記実施例の半導体装置の製造
工程断面図である。先ず半導体基板１上にＢＰＳＧ膜３
を形成し、更にこのＢＰＳＧ膜３の上に窒化膜、例えば
ＳｉＮ膜４をＣＶＤ法を用いて形成する（第１図（ａ）
参照）。(Embodiment) An embodiment of the semiconductor device according to the first invention will be described with reference to FIG. FIG. 1 is a cross-sectional view of the manufacturing process of the semiconductor device of the above embodiment. First, a BPSG film 3 is formed on a semiconductor substrate 1.
A nitride film, for example, a SiN film 4 is further formed on this BPSG film 3 using the CVD method (see FIG. 1(a)).
reference).
その後、基板１上の拡散層２とのコンタクトを取るため
フンタクトホールを開孔する（第１図（ａ）参照）。Thereafter, a hole is opened to make contact with the diffusion layer 2 on the substrate 1 (see FIG. 1(a)).
次にＴｉ膜５及びＴｉＮ膜７からなるバリアＡｌ！′を
形成する（第１図（ｂ）参照）。そしてコンタクト抵抗
を低減するために約５００〜８００℃の温度で上記バリ
ア膜の熱処理を行って、拡散層２近傍のＴｉ膜５をＴｉ
−Ｓｉ化合物に変える（第１図（Ｃ）参照）。その後、
Ａ、Ｑ采配線膜８を堆積しく第１図（Ｃ）参照）、バタ
ーニングを行って配線を形成する（図示せず）。そして
絶縁保護膜を形成後、パッド開孔を行う（図示せず）。Next, barrier Al! made of Ti film 5 and TiN film 7! ' (see Figure 1(b)). Then, in order to reduce the contact resistance, the barrier film is heat-treated at a temperature of about 500 to 800°C, and the Ti film 5 near the diffusion layer 2 is changed to a Ti film.
-Si compound (see FIG. 1(C)). after that,
The A and Q frame wiring films 8 are deposited (see FIG. 1C) and patterned to form wiring (not shown). After forming the insulating protective film, pad holes are formed (not shown).
このようにして形成されたパッド部にワイヤ接続した後
１とこのワイヤめ剥離テストを行った結果を第３図のグ
ラフＡｌに示す。第３図に示すグラフの横軸はバリア膜
の熱処理温度を示し、縦軸はパッド部の、下地絶縁膜と
の界面がはがれる割合すなわち、界面はがれ率を示して
いる。本実施例の半導体装置の製造において、バリア膜
の熱処理を比較的高温（約５００〜８００℃）で行って
も界面はがれ率はほぼ零であることがグラフｇ１から分
かる。これに対して従来の半導体装置の、バリア膜の熱
処理温度に対する界面はがれ率をグラフｇ に示すが、
このグラフＡｌ２から分かるように熱処理温度が高くな
るにつれて界面はがれ率も上昇していることが分かる。After a wire was connected to the pad portion thus formed, a peel test was performed on the wire, and the results are shown in graph Al in FIG. The horizontal axis of the graph shown in FIG. 3 indicates the heat treatment temperature of the barrier film, and the vertical axis indicates the rate at which the interface between the pad portion and the underlying insulating film peels off, that is, the interface peeling rate. It can be seen from graph g1 that even when the barrier film is heat-treated at a relatively high temperature (approximately 500 to 800° C.) in manufacturing the semiconductor device of this example, the interface peeling rate is almost zero. In contrast, graph g shows the interface peeling rate versus heat treatment temperature of the barrier film in a conventional semiconductor device.
As can be seen from this graph Al2, as the heat treatment temperature increases, the interface peeling rate also increases.
したがって本実施例の半導体装置によれば界面はかり率
がほぼ零、すなわち密着性不良はほとんど生じず、信頼
性の高いものとなる。Therefore, according to the semiconductor device of this embodiment, the interface coverage rate is almost zero, that is, almost no adhesion failure occurs, and the reliability is high.
なお、上記実施例においては゛、バリア膜とＢ Ｐ Ｓ
Ｇ＠３との間の絶縁膜としてＳｉＮ膜を設けたが、こ
のＳｉＮ膜の代わりにＡＪ７Ｎからなる窒化膜を設けて
も同様の効果を得ることができる。In addition, in the above embodiment, the barrier film and the BPS
Although a SiN film is provided as an insulating film between G@3 and G@3, the same effect can be obtained by providing a nitride film made of AJ7N instead of this SiN film.
又、バリア膜とＢＰＳＧ膜との間の絶縁膜として窒化膜
の代わりにポリシリコン又はシリコン化合物からなる膜
を設けても上記実施例と同様の効果を害ることができる
。Further, even if a film made of polysilicon or a silicon compound is provided as an insulating film between the barrier film and the BPSG film instead of the nitride film, the same effect as in the above embodiment can be impaired.
又、窒化膜の代わりに、Ｂを含まない酸化膜、例えばＣ
ＶＤ法を用いて形成するＳｉＯ２膜を用いても、従来の
半導体装置に比べて密着性不良を改善することができる
。但し、この場合界面はがれ率はほぼ零とはならない。Also, instead of the nitride film, an oxide film that does not contain B, such as C
Even with the use of a SiO2 film formed using the VD method, poor adhesion can be improved compared to conventional semiconductor devices. However, in this case, the interface peeling rate is not approximately zero.
なお、上記実施例においては、下地絶縁膜がＢＰＳＧ膜
である場合について説明したが、ＢＰＳＧ膜の代わりに
酸化膜、例えばＳ ＩＯ２＠を用いた場合でも本実施例
と同様の効果を得る二とかできる。In the above embodiment, the case where the underlying insulating film is a BPSG film has been described, but the same effect as in this embodiment can be obtained even when an oxide film, for example, SIO2@, is used instead of the BPSG film. can.
次に、第２の発明による半導体装置の一実施例を第２図
を参照して説明する。第２図は上記実施例の半導体装置
の製造工程断面図である。この半導体装置は先ず、半導
体基板１上に例えばＢＰＳＧ膜３を形成し、半導体基板
１上の拡散層２とのコンタクトを取るためのコンタクト
ホールをＢＰＳＧ膜３に開孔する。その後、ＴｉｉＳを
スパッタ法を用いて堆積する（第２図（ａ）参照）。そ
の後史にその上に例えばＴｉＮ膜（図示せず）をスパッ
タ法を用いて堆積させるか又はＴｉｉＳの表面の窒化を
行った後に、約５００〜８００℃の温度で熱処理を行う
。Next, an embodiment of the semiconductor device according to the second invention will be described with reference to FIG. FIG. 2 is a cross-sectional view of the manufacturing process of the semiconductor device of the above embodiment. In this semiconductor device, first, for example, a BPSG film 3 is formed on a semiconductor substrate 1, and a contact hole for making contact with a diffusion layer 2 on the semiconductor substrate 1 is opened in the BPSG film 3. Thereafter, TiiS is deposited using a sputtering method (see FIG. 2(a)). Thereafter, for example, a TiN film (not shown) is deposited thereon by sputtering or the surface of the TiiS is nitrided, and then heat treatment is performed at a temperature of about 500 to 800°C.
すると、ＴｉｉＳとＳｉの界面、すなわちＴｉｉＳと半
導体基板１の界面のみにＴｉとＳｉの化合物（ＴｉＳｉ
２）からなる層６が形成され、このＴ ｉＳ Ｌ ２層
を残してＴｉｉＳ又は、ＴｉＮ膜及びＴｉｉＳを選択的
にエツチング除去する（第２図（ｂ）参照）。その後Ｔ
ｉＮ膜７を堆積した後、ＡＩｌ又はＡｌ１ｅ：金からな
る配線膜８を形成する（第２図（Ｃ）参照）。そしてバ
ターニングを行って配線を形成した後、絶縁保護膜（図
示せず）を堆積してパッド開孔を行う（図示せず）。Then, a compound of Ti and Si (TiSi
A layer 6 consisting of 2) is formed, and TiiS or the TiN film and TiiS are selectively etched away leaving this T iS L 2 layer (see FIG. 2(b)). Then T
After depositing the iN film 7, a wiring film 8 made of Al or Al1e:gold is formed (see FIG. 2(C)). After patterning is performed to form wiring, an insulating protective film (not shown) is deposited, and pad holes are formed (not shown).
このようにして形成された半導体装置のノくラド部にワ
イヤ接続した後、このワイヤの剥離テストを行っても、
パッド部の、下地絶縁膜３とバリアメタル７との界面近
傍で剥離する割合、すなわち界面はがれ率は、バリアメ
タル５の熱処理ａ度に依らずほぼ零であった。これによ
り、本実施例の半導体装置は密着性不良は生じず、信頼
性の高いものとなる。Even if a peel test is performed on the wire after connecting the wire to the nodal part of the semiconductor device formed in this way,
The peeling rate near the interface between base insulating film 3 and barrier metal 7 in the pad portion, that is, the interface peeling rate, was almost zero regardless of the degree of heat treatment of barrier metal 5. As a result, the semiconductor device of this example does not suffer from poor adhesion and is highly reliable.
なお、本実施例の半導体装置のコンタクト抵抗を計量ｌ
したとこる従来の半導体装置と同程度て間−題ない。Note that the contact resistance of the semiconductor device of this example was measured by l.
There is no problem as it is on the same level as a conventional semiconductor device.
本発明によれば密も性に対して高い（Ｑ顕性を得ること
ができる。According to the present invention, it is possible to obtain high (Q-sensitivity) relative to density.
第１図は第１の発明による半導体装置の一実施例の製造
工程を示す断面図、第２図は第２の発明による半導体装
置の一実施例の製造工程を示す断面図、第３図は本発明
の詳細な説明するグラフ、第４図は従来の半導体装置の
断面図である。
１・・・半導体基板、２・・・拡散層、３・・・ＢＰＳ
Ｇ膜、４・・・５ｉＮＰＡｌ５・・・ＴｉＷＩＩｃ１６
・・・ＴｉＳｉ２膜、７・・・ＴｉＮ膜、８・・・Ａｊ
７系配系層線層願人代理人 佐 藤 −雄
第１図FIG. 1 is a sectional view showing the manufacturing process of an embodiment of the semiconductor device according to the first invention, FIG. 2 is a sectional view showing the manufacturing process of an embodiment of the semiconductor device according to the second invention, and FIG. A graph explaining the present invention in detail, and FIG. 4 is a cross-sectional view of a conventional semiconductor device. 1... Semiconductor substrate, 2... Diffusion layer, 3... BPS
G film, 4...5iNPAl5...TiWIIc16
...TiSi2 film, 7...TiN film, 8...Aj
7th system distribution layer applicant agent Sato -O Figure 1
Claims (1)
に形成されるホウ素を含まない絶縁膜層と、このホウ素
を含まない絶縁膜層上に形成されるＴｉ及びＴｉＮから
なる２層構造のバリア膜と、このバリア膜上に形成され
るＡｌ又はＡｌ合金からなるＡｌ系配線膜とを備えてい
ることを特徴とする半導体装置。 ２、前記ホウ素を含まない絶縁膜層は、 ＳｉＮ又はＡｌＮのいずれか一方の材料によって形成さ
れていることを特徴とする請求項１記載の半導体装置。 ３、半導体基板上に形成された絶縁膜と、この絶縁膜に
開孔されたコンタクトホールの底部の半導体基板表面の
みに形成されるＴｉシリサイド層と、このＴｉシリサイ
ド層及び前記絶縁膜上に形成されるＴｉＮ膜と、このＴ
ｉＮ膜上に形成されるＡｌ又はＡｌ合金からなるＡｌ系
配線膜とを備えていることを特徴とする半導体装置。 ４、前記半導体基板上に形成される絶縁膜はＢＰＳＧ膜
であることを特徴とする請求項１乃至３のいずれかに記
載の半導体装置。[Claims] 1. An insulating film formed on a semiconductor substrate, an insulating film layer not containing boron formed on the insulating film, and a Ti insulating film layer formed on the insulating film layer not containing boron. A semiconductor device comprising: a barrier film having a two-layer structure made of TiN; and an Al-based wiring film made of Al or an Al alloy formed on the barrier film. 2. The semiconductor device according to claim 1, wherein the insulating film layer not containing boron is formed of one of SiN and AlN. 3. An insulating film formed on a semiconductor substrate, a Ti silicide layer formed only on the surface of the semiconductor substrate at the bottom of a contact hole opened in this insulating film, and a Ti silicide layer formed on this Ti silicide layer and the insulating film. TiN film and this T
A semiconductor device comprising an Al-based wiring film made of Al or an Al alloy formed on an iN film. 4. The semiconductor device according to claim 1, wherein the insulating film formed on the semiconductor substrate is a BPSG film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP32755390A JP2848694B2 (en) | 1990-11-28 | 1990-11-28 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP32755390A JP2848694B2 (en) | 1990-11-28 | 1990-11-28 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH04196486A true JPH04196486A (en) | 1992-07-16 |
| JP2848694B2 JP2848694B2 (en) | 1999-01-20 |
Family
ID=18200353
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP32755390A Expired - Lifetime JP2848694B2 (en) | 1990-11-28 | 1990-11-28 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2848694B2 (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0660392A1 (en) * | 1993-12-17 | 1995-06-28 | STMicroelectronics, Inc. | Method and interlevel dielectric structure for improved metal step coverage |
| US5793114A (en) * | 1993-12-17 | 1998-08-11 | Sgs-Thomson Microelectronics, Inc. | Self-aligned method for forming contact with zero offset to gate |
| US6051864A (en) * | 1993-12-17 | 2000-04-18 | Stmicroelectronics, Inc. | Memory masking for periphery salicidation of active regions |
| US6344411B1 (en) | 1997-11-21 | 2002-02-05 | Nec Corporation | OHMIC contact plug having an improved crack free tin barrier metal in a contact hole and method of forming the same |
| JP2004063610A (en) * | 2002-07-26 | 2004-02-26 | Seiko Instruments Inc | Manufacturing method of semiconductor device |
-
1990
- 1990-11-28 JP JP32755390A patent/JP2848694B2/en not_active Expired - Lifetime
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0660392A1 (en) * | 1993-12-17 | 1995-06-28 | STMicroelectronics, Inc. | Method and interlevel dielectric structure for improved metal step coverage |
| US5793114A (en) * | 1993-12-17 | 1998-08-11 | Sgs-Thomson Microelectronics, Inc. | Self-aligned method for forming contact with zero offset to gate |
| US6051864A (en) * | 1993-12-17 | 2000-04-18 | Stmicroelectronics, Inc. | Memory masking for periphery salicidation of active regions |
| US6284584B1 (en) * | 1993-12-17 | 2001-09-04 | Stmicroelectronics, Inc. | Method of masking for periphery salicidation of active regions |
| US6514811B2 (en) | 1993-12-17 | 2003-02-04 | Stmicroelectronics, Inc. | Method for memory masking for periphery salicidation of active regions |
| US6812142B1 (en) | 1993-12-17 | 2004-11-02 | Stmicroelectronics, Inc. | Method and interlevel dielectric structure for improved metal step coverage |
| US6344411B1 (en) | 1997-11-21 | 2002-02-05 | Nec Corporation | OHMIC contact plug having an improved crack free tin barrier metal in a contact hole and method of forming the same |
| US6787913B2 (en) | 1997-11-21 | 2004-09-07 | Nec Electronics Corporation | Ohmic contact plug having an improved crack free TiN barrier metal in a contact hole and method of forming the same |
| JP2004063610A (en) * | 2002-07-26 | 2004-02-26 | Seiko Instruments Inc | Manufacturing method of semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2848694B2 (en) | 1999-01-20 |
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