JPH0758111A - Multilayer interconnection structure for semiconductor device and its manufacture - Google Patents

Abstract

PURPOSE:To improve the embedding characteristics to a connecting hole of an upper wiring forming film to be coated by high temperature spattering method by improving the wettability of a barrier metal layer and by enlarging connecting holes. CONSTITUTION:Lower layer wirings 13 and 14 are formed on an insulation layer 12 provided on the upper layer of a substrate 11, a first silicon nitride film 15 is formed to a state of covering the above, and flattening embedding portions 19, 20 and 21 are formed on low portions 16, 17 and 18 on the first silicon nitride film 15 at both the sides of the lower layer wiring 13 and 14. Moreover, a second silicon nitride film 22 is formed on the first silicon nitride film 15 and on the first silicon nitride film 15 and the flattening embedding portions 19, 20 and 21; connecting holes 23 and 24 are formed on the first and second silicon nitride films 15 and 22 over the lower layer wirings 13 and 14; a barrier metal layer 25 is formed on the second silicon nitride film 22 together with the inner wall of said holes; and an upper wiring formation layer 26 is formed in the state of embedding the connecting holes 23 and 24 on said layer 25.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a multilayer wiring structure for a semiconductor device.

[0002]

2. Description of the Related Art As semiconductor devices have been highly integrated and miniaturized, a technique for filling a contact hole having a high aspect ratio has been required. At present, a so-called high-temperature aluminum alloy sputtering method has been proposed as an embedding process that is highly producible for mass production, in which the conventional aluminum alloy sputtering method is performed while the substrate is heated. Alternatively, a so-called blanket tungsten CVD method has been proposed in which a metal film is formed in a state of being embedded in a connection hole and then the entire surface is etched to leave the metal film in the connection hole. Alternatively, a selective tungsten CVD method has been proposed in which a metal is selectively grown only in the connection hole to form a metal plug.

Particularly, the high temperature aluminum alloy sputtering method is
It has the feature of low process cost.

And as a technique for forming a multilayer wiring,
A planarization technique for the interlayer insulating film is also important. Tetraethoxysilane (TEOS) is used as a planarization technique for the interlayer insulating film.
After forming a silicon oxide film in a state of covering the wiring by a CVD method using SOG (Spin (Spin)
A method of applying an on glass) film to planarize the film has been proposed.

Further, since the interlayer insulating film is made of silicon oxide, the adhesion of the barrier metal made of the titanium film formed on the inner wall of the connection hole is not good. Therefore, in order to improve adhesion, a sidewall made of silicon nitride is formed on the sidewall of the connection hole.

Next, a method of manufacturing a multi-layer wiring structure, which comprises the above flattening technique, the technique of forming a sidewall made of silicon nitride in the contact hole, and the technique of using the high temperature aluminum alloy sputtering method to form the upper layer interconnection, This will be described with reference to the manufacturing process diagram of the conventional example shown in FIG.

As shown in (1) of FIG. 5, in the first step, the lower layer wiring 5 is formed on the insulating layer 52 provided on the upper layer of the substrate 51.
3, 54 are formed.

Then, the second step shown in FIG. 5B is performed. In this process, tetraethoxysilane (TEOS)
A first silicon oxide film 55 is formed in a state of covering the lower wirings 53 and 54 by the CVD method using. After that, by the spin coating technique, the lower portions 56, 57 on the first silicon oxide film 55 on both sides of the lower layer wirings 53, 54,
An SOG (Spin on glass) film is applied in a state of embedding the upper part of 58. Then, by etching back, a portion of the flattening layer 59 indicated by a two-dot chain line is formed. Then, the first silicon oxide film 55 is formed by reactive ion etching.
The flattening layer 59 is removed to expose the upper part of
Flattening embedded portions 60, 61 and 62 made of a flattening layer (59) are formed on the lower portions 56, 57 and 58.

Subsequently, a third step shown in FIG. 5C is performed. In this process, tetraethoxysilane (TEOS)
The first silicon oxide film 5 is formed by the CVD method using
A second silicon oxide film 63 is formed on the surface 5 and on the flattening buried portions 60, 61 and 62.

Then, a fourth step shown in FIG. 5D is performed. In this step, connection holes 64 and 65 are formed in the first and second silicon oxide films 55 and 63 on the wirings 53 and 54 by the lithography technique and etching.

Thereafter, a fourth step shown in FIG. 5 (5) is performed. In this process, the connection holes 64 and 65 are formed by the CVD method.
A plasma silicon nitride (P-SiN) film is formed on the inner wall of the second silicon oxide film 63. Then, by etching back, only the side walls 66, 6 of the plasma silicon nitride film are formed only on the side walls of the connection holes 64, 65.
Form 7.

Next, the connection holes 64,
A barrier metal layer 71 made of a titanium film is formed on the inner wall of 65 and the second silicon oxide film 63. Then, the connection hole 64,
A wiring forming film 72 made of an aluminum alloy is formed on the barrier metal layer 71 in a state where the inside of 65 is embedded. At this time, the substrate 51 is heated to a temperature at which the wiring forming film 72 sufficiently flows into the connection holes 64 and 65.

Then, the wiring forming film 72 and the barrier metal layer 7 are formed by photolithography and etching.
1 is removed, and a wiring 73 connected to the lower wirings 53 and 54 through the connection holes 64 and 65 is formed by the wiring forming film 72 and the barrier metal layer 71.

[0014]

However, in the wiring structure obtained by the above-described method for manufacturing a wiring structure, there is a problem regarding the sidewall formed on the side wall of the connection hole. That is, the sidewall of the plasma silicon nitride film is necessary to improve the characteristics of embedding the high temperature aluminum alloy in the connection hole, but since it is formed after the connection hole is opened, the number of working steps is increased and the connection hole There are problems such as reduction in diameter and deterioration of electromigration resistance.

For example, when the diameter of the connection hole is 0.8 μm, the side wall thickness is about 0.65 μm. In this case, the cross-sectional area of the connection hole is about 2/3.

Then, the allowable current value Imax at the connection hole
Is expressed as Imax = Jmax × A, where Jmax is the allowable current density of the connection hole and A is the cross-sectional area of the connection hole. Therefore, even if the permissible current density Jmax of the connection hole is the same, the permissible current value Imax in the connection hole becomes smaller when the cross-sectional area A of the connection hole becomes smaller. For example, in the case where the sidewall is formed, the allowable current value Imax becomes about 2/3 as compared with the case where the sidewall is not formed. Moreover, when the diameter of the connection hole is reduced, the coverage of the barrier metal is also deteriorated.

According to the present invention, it is possible to reduce the diameter of the connecting hole without reducing the diameter.
It is an object of the present invention to provide a multilayer wiring structure of a semiconductor device, which has excellent embedding characteristics when an aluminum alloy is embedded in a connection hole by a high-temperature aluminum alloy sputtering method and has excellent electromigration resistance, and a manufacturing method thereof.

[0018]

SUMMARY OF THE INVENTION The present invention is a multilayer wiring structure for a semiconductor device and a method for manufacturing the same, which has been made to achieve the above object. That is, in the multilayer wiring structure of the semiconductor device, the lower layer wiring is formed on the insulating layer provided on the upper layer of the substrate, and the first silicon nitride film is formed so as to cover the lower layer wiring. Then, a flattening buried portion is formed on the lower portion on the first silicon nitride film on both sides of the lower wiring. Further, a second silicon nitride film is formed on the first silicon nitride film and the flattening buried portion. A connection hole is formed in the first and second silicon nitride films on the lower layer wiring, a barrier metal layer is formed on the second silicon nitride film together with the inner wall of the connection hole, and further on the barrier metal layer. The upper wiring forming layer is formed so as to fill the connection hole.

A silicon oxide film may be formed between the lower wiring and the first silicon nitride film.

As a manufacturing method thereof, in the first step, a lower layer wiring is formed on an insulating layer provided on the upper layer of the substrate. Next, in a second step, a first silicon nitride film is formed so as to cover the lower layer wiring, and then a flattening layer is formed so as to fill the lower portions on the first silicon nitride film on both sides of the lower layer wiring. The planarization layer is removed in a state where the upper portion of the first silicon nitride film is exposed, and a planarization buried portion made of the planarization layer is formed on the lower portion. Then, in a third step, a second silicon nitride film is formed on the first silicon nitride film and the flattening layer. Then, in the fourth step, the first and second wirings on the lower layer wiring are
A connection hole is formed in the silicon nitride film. Then, in a fifth step, after forming a barrier metal layer on the second silicon nitride film in a state of being connected to the lower layer wiring through the connection hole, the connection hole is filled and an upper wiring forming layer is formed on the barrier metal layer. To form.

Alternatively, after the first step is performed, a silicon oxide film is formed in a state of covering the lower layer wiring, and thereafter, the steps after the step of forming the first silicon nitride film in the second step are performed.

The upper wiring forming layer is formed of an aluminum-based metal by a high temperature sputtering method.

[0023]

In the multilayer wiring structure of the semiconductor device described above, since the sidewall of the connection hole is formed of the first and second silicon nitride films, the barrier metal layer made of the titanium film does not react with the sidewall of the connection hole. Therefore, since the barrier metal layer is not oxidized, the inside of the connection hole is filled with the upper wiring forming layer made of an aluminum alloy formed by the high temperature sputtering method. Further, since the silicon oxide film is formed between the lower layer wiring and the first silicon nitride film, the stress generated in the first silicon nitride film by the silicon oxide film is relaxed.

In the above manufacturing method, after forming the first and second silicon nitride films on the lower layer wiring, the connection holes are formed on the lower layer wiring, so that the sidewalls of the connection holes are formed on the first and second silicon nitride films. become. Therefore, even if the barrier metal layer formed on the inner wall of the connection hole is formed of, for example, a titanium film thereafter, the barrier metal layer does not react with the side wall of the connection hole and is not oxidized. For this reason, since the sidewall of the connection hole is formed of a titanium film having excellent wettability with respect to the high temperature aluminum alloy, when the upper layer wiring forming layer made of the aluminum alloy is formed by the high temperature sputtering method, the upper layer wiring forming layer is formed. Smoothly enter the inside of the connection hole through the barrier metal layer.

[0025]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the present invention will be described with reference to the schematic sectional view of FIG. As shown in the figure, lower layer wirings 13 and 14 are formed on the insulating layer 12 provided on the upper layer of the substrate 11.

On the insulating layer 12, each lower layer wiring 13,
A first silicon nitride film 15 is formed so as to cover 14. The first silicon nitride film 15 is made of, for example, plasma CVD silicon nitride having a compressive stress of about 0.01 Pa to 0.3 Pa. Furthermore, the lower parts 16, 1 on the first silicon nitride film 15 on both sides of each lower layer wiring 13, 14 are formed.
Flattening buried portions 19, 20, and 21 are formed on the surfaces 7 and 18 so that the upper surfaces thereof are substantially flush with the upper surface of the high portion of the first silicon nitride film 15. The flattening embedded portions 19, 20, 21 are made of SOG (Spin on glass). Then, the first silicon nitride film 15
A second silicon nitride film 22 is formed on the top and the flattening buried portions 19, 20, 21. The second silicon nitride film 22 has, for example, a compressive stress of 0.01 Pa to
It is made of plasma CVD silicon nitride of about 0.3 Pa.

Connection holes 23 and 24 are formed in the first and second silicon nitride films 15 and 22 on the lower layer wirings 13 and 14, respectively.

A barrier metal layer 25 is formed on the second silicon nitride film 22 together with the inner walls of the connection holes 23 and 24. The barrier metal layer 25 is made of, for example, a titanium film. An upper wiring formation layer 26 made of an aluminum alloy film formed by a high temperature sputtering method is formed on the barrier metal layer 25 in a state where the connection holes 23 and 24 are filled. Therefore, the barrier metal layer 25 and the upper wiring forming layer 26 form an upper wiring 27.

The multilayer wiring structure of the semiconductor device is constructed as described above.

In the multilayer wiring structure of the above semiconductor device, the sidewalls of the connection holes 23 and 24 have the first and second silicon nitride films 15 and 24, respectively.
The barrier metal layer 25 made of a titanium film does not react with the sidewalls of the connection holes 23 and 24 because it is formed of 22. Therefore, since the barrier metal layer 25 is not oxidized, the insides of the connection holes 23 and 24 are formed in the upper wiring formation layer 2 made of an aluminum alloy formed by the high temperature sputtering method.
It becomes a state filled with 6.

Next, a method of manufacturing the multilayer wiring structure of the semiconductor device will be described with reference to the manufacturing process chart of FIG. In the figure, the same components as those described in FIG. 1 are designated by the same reference numerals.

As shown in FIG. 2A, in the first step, the lower wirings 13 and 14 are formed on the insulating layer 12 provided on the upper layer of the substrate 11 by a normal wiring forming technique.

Then, the second step shown in FIG. 2B is performed. In this step, the first silicon nitride film 15 is formed by plasma CVD so as to cover the lower wirings 13 and 14.
To form a film. The first silicon nitride film 15 is formed under the film forming conditions in which the compressive stress is about 0.01 Pa to 0.3 Pa. The film forming conditions are, for example, a mixed gas of monosilane (SiH ₄ ) having a flow rate of 185 sccm and ammonia (NH ₃ ) having a flow rate of 60 sccm as a reaction gas, a pressure of a film forming atmosphere of 733 Pa, and a film forming atmosphere of Set the temperature to 360 ° C.

Next, by SOG (Spin on glass) by a coating technique (for example, a spin coating technique), the lower portions 16, 17, 18 on the first silicon nitride film 15 on both sides of the lower wirings 13, 14 are buried. The flattening layer 31 is formed. Then, reactive ion etching is performed to remove a portion indicated by a chain double-dashed line of the planarization layer 31 in a state where the upper portion of the first silicon nitride film 15 is exposed, and the planarization layer is formed on the lower portions 16, 17, and 18. The flattening embedded portions 19, 20, and 21 made of (31) are formed.

Subsequently, a third step shown in FIG. 2C is performed. In this step, plasma planarization is performed on the first silicon nitride film 15 and the planarization embedded portion 19,
A second silicon nitride film 22 is formed on the layers 20 and 21.
The second silicon nitride film 22 has a compressive stress of 0.01 Pa.
The film is formed under the film forming condition of about 0.3 Pa.

After that, a fourth step shown in FIG. 2D is performed. In this step, the first and second wirings on the lower wirings 13 and 14 are formed by photolithography and etching.
Connection holes 23 and 24 are formed in the second silicon nitride films 15 and 22, respectively. The diameter of these connection holes 23, 24 is, for example, 0.
It is formed to 8 μm.

Then, the fifth step shown in FIG. 2 (5) is performed. In this step, the connection hole 2 is formed by the sputtering method.
A barrier metal layer 25 is formed on the second silicon nitride film 22 in a state of being connected to the lower wirings 13 and 14 via 3, 24. The barrier metal layer 25 is made of, for example, a titanium film. As the film forming conditions for the barrier metal layer 25, for example, the pressure of the film forming atmosphere is set to 0.26 Pa, the output is set to 7.5 kW, and the film forming atmosphere is set to 100% argon (Ar).

Next, an upper wiring forming layer 26 made of an aluminum-based metal is formed on the barrier metal layer 25 by the high temperature sputtering method. In this sputtering method, for example, a target of aluminum-1% silicon alloy is used. As film forming conditions, for example, the pressure of the film forming atmosphere is set to 0.26 Pa, the output is set to 7.5 kW, and the film forming atmosphere is set to 100% argon (Ar). The upper wiring forming layer 26 enters the inside of the connection holes 23, 24 via the barrier metal layer 25 and fills the connection holes 23, 24.

After that, the upper wiring forming layer 26 and the barrier metal layer 2 are formed by photolithography and etching.
5 and the lower layer wirings 13 and 14 through the connection holes 23 and 24.
An upper layer wiring 27 connected to is formed.

As described above, the multilayer wiring structure of the semiconductor device is formed.

In the above manufacturing method, the sidewalls of the connection holes 23, 24 become the first and second silicon nitride films 15, 22. Therefore, even if the barrier metal layer 25 formed on the inner walls of the connection holes 23 and 24 is subsequently formed of, for example, a titanium film, the barrier metal layer 25 does not react with the side walls of the connection holes 23 and 24 and is not oxidized. For this reason, since the sidewalls of the connection holes 23 and 24 are formed of a titanium film having excellent wettability with respect to the high temperature aluminum alloy, when the upper wiring forming layer 26 made of the aluminum alloy is formed by the high temperature sputtering method, The upper wiring forming layer 26 smoothly enters the inside of the connection holes 23, 24 via the barrier metal layer 25.

Since the silicon oxide film 41 is formed between the lower layer wirings 13 and 14 and the first silicon nitride film 15, the stress generated in the first silicon nitride film 15 by the silicon oxide film 41 is relaxed.

Next, the second embodiment will be described with reference to the schematic sectional view of FIG. In the figure, the same components as those described in the first embodiment are designated by the same reference numerals, and detailed description of the respective components described with reference to FIG. 1 will be omitted.

As shown in the figure, a silicon oxide film 41 is formed between the lower layer wirings 13 and 14 formed on the insulating layer 12 provided on the upper layer of the substrate 11 and the first silicon nitride film 15. Since the other components are the same as those described in FIG. 1, the description thereof will be omitted here. The silicon oxide film 41 is, for example, tetraethoxysilane (TEOS) C.
It is made of silicon oxide formed by the VD method.

In the above configuration, the lower layer wirings 13 and 14 and the first wiring
By forming the silicon oxide film 41 between the silicon oxide film 41 and the silicon nitride film 15, the stress generated in the first silicon nitride film 15 by the silicon oxide film 41 is relaxed, and the lower wirings 13 and 14 are formed.
Reduce the impact on.

Next, the manufacturing method of the second embodiment will be described with reference to FIG.
Will be described with reference to manufacturing process diagrams. In the figure, the same components as those described in FIG. 2 are designated by the same reference numerals. Further, the description of the steps which are the same as those described with reference to FIG. 2 is omitted.

First, the first step described in FIG. 2A is performed. Then, as shown in (1) of FIG. 4, the substrate 1 is formed by a tetraethoxysilane (TEOS) CVD method.
A silicon oxide film 41 is formed in a state of covering the lower layer wirings 13 and 14 on the insulating layer 12 provided on the first layer. Then, similar to the second step described in FIG. 2B, steps after the step of forming the first silicon nitride film 15 on the surface of the silicon oxide film 41 are performed.

At the time when the third step shown in FIG. 2C is completed, as shown in FIG. 4B, the silicon oxide film 41 and the first and second silicon oxide films 41 and 14 are formed on the lower wirings 13 and 14. The second silicon nitride films 15 and 22 are formed. Therefore, as shown in (3) of FIG. 4, when the connection holes 23 and 24 are formed on the lower layer wirings 13 and 14, the lower layer wirings 13 and 14 are formed by photolithography and etching.
The upper silicon oxide film 41 and the first and second silicon nitride films 1
Connection holes 23 and 24 are formed in the holes 5 and 22, respectively.

[0049]

As described above, according to the multilayer wiring structure of the semiconductor device of the present invention, the sidewalls of the connection holes are the first and second side walls.
Since it is formed of only the silicon nitride film, it is not necessary to form a sidewall on the sidewall of the connection hole as in the conventional case. For this reason, the cross-sectional area of the connection hole is about 1.5 times larger than the conventional one. Therefore, the allowable current value Imax also increases by about 1.5 times. Further, since the diameter of the connection hole is increased, the coverage of the barrier metal can be improved. Therefore, the wiring reliability can be improved. And the manufacturing process is simplified. Further, the barrier metal layer made of the titanium film does not react with the side wall of the connection hole. Therefore, since the barrier metal layer is not oxidized, the inside of the connection hole is filled with the upper wiring forming layer made of an aluminum alloy formed by the high temperature sputtering method.

Further, since the silicon oxide film is formed between the lower wiring and the first silicon nitride film, the silicon oxide film can relieve the compressive stress generated in the first silicon nitride film. Therefore, the reliability of the lower layer wiring can be improved.

According to the manufacturing method of the present invention, since the sidewalls of the connection holes are formed of the first and second silicon nitride films, the barrier metal layer can be formed of, for example, a titanium film without being oxidized. For this reason, the side wall of the connection hole becomes a barrier metal layer of a titanium film having excellent wettability with respect to the high temperature aluminum alloy. Therefore, when the upper layer wiring forming layer made of the aluminum alloy is formed by the high temperature sputtering method, the upper layer wiring forming layer is formed. Smoothly enters the inside of the connection hole through the barrier metal layer,
The connection hole can be embedded.

[Brief description of drawings]

FIG. 1 is a schematic configuration sectional view of a first embodiment.

FIG. 2 is a manufacturing process diagram of the first embodiment.

FIG. 3 is a schematic configuration sectional view of a second embodiment.

FIG. 4 is a manufacturing process diagram of the second embodiment.

FIG. 5 is a manufacturing process diagram for forming a conventional wiring structure.

[Explanation of symbols]

 11 Substrate 12 Insulating Layer 13 Lower Layer Wiring 14 Lower Layer Wiring 15 First Silicon Nitride Film 16 Lower Part 17 Lower Part 18 Lower Part 19 Flattening Embedded Portion 20 Flattening Embedded Portion 21 Flattening Embedded Portion 22 Second Silicon Nitride Film 23 Connection Hole 24 Connection Hole 25 Barrier Metal Layer 26 Upper Wiring Forming Layer 27 Upper Wiring 31 Flattening Layer 41 Silicon Oxide Film

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical indication H01L 21/768

Claims (5)

[Claims] 1. A lower layer wiring formed on an insulating layer provided on an upper layer of a substrate, a first silicon nitride film formed so as to cover the lower layer wiring, and the first silicon nitride film on both sides of the lower layer wiring. , A second silicon nitride film formed on the first silicon nitride film and the flattening buried part, and the first and second nitrides on the lower wiring. A semiconductor device, comprising: a connection hole formed in a silicon film; a barrier metal layer formed on the second silicon nitride film together with an inner wall of the connection hole; and an upper layer wiring formed on the barrier metal layer. Multi-layer wiring structure. 2. The method for manufacturing a multilayer wiring structure of a semiconductor device according to claim 1, wherein the lower layer wiring is formed on an insulating layer provided on the upper layer of the substrate.
And a step of forming a first silicon nitride film in a state of covering the lower layer wiring, and then forming a planarization layer in a state of filling a lower portion on the first silicon nitride film on both sides of the lower layer wiring, A second step of removing the flattening layer in a state where the upper portion of the first silicon nitride film is exposed, and forming a flattening buried portion made of the flattening layer on the lower portion; A third step of forming a second silicon nitride film on the film and the flattening layer, and a fourth step of forming a contact hole in the first and second silicon nitride films on the lower wiring. After forming a barrier metal layer on the second silicon nitride film in a state of being connected to the lower wiring via the connection hole,
Fifth, forming an upper wiring forming layer on the barrier metal layer
The method of manufacturing a multilayer wiring structure of a semiconductor device, comprising: 3. The multilayer wiring structure for a semiconductor device according to claim 1, wherein a silicon oxide film is formed between the lower layer wiring and the first silicon nitride film. 4. The method for manufacturing a multilayer wiring structure of a semiconductor device according to claim 2, wherein after the first step is performed, a silicon oxide film is formed to cover the lower layer wiring, and then the second layer is formed. The method for manufacturing a multilayer wiring structure of a semiconductor device, which is characterized by performing the steps subsequent to the step of forming the first silicon nitride film in the above step. 5. The method of manufacturing a multilayer wiring structure of a semiconductor device according to claim 2, wherein the upper wiring forming layer is formed of an aluminum-based metal by a high temperature sputtering method. Method for manufacturing multi-layer wiring structure of device.