JP2001085517A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a wiring structure of high reliability, which is superior in adhesion by restraining exfoliation of an SiOF-(silicon oxide) film, in a wiring structure using an SiOF film having low permitivity. SOLUTION: This semiconductor device is provided with a substrate 11, a wiring 13 which is formed on the substrate 11 and has a P-SiN film 14 formed on the upper surface, a silicon oxide film a 15 which is formed on the side part of the wiring 13 (includes the P-SiN film 14) and contains fluorine, a silicon oxide film 16, which is formed continuously on the P-SiN film 14 and the silicon oxide film 15 containing fluorine.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device using a silicon oxide film containing fluorine between wirings of the same wiring layer and a method of manufacturing the same.

[0002]

2. Description of the Related Art As wiring pitches have been scaled down, the problem of signal delay due to an increase in wiring resistance and an increase in wiring capacitance has attracted attention. Therefore, a low dielectric constant film or a low resistance wiring material is being studied. For example, a silicon oxide film containing fluorine (hereinafter referred to as SiOF) film is widely evaluated in terms of compatibility with the conventional technology because a low dielectric constant can be achieved by adding fluorine to the conventional silicon oxide film. ing. In particular, an SiOF film formed using high-density plasma (hereinafter referred to as HDP-SiOF) is expected to be a film having excellent embedding performance and low hygroscopicity.

Next, a method of forming a multilayer wiring structure using an HDP-SiOF film will be described below.

As shown in FIG. 6A, after an insulating film 101 is formed on a silicon substrate 100, the insulating film 10 is formed.
The wiring 102 is formed on the substrate 1. Then, HDP-SiO
The F film 103 is formed to a thickness of, for example, 800 nm. The film thickness of the HDP-SiOF film 103 on the wiring 102 depends on the wiring width, and is formed to be thin on a fine wiring and thick on a wide wiring.

Next, as shown in FIG. 6 (2), a silicon oxide film (hereinafter referred to as a P-TEOS film) is formed on the HDP-SiOF film 103 by plasma CVD using tetraethoxysilane (TEOS) as a source gas. ) 104 is formed to a thickness of, for example, 1.60 μm.

In the above state, since a step corresponding to the wiring pattern exists on the surface of the P-TEOS film 104, the P-TOS film is formed by chemical mechanical polishing as shown in FIG.
The surface of the EOS film 104 is flattened. At this time, it is necessary to set the amount of polishing so that the SiOF film 103 on the wide wiring is not exposed. This is because when the SiOF film 103 is exposed, a metal film formed in a subsequent step is easily peeled.

[0007] Next, as shown in FIG. 7, a via hole 105 is opened at a predetermined position of the P-TEOS film 104 and the SiOF film 103, and an adhesion layer 106 is formed on the inner surface of the via hole 105 with a titanium nitride film. After the tungsten film is buried in 105, the tungsten film and the adhesion layer 106 are etched back, and a tungsten plug 107 made of a tungsten film is formed only in the via hole 105 via the adhesion layer 106 of the titanium nitride film.

By repeating the above steps, a multilayer wiring structure is formed as shown in FIG. In FIG. 8, a wiring 102 is formed on a substrate 100 so as to cover the wiring 102.
The wiring structure including the iOF film 103 and the P-TEOS film 104 as one layer is shown as a four-layer wiring structure in which four layers are formed. Note that an HDP-SiO ₂ film 108 and a P-Si
An N film 109 is formed.

[0009]

However, when heat treatment is performed on the wiring structure described in the above-mentioned conventional technique,
The SiOF film is peeled off depending on the temperature and time. SiO
The area where the F film is peeled off is a region where a thick SiOF film is deposited on a wide wiring, a P-TEOS film is formed thin by a planarization process, and a SiOF film is further deposited thereon. It is.

That is, as shown in FIG. 9, the interface P where the peeling occurs is the SiOF film 103 on the upper surface of the wiring 102.
The mechanism of this peeling is as follows.
Fluorine that does not form a fluorine bond (hereinafter referred to as free fluorine) diffuses into the film by heat treatment and segregates on the upper surface of the wiring 102. It is presumed that the segregated fluorine causes the adhesion between the wiring 102 and the SiOF film 103 to be reduced, and causes separation due to residual stress in the interlayer insulating film.

Further, as disclosed in Japanese Patent Application No. 10-275859, it is difficult to suppress the peeling phenomenon depending on the heat treatment time in the method of forming an SiO ₂ film on a wiring. Further, an attempt was made to form a plasma-silicon nitride film on the wiring to suppress the diffusion of free fluorine from the SiOF film, but film peeling occurred on the upper surface of the plasma-silicon nitride film. In the prior art, forming a thick P-TEOS film on a SiOF film prevents film peeling, but the increased thickness increases the aspect ratio of the via hole. Therefore, it is difficult to form a via hole stably.

[0012]

SUMMARY OF THE INVENTION The present invention is directed to a semiconductor device and a method of manufacturing the same to solve the above-mentioned problems.

In the semiconductor device, a substrate, a wiring formed on the substrate, a silicon oxide film containing fluorine formed on both sides of the wiring, and a wiring and a silicon oxide film containing fluorine are formed continuously on the wiring. And a silicon oxide film.

In the above-described semiconductor device, the silicon oxide film containing fluorine is formed on both sides of the wiring, and the silicon oxide film is continuously formed on the wiring and the silicon oxide film containing fluorine. It is possible to eliminate film peeling on the wiring due to diffusion and segregation of free fluorine in the silicon oxide film in the thermal process.

A method of manufacturing a semiconductor device includes a step of forming a silicon oxide film containing fluorine on both sides of a wiring formed on a substrate, and a step of forming a silicon oxide film on the wiring and on the silicon oxide film containing fluorine. Continuous forming step.

In the method of manufacturing a semiconductor device, a silicon oxide film containing fluorine is formed on both sides of the wiring so as to be buried, and the silicon oxide film is continuously formed on the wiring and the silicon oxide film containing fluorine. In addition, the peeling of the film on the wiring due to the diffusion and segregation of the free fluorine in the fluorine-containing silicon oxide film in the thermal process does not occur.

[0017]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment according to the semiconductor device of the present invention will be described with reference to a schematic sectional view of FIG.

As shown in FIG. 1, the surface of a semiconductor substrate 11 is covered with an insulating film 12. This insulating film 12
For example, it is formed to a thickness of 500 nm. The wiring 13 is formed on the insulating film 12. This wiring 13
Is, for example, a titanium film having a thickness of 10 nm and a thickness of 500
An aluminum film having a thickness of 5 nm, a titanium film having a thickness of 5 nm, and a titanium nitride film having a thickness of 80 nm are sequentially laminated. Further, a plasma-silicon nitride (hereinafter, referred to as P-SiN) film 14 is formed on the wiring 13 by, for example, 200 nm.
m.

Further, the wiring 13 and the P-Si
On the insulating film 12 on both sides of the N film 14, a silicon oxide film containing fluorine (hereinafter, referred to as SiOF film) 15 is formed. The surface of this SiOF film 15 is
The surface is planarized so as to be flush with the surface of the SiN film 14.

Further, on the SiOF film 15, the P
A silicon oxide film 16 covering the SiN film 14 is formed to a thickness of 800 nm by a plasma CVD method using, for example, tetraethoxysilane (TEOS) as a source gas. In the silicon oxide film 16 and the P-SiN film 14, a via hole 17 reaching a predetermined wiring 13 is opened. Further, an adhesion layer 21 is provided inside the via hole 17.
The plug 22 is formed through the plug. This plug 22
Is formed of tungsten, and the adhesion layer 21 is formed of, for example, a titanium nitride film having a thickness of 30 nm.

In the above semiconductor device, S
Since the iOF film 15 is formed and the silicon oxide film 16 is continuously formed on the wiring 13 and the SiOF film 15, free fluorine in the SiOF film 15 is diffused and segregated in the thermal process. Film peeling on the wiring 13 can be eliminated.

A first embodiment of the method for manufacturing a semiconductor device according to the present invention will be described with reference to a manufacturing process diagram of FIG.

As shown in FIG. 2A, the semiconductor substrate 1
The insulating film 12 covering the surface of the first substrate is formed to a thickness of, for example, 500 nm. The wiring layer 31 is formed on the insulating film 12.
To form The wiring layer 31 is made of, for example,
0 nm, aluminum film 500 nm, titanium film 5 n
m, a titanium nitride film is formed by sequentially laminating to a thickness of 80 nm. Next, a plasma-silicon nitride (hereinafter, referred to as P-SiN) film 14 is formed on the wiring layer 31 by, for example, 200 n.
m. Next, after applying a resist on the P-SiN film 14 to form a resist film (not shown),
The resist film is patterned into a wiring pattern by a lithography technique, and the P-SiN film 14 and the wiring layer 31 are etched by an etching technique (for example, reactive ion etching) using the resist film as an etching mask to form a P-SiN. The wiring 13 on which the film 14 is mounted is formed.

Then, as shown in FIG. 2B, a fluorine-containing silicon oxide film (hereinafter, referred to as an SiOF film) covering the wiring 13 on which the P-SiN film 14 is mounted, for example, by a high-density plasma CVD method. 15) for example 1000n
m to form a film. As an example of the film forming conditions, as source gas, silane tetrafluoride (SiF ₄ ) (for example, supply flow rate is 34 sccm), monosilane (SiH ₄ ) (for example, supply flow rate is 30 sccm), and oxygen (O ₂ ) [ For example, supply flow rate is 110 sccm] and argon (Ar) [for example, supply flow rate is 65 sccm] is used. In addition, the pressure of the film formation atmosphere is set to 0.67 Pa, and the ICP (Inductively Coup
led Plasma) power was set to 4.53 kW, and the bias power was set to 2.20 kW.

The thickness of the SiOF film 15 depends on the width of the wiring 13 and is formed thin on the fine wiring 13 (13s) and thick on the wide wiring 13 (13w). . For example, a film having a thickness of 300 nm is formed on a 0.36 μm wiring, and a film having a thickness of 1000 nm is formed on a 110 μm width pad.
The film was formed to a thickness of nm.

Next, as shown in FIG. 2C, chemical mechanical polishing (hereinafter referred to as CMP) is a chemical mechanical polishing (CMP).
hanical Polishing), the P-
The SiOF film 15 is polished and flattened until the surface of the SiN film 14 is exposed. At this time, wiring 1 depends on the wiring width.
3, the time required for completely polishing the SiOF film 15 varies depending on the wiring width and the wiring density. However, the P-SiN film 14 and S
By setting the polishing conditions so that the polishing rate with the iOF film 15 is higher, that is, the polishing rate of the SiOF film 15 is higher than that of the P-SiN film 14,
On the wiring 13 on which the F film 15 is polished first, when the P-SiN film 14 is exposed, the polishing speed becomes slow, and the wiring 1
The difference in film thickness of the P-SiN film 14 on No. 3 does not become large.

Next, as shown in FIG.
A silicon oxide film 16 covering the P-SiN film 14 is formed on the iOF film 15 to a thickness of, for example, 800 nm. If a step occurs at the stage when the silicon oxide film 16 is formed, planarization may be performed again by CMP.

Next, as shown in FIG. 3, after forming a resist film (not shown) on the silicon oxide film 16 by a normal resist coating technique, a via hole is formed in the resist film by a normal lithography technique. An opening for opening the hole is formed. Using the resist film as an etching mask, a via hole 17 reaching the predetermined wiring 13 is opened in the silicon oxide film 16 and the P-SiN film 14 by a normal etching technique. Thereafter, the adhesion layer 21 is formed on the inner surface of the via hole 17 by sputtering. The adhesion layer 21 is formed of, for example, a titanium nitride film having a thickness of 30 nm. Note that the adhesion layer 21 is also formed on the silicon oxide film 16. Further, the tungsten film 23 is, for example, 50
It is formed to a thickness of 0 nm. The tungsten film 23 is also formed on the silicon oxide film 16 via the adhesion layer 21. Next, the tungsten film 23 and the adhesion layer 21 are etched back to form a plug 22 made of the tungsten film 23 only through the adhesion layer 21 inside the via hole 17.

By repeating the steps described with reference to FIGS. 2 and 3, a multilayer wiring structure is formed as shown in FIG. In FIG. 4, the wiring 13 is provided on the substrate 11.
The P-SiN film 14 formed on the wiring 13 and the wiring 1
3 and a silicon oxide film 16 continuously formed on the P-SiN film 14 and the SiOF film 15 as a single layer, and the SiOF film 15 formed on both sides of the P-SiN film 14 is formed as one layer. A four-layer wiring structure formed in four layers is shown. Note that an HDP-SiO ₂ film 41 as a passivation film, for example, 800 n
m and a P-SiN film 42 of, for example,
It was formed to a thickness of 50 nm.

In the above manufacturing method, since the SiOF film 15 which causes the film peeling is removed from the wiring 13 by the CMP, free fluorine is removed from the wiring 13 or the P-SiN film 14 even if a heating step is performed. No segregation upwards. Therefore, the adhesion of the silicon oxide film 16 serving as the interlayer insulating film is secured, and the peeling phenomenon does not occur.
Reliability can be improved. Further, since the SiOF film 15 does not exist on the wiring 13, the thickness of the silicon oxide film 16 can be set arbitrarily, and an increase in the aspect ratio of the via hole 17 can be suppressed.

In the first embodiment, the SiOF
When the film 15 is polished to expose the P-SiN film 14 on the wiring 13, depending on the CMP conditions, the polishing time of the SiOF film 15 (to completely remove the SiOF film 15) depends on the width and wiring density of each wiring. P-SiN film 14 on each wiring 13
The time until the light is completely exposed). Alternatively, when the difference in polishing rate between the P-SiN film 14 and the SiOF film 15 is small, the insulating film (SiOF
The thickness of the film 15 and the P-SiN film 14) may increase. Therefore, the improvement will be described as a second embodiment with reference to the manufacturing process diagram of FIG.

As shown in FIG. 5A, the SiOF film 1
Until the film 5 is formed, the process is the same as in the first embodiment.

First, as shown in FIG. 5B, a resist film 51 is formed on the SiOF film 15 by a normal resist coating technique. Next, an opening 52 is formed in the resist film 51 on the wide wiring 13 (13w) by a normal sography technique.

Next, as shown in FIG. 5 (3), using the resist film 51 (see FIG. 5 (2)) as an etching mask, by a normal etching technique (for example, reactive ion etching). The wide wiring 13 (13
w) The upper SiOF film 15 is removed by etching.
After that, the resist film 51 is removed by, for example, an ashing technique.

Then, in the same manner as described in the first embodiment, the SiOF film 15 is polished by CMP to expose the entire surface of the P-SiN film 14 on the wiring 13 and to planarize it. And the subsequent steps may be performed sequentially.

According to the second embodiment, the thickness of the SiOF film 15 on the wide wiring (strictly speaking, the volume of the SiOF film to be polished) can be suppressed, and the subsequent Polishing time depending on wiring width and wiring density (wiring 1
3), the difference required for completely polishing the SiOF film 15 on the wiring 3 can be reduced.
3 can reduce a difference in thickness of the insulating film.

In the first and second embodiments, the P-SiN film 14 is left on the wiring 13.
After the CMP of the film 15 is performed, the P-SiN film 14 may be removed by etching. Thus, the P-SiN film 1
By removing 4, the effect of reducing the wiring capacitance can be expected.

Note that Japanese Patent Application No. Hei 10-326829 discloses this. Although it is disclosed that the SiOF film is removed at the time of planarization by CMP, it is disclosed that the CMP is performed so that the SiOF film remains on the wiring. Thus, if the SiOF film remains on the wiring, the problem to be solved by the present invention cannot be completely solved.

[0039]

As described above, according to the semiconductor device of the present invention, the silicon oxide film containing fluorine is formed on both sides of the wiring, and the silicon oxide film is continuously formed on the wiring and the silicon oxide film containing fluorine. Since it is formed selectively, it is possible to eliminate the film peeling on the wiring due to the diffusion and segregation of free fluorine in the fluorine-containing silicon oxide film in the thermal process. Therefore, the reliability of the wiring structure can be improved. Further, since film peeling does not occur, it is not necessary to increase the thickness of the silicon oxide film on the silicon oxide film containing fluorine. Therefore, the thickness of the silicon oxide film on the wiring is not increased, and the via hole does not need to have a high aspect ratio, so that the contact reliability can be improved.

According to the method of manufacturing a semiconductor device of the present invention,
Since the silicon oxide film containing fluorine is formed to be embedded on both sides of the wiring and the silicon oxide film is continuously formed on the wiring and the silicon oxide film containing fluorine, free fluorine in the silicon oxide film containing fluorine is reduced. The film does not peel off on the wiring due to diffusion and segregation in the thermal process. Therefore, a highly reliable wiring structure can be formed. Further, since only the silicon oxide film is formed on the wiring, the via hole formed in the silicon insulating film does not require a high aspect ratio, and the reliability of the contact can be improved.

[Brief description of the drawings]

FIG. 1 is a schematic sectional view showing an embodiment of a semiconductor device according to the present invention.

FIG. 2 is a cross-sectional view illustrating a manufacturing process of the first embodiment of the method for manufacturing a semiconductor device according to the present invention.

FIG. 3 is a manufacturing process sectional view showing the first embodiment (continued) of the method for manufacturing a semiconductor device according to the present invention;

FIG. 4 is a schematic sectional view of a four-layer wiring structure showing a first embodiment according to a method of manufacturing a semiconductor device of the present invention.

FIG. 5 is a manufacturing process sectional view showing a second embodiment according to a method of manufacturing a semiconductor device of the present invention.

FIG. 6 is a cross-sectional view of a manufacturing process showing a method of manufacturing a wiring structure according to a conventional technique.

FIG. 7 is a manufacturing process sectional view showing a method (continued) of manufacturing a wiring structure in a conventional technique.

FIG. 8 is a schematic sectional view showing a four-layer wiring structure according to a conventional technique.

FIG. 9 is a schematic cross-sectional view showing a problem of a wiring structure in a conventional technique.

[Explanation of symbols]

11: substrate, 13: wiring, 15: silicon oxide film containing fluorine (SiOF film), 16: silicon oxide film

Claims (6)

[Claims] 1. A substrate, a wiring formed on the substrate, a silicon oxide film containing fluorine formed on both sides of the wiring, and a silicon oxide film continuously formed on the wiring and the silicon oxide film containing fluorine. A semiconductor device comprising a silicon oxide film. 2. An insulating film containing no fluorine is provided between the wiring and the silicon oxide film, and the silicon oxide film containing fluorine is also formed between the insulating films containing no fluorine. The semiconductor device according to claim 1, wherein: 3. The semiconductor device according to claim 2, wherein said insulating film containing no fluorine is made of a silicon nitride film. 4. A step of forming a silicon oxide film containing fluorine on both sides of a wiring formed on a substrate, and forming a silicon oxide film continuously on the wiring and on the silicon oxide film containing fluorine. And a method of manufacturing a semiconductor device. 5. An insulating film containing no fluorine is formed on the wiring before forming the silicon oxide film containing fluorine, and the silicon oxide film containing fluorine does not contain both sides of the wiring and the fluorine. 5. The method according to claim 4, wherein the semiconductor device is formed on both sides of the insulating film. 6. The method according to claim 5, wherein the insulating film containing no fluorine is formed of a silicon nitride film.