JP3309570B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device in which a surface of an interlayer insulating film is smoothed, for example, when a multilayer wiring is provided.

[0002]

2. Description of the Related Art With the increase in the density of semiconductor devices, the wiring technology has advanced in the direction of miniaturization and multilayering. But,
The step of the interlayer insulating film is large and steep due to the progress of miniaturization and multilayering of wiring. Therefore, the processing accuracy and reliability of the wiring formed on the interlayer insulating film are reduced. Therefore, with the miniaturization of patterns, smoothing with an interlayer insulating film having good filling characteristics and high quality is required.

At present, the smoothing of the interlayer insulating film when the aspect ratio between the wiring step and the space between the wirings is close to 1 is typically performed as follows. First, an insulating film is formed on a wiring by chemical vapor deposition (hereinafter, referred to as CVD) using plasma. Then, S
OG (Spin On Glass) or ozone (O ₃ ) -tetraethoxysilane (T
The space gap between wirings is buried by EOS) CVD or the like. Furthermore, an interlayer insulating film whose surface is smoothed by performing etch-back on this is formed.

However, in a device having a structure in which an anti-reflection film for a photoresist is left on a wiring, the anti-reflection film usually protrudes in an eaves shape from the wiring when the wiring is cut. Therefore, SOG and O ₃
-Insufficient embedding of an insulating film such as a TEOS-based CVD film is likely to occur, resulting in a so-called void or seam in a space between wirings. The generation of voids or seams in the spaces between the wirings causes contamination in a later step, for example, due to a residual chemical solution, or rupture in a heating step, and significantly lowers the reliability of the device.

Therefore, conventionally, for example, as shown in FIG. 6, a side wall of the wiring 31 having an antireflection film 32 formed on the upper surface is formed by attaching a side wall with an insulating material 33 of, for example, silicon oxide. Alternatively, a slope is provided on the side of the wiring 31 to improve the burying characteristic of the insulating film. In forming the sidewall, first, an insulating material 33 is deposited by CVD on the surface of the base 30 on which the lower wiring layer is formed, for example, in a state of covering the wiring 31 and the antireflection film 32. Thereafter, the insulating material 33 is subjected to reactive ion etching (hereinafter referred to as RI
E).

[0006]

However, in the above method, when the space between the wirings is very narrow, the quality of the insulating film deposited in the space between the wirings by CVD often becomes very deteriorated. . Alternatively, the thickness of the insulating film in the space between the wirings is often extremely thinner than that of the pattern portion having a large width.

For this reason, if the etch-back is performed as it is, excessive over-etching is applied to a portion where the film quality is deteriorated or a portion where the film thickness is small, and the base 30 is excessively etched as shown in FIG. As a result, the aspect ratio of the space between the wirings is increased, so that a filling defect occurs.
In addition, since damage is applied to the lower wiring layer, problems such as open / short defects between the wiring and the interlayer occur.

Further, when the etch-back is performed, the upper portion of the lower wiring layer is exposed due to a variation in film thickness in the CVD process or a variation in RIE. Then, the exposed portion is excessively damaged by RIE, deteriorating the resistance to electromigration and stress migration, and causing a problem that the reliability of the wiring is significantly reduced.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problem. In a case where a second pattern is formed on a first pattern so as to extend from the first pattern, an insulating film is provided between the patterns. It is an object of the present invention to provide a method of manufacturing a semiconductor device having excellent embedding characteristics.

[0010]

In order to solve the above-mentioned problems, the invention according to claim 1 firstly comprises a first substrate formed on a substrate surface.
An etching stop film is formed on the surface of the base in a state of covering the pattern and the second pattern formed on the upper surface of the first pattern with the eaves protruding from the first pattern. Next, a shaping film is formed on the surface of the etching stop film such that the surface of the shaping film on the side of the first pattern is located outside the surface of the etching stop layer on the side of the eaves. . Thereafter, anisotropic etching is performed to remove the shaping film in the other portions while leaving the shaping film below the etching stop film on the side of the second pattern. Then, an insulating film is formed on the substrate so as to have at least a surface higher than the upper surface of the second pattern, and a semiconductor device in which the surface of the insulating film is smoothed is manufactured.

According to a second aspect of the present invention, there is provided a method for performing the anisotropic etching according to the first aspect of the present invention in a state where the etching rate of the shaping film is higher than the etching rate of the etching stop film. . According to a third aspect of the present invention, by performing the anisotropic etching according to the first or second aspect of the invention, the shaping film is formed into a positive taper shape below the etching stop film on the side of the second pattern. It is a way to leave.

[0012]

According to the first aspect of the present invention, since the shaping film is formed on the etching stop film and then anisotropic etching is performed, the etching stop film serves as an etching buffer film. Further, in the anisotropic etching, since the shaping film is left below the etching stop film on the side of the second pattern, a step on the side of the first and second patterns due to the eaves of the second pattern is reduced. Will be resolved.

According to the second aspect of the present invention, since the anisotropic etching is performed in a state where the etching rate of the shaping film is higher than the etching rate of the etching stop film, the etching is performed on the etching stop film. Stops. According to the third aspect of the present invention, the shaping film is left in a positive taper shape below the etching stop film on the side of the second pattern, so that the insulating film is easily buried.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a method for manufacturing a semiconductor device according to the present invention (hereinafter referred to as the method of the present invention) will be described below with reference to the drawings. FIG. 1 is an explanatory view showing an example of the method of the present invention in the order of steps. FIG. 2 is an enlarged view of a main part.

As shown in FIG. 1A, a semiconductor device manufactured by this embodiment has a first pattern 11 formed on the surface of a base 10 and a first pattern 11 formed on the upper surface of the first pattern 11. Eaves 1 protruding from one pattern 11
2a having the second pattern 12a.

The first pattern 11 is made of, for example, a barrier metal and a main wiring layer, and the second pattern 12 is made of an antireflection film. Then, the first pattern 11 and the second pattern 12 are in a state where wiring is formed. In addition,
The main wiring layer is made of, for example, an Al-Si alloy, pureAl or Al-S
It is made of an Al alloy such as an i-Cu alloy. The barrier metals are Ti / TiON / Ti, Ti and Ti / TiN.
/ Ti and other materials. Further, the antireflection film is made of Ti
It is formed of a material such as ON, a-Si, SiO _x (x <2), and SiON.

In the method of the present invention, first, an etching stop film 13 is formed on the surface of the base 10 so as to cover the first pattern 11 and the second pattern 12. As the etching stop film 13, for example, a SiO ₂ film, a SiON film, or the like is used. As a forming method, for example, a plasma enhanced (hereinafter, referred to as PE) C having good coverage can be used.
VD method is mentioned.

Next, a shaping film 14 is formed on the surface of the etching stopper film 13. At this time, the first of the shaping film 14
The surface on the side of the pattern 11 is located outside the surface of the etching stop layer 13 on the side of the eaves 12 a of the second pattern 12. The shaping film 14 is to be left in the shape of a sidewall on the side of the first pattern 11 in an anisotropic etching process described later.
An iN film, a SiO ₂ film, or the like is used. Also, for example, P
It is formed by an E-CVD method.

Thereafter, anisotropic etching such as RIE is performed. Then, as shown in FIG. 1B, the shaping film 1 is formed below the etching stopper film 13 on the side of the second pattern 12.
The remaining part of the shaping film 14 is removed in a state where 4 is left.

In this case, the anisotropic etching is performed so that the etching rate of the shaping film 14 is higher than the etching rate of the etching stopper film 13. As an etching gas used when the shaping film 14 is formed of a SiN film, for example, an O ₂ / CHF ₃ gas is used. The etching gas used when the shaping film 14 is formed of, for example, an SiO ₂ film is C gas.
F ₄ -O ₂ system, CHF ₃ -CF ₄ -Ar system, C ₄ H ₈ -
CHF ₃ -Ar-based gas and CO-CHF ₃ -Ar-based gas are exemplified.

Then, the insulating film 15 is formed so as to cover the first pattern 11 and the second pattern 12 and to have a surface higher than the upper surface of the second pattern 12. The insulating film 15 is made of, for example, S
It is made of an iO ₂ film, and uses an ordinary SOG coating (+ etch back) process as shown in FIGS. 1C, 1D, and 1E, and an organic silicon gas such as an organic siloxane or an organic silane. It is formed by a CVD process or the like.
Thereby, a semiconductor device in which the surface of the insulating film 15 is smoothed is manufactured.

In the above embodiment, the surface of the shaping film 14 on the side of the first pattern 11 is located outside the surface of the etching stop layer 13 on the side of the eaves 12a of the second pattern 12. It is formed as follows. Therefore, the base 1
When anisotropic etching is performed on the entire surface of
4 is left in a sidewall shape on the side of the first pattern 11.

By leaving the shaping film 14 in a sidewall shape on the side of the first pattern 11, the first pattern 11 and the second pattern 11 generated by the eaves 12 a of the second pattern 12 are formed.
The step on the side of the pattern 12 is eliminated. And the first
The sides of the pattern 12 are shaped into a smooth state. Therefore, the insulating film 15 can be sufficiently buried in a narrow space between the wirings without generating a void or a seam.

The shaping film 14 is the etching stop film 1.
Since the film is formed on the three surfaces, the etching stop film 13 becomes a buffer film during anisotropic etching, and the surface of the base 10 is hardly damaged by the etching. Moreover, since the anisotropic etching is performed so that the etching rate of the shaping film 14 is higher than the etching rate of the etching stopper film 13, the etching stops on the etching stopper film 13, and the base 10 in the space between the wirings becomes excessive. It will not be etched.

For this reason, when the lower wiring layer is formed on the base 10, the open / short defect between the wiring and the interlayer of the lower wiring layer is reduced. Further, since the lower wiring layer is not damaged by the anisotropic etching, deterioration of electromigration and stress migration resistance does not occur. Therefore, according to this embodiment, it is possible to manufacture a semiconductor device with high wiring reliability and to realize a multilayer wiring with high reliability.

Next, a specific example in which a semiconductor device is actually manufactured by the method of the above embodiment will be described. Prior to the implementation, Al-Si
A first pattern 11 is formed of a main wiring layer made of an alloy and a barrier metal made of Ti / TiON / Ti,
The second pattern 12 was formed of an N anti-reflection film.
At this time, in a pattern having a wiring height of about 0.8 μm and a minimum space between wirings of about 0.5 μm, the second pattern 12 has a thickness of about 10 to 100 nm and extends about 20 to 50 nm from the upper surface of the first pattern 11. Formed out.

First, for example, P using TEOS as a reaction gas
The PE-SiO ₂ film is formed in a thickness of 20 to 100 by the E-CVD method.
the first pattern 11 and the second pattern 12
The etching stop film 13 is formed on the surface of the
Was formed. Next, PE-Si by PE-CVD method.
The shaping film 14 was formed by depositing an N film of about 50 to 1000 nm.

Then, the selectivity of the PE-SiN film / PE-SiO ₂ film is 2 to 40 using the O ₂ / CHF ₃ gas.
Etch-back was performed under RIE conditions such that the degree of RIE was reduced.
At this time, the PE-SiN film is not left on the surface of the substrate 10 at the space between the wirings (overetch amount <
(30%). As a result, the shaping film 14 remained below the etching stop film 13 on the side of the second pattern 12, and the side of the first pattern 11 was shaped into a smooth state. Further, the etching was stopped by the etching stop film 13, and the base 10 was not excessively etched in the space between the wirings.

Subsequently, an insulating film 15 was formed by a normal SOG process. That is, as shown in FIG. 1C, the first pattern 11 and the second pattern 12 are formed on the surface of the base 10 by PE-CVD using TEOS as a reaction gas.
And the PE-SiO ₂ film 15a is
Deposited about 0 nm. Further, an SOG film 15b was applied on the PE-SiO ₂ film 15a to a thickness of about 400 to 800 nm, and the surface thereof was formed to be substantially flat. As a result, PE-
The SiO ₂ film 15a and the SOG film 15b were satisfactorily embedded in the space between the wirings.

Next, the selectivity of the SOG film / PE-SiO ₂ film is about 0.8 to 2.0 and the over-etching amount is 0 to 30 by a normal SOG etch-back process.
The etch back was performed under the condition of about%. by this,
As shown in FIG. 1D, the surface of the PE-SiO ₂ film 15a was smoothed.

Then, PE- using TEOS as a reaction gas
PE-Si is deposited on the surface in the state shown in FIG.
The O ₂ film 15c was deposited to a thickness of about 400~800nm. As a result, as shown in FIG. 1 (e), PE-SiO 2 film 15
a, a semiconductor device comprising an insulating film 15 composed of the SOG film 15b and the PE-SiO ₂ film 15c and having a smooth surface was obtained.

The above-mentioned insulating film 15 is formed by SOG
The process was performed by a CVD process using an organic silicon gas instead of the process under the conditions described later. First, similarly to the above-described embodiment, after the side of the first pattern 12 is shaped by anisotropic etching, PE-CV using TEOS as a reaction gas is used.
It was deposited about 50~400nm a PE-SiO ₂ film by a D method.

Then, an SiO ₂ film was deposited to a thickness of about 500 to 1000 nm by an O ₃ -TEOS-based CVD method carried out under normal pressure under conditions of good self-flow. As a result, FIG.
In the space between the narrow wiring as shown in PE-SiO ₂
The semiconductor device in which the insulating film 15 composed of the film 15d and the SiO ₂ film 15e was sufficiently buried, and the surface of which was further improved in smoothness was obtained.

As is apparent from these results, according to the above embodiment, the insulating film 1 is formed in the space between the first patterns 11 and the space between the second patterns 12, that is, in the space between the wirings.
5 can be manufactured satisfactorily, and the surface of the insulating film 15 can be smoothed.

In the anisotropic etching process of the above embodiment, as shown in FIG. 4, the shaping film 14 may be left in a positive taper shape below the etching stopper film 13 on the side of the second pattern 12. . In the case where the insulating film 15 is formed in a positive tapered shape, the insulating film 15 is easily buried in the space between the narrow wirings, and the burying characteristics are improved. As a result, the insulating film 1
The smoothing of the surface of No. 5 can be further improved.

FIG. 5 is a sectional view showing a state in which the shaping film 14 is formed in a positive taper shape to form a multilayer wiring. As illustrated, since the shaping film 14 on the side of the first pattern 11 of each wiring layer has a positive taper shape, the insulating film 15 of each wiring layer is satisfactorily embedded in the space between the wirings. As a result, the insulating film 15 having a smoother surface is formed between the wiring layers, so that a more reliable multilayer wiring can be realized. Therefore, by using this embodiment, a semiconductor device with high wiring reliability can be manufactured, and a multi-layer wiring with high reliability can be realized.

In the above embodiment, the etching stopper film 1 is used.
3 is an SiO ₂ film, and a shaping film 14 is SiN
Although an example using a film has been described, the present invention is not limited to this, and other insulating materials can be used in combination. For example, the etching stop film 13 may be formed of a SiON film, and the shaping film 14 may be formed of a SiN film or a SiO ₂ film. Even in this case, the etching conditions can be optimized by controlling the type of gas system used for anisotropic etching, the flow rate ratio, and the applied high-frequency power.

[0038]

As described above, according to the first aspect of the present invention, since the shaping film is left below the etching stop film on the side of the second pattern, the first pattern and the second pattern caused by the eaves are formed. Can be eliminated. Therefore, the insulating film can be sufficiently buried in the space between the wirings having a high aspect ratio and in the space between the wirings without generating voids or seams even in the space between the wiring steps / wirings and the wiring structure. Further, since the insulating film can be sufficiently buried in the space between the narrow wirings, the surface of the insulating film can be improved in smoothness.

Further, since the shaping film is formed on the etching stopper film, the substrate in the space between the wirings is hardly damaged by the etching, and the reliability of the wirings can be secured. In the invention according to claim 2, the anisotropic etching is performed in a state where an etching rate of the shaping film is higher than an etching rate of the etching stop film. For this reason, the etching can be stopped on the etching stop film, and the base can be prevented from being excessively etched.

[0040] Further, in the invention according to claim 3, the second aspect is provided.
Since the shaping film is left in a positive taper shape below the etching stop film on the side of the pattern, the filling characteristics of the insulating film to be buried in the space between the narrow wirings can be improved. Therefore, according to the method of the present invention, a semiconductor device with high wiring reliability can be manufactured, and a multi-layer wiring with high reliability can be realized. As a result, higher density,
A highly integrated and highly reliable semiconductor device can be obtained.

[Brief description of the drawings]

FIG. 1 is an explanatory view showing an example of the method of the present invention in the order of steps.

FIG. 2 is an enlarged view of a main part in a state where a shaping film is formed.

FIG. 3 is a cross-sectional view of another example of forming an insulating film.

FIG. 4 is a cross-sectional view when the shaping film has a tapered shape.

FIG. 5 is a sectional view showing a state in which a multilayer wiring is formed.

FIG. 6 is a cross-sectional view of a conventional example of forming a sidewall.

[Explanation of symbols]

 Reference Signs List 10 base 11 first pattern 12 second pattern 13 etching stop film 14 shaping film 15 insulating film

Claims (3)

(57) [Claims] 1. A first pattern formed on a surface of a substrate,
A method of manufacturing a semiconductor device having an eaves portion protruding from the first pattern and forming an insulating film so as to cover the second pattern formed on the upper surface of the first pattern, and having a smoothed surface. A first step of forming an etching stop film on the surface of the base while covering the first pattern and the second pattern; and forming a shaping film on the surface of the etching stop film; A second step of forming a film in a state in which the surface on the side of the first pattern is located outside the surface of the etching stop layer on the side of the eaves portion, and thereafter, performing anisotropic etching, A third step of removing the shaping film in other portions while leaving the shaping film below the etching stop film on the side of the second pattern; and in a state having at least a surface higher than the upper surface of the second pattern. Absolute And a fourth step of forming an edge film on the substrate. 2. The method for manufacturing a semiconductor device according to claim 1, wherein the anisotropic etching is performed in a state where an etching rate of the shaping film is higher than an etching rate of the etching stop film. Semiconductor device manufacturing method. 3. The method of manufacturing a semiconductor device according to claim 1, wherein the shaping film is formed below the etching stop film on the side of the second pattern by performing the anisotropic etching. A method for manufacturing a semiconductor device, wherein the semiconductor device is left in a tapered shape.