JPS57202776A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS57202776A
JPS57202776A JP56087638A JP8763881A JPS57202776A JP S57202776 A JPS57202776 A JP S57202776A JP 56087638 A JP56087638 A JP 56087638A JP 8763881 A JP8763881 A JP 8763881A JP S57202776 A JPS57202776 A JP S57202776A
Authority
JP
Japan
Prior art keywords
wiring
film
wiring layer
interlayer insulating
intersecting
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56087638A
Other languages
Japanese (ja)
Inventor
Toru Furuyama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP56087638A priority Critical patent/JPS57202776A/en
Publication of JPS57202776A publication Critical patent/JPS57202776A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
    • H01L23/5252—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising anti-fuses, i.e. connections having their state changed from non-conductive to conductive
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

PURPOSE:To increase the degree of freedom in designing the pattern for the titled device by a method wherein the first and the second wiring layers, which are intersecting each other through the intermediary of an interlayer insulating film, is formed in the event when they are required to be connected, and the film exposed in the contact hole provided at the intersecting part is broken down by applying a high voltage. CONSTITUTION:An SiO2 interlayer insulating film 12 is grown on an N type Si substrate 11 whereon a number of elements such as a transistor and the like were formed using CVD method, the first wiring layer 13 consisting of polycrystalline Si is formed on the film 12, and the wiring layer 13 is connected to the memory cell and the like located in the substrate 11. Then, the second wiring layer 14 of Al, which will be turned to a source wiring, is provided on the first wiring layer 13 through the intermediary of an interlayer insulating film 16 in such a manner that it is intersecting with the layer 13. Through these procedures, the wiring 13 is not ohmic-contacted to the wiring 14, and even when an unsatisfactory conducting state is generated on the circuit, no action is necessary to be taken. Also, when it is necesary to connect the above, the film 16 is broken down by applying a voltage higher than the source voltage, and a connection is performed using migration of Al.
JP56087638A 1981-06-08 1981-06-08 Semiconductor device Pending JPS57202776A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56087638A JPS57202776A (en) 1981-06-08 1981-06-08 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56087638A JPS57202776A (en) 1981-06-08 1981-06-08 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS57202776A true JPS57202776A (en) 1982-12-11

Family

ID=13920517

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56087638A Pending JPS57202776A (en) 1981-06-08 1981-06-08 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS57202776A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58110053A (en) * 1981-12-24 1983-06-30 Fujitsu Ltd Semiconductor device and manufacture thereof
JPS62242336A (en) * 1986-04-07 1987-10-22 アメリカン・マイクロシステムズ・インコ−ポレイテツド Programmable fuse
JPH02295155A (en) * 1989-05-09 1990-12-06 Nec Corp Multilayer wiring semiconductor device
US6476477B2 (en) * 2000-12-04 2002-11-05 Intel Corporation Electronic assembly providing shunting of electrical current

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58110053A (en) * 1981-12-24 1983-06-30 Fujitsu Ltd Semiconductor device and manufacture thereof
JPS62242336A (en) * 1986-04-07 1987-10-22 アメリカン・マイクロシステムズ・インコ−ポレイテツド Programmable fuse
JPH02295155A (en) * 1989-05-09 1990-12-06 Nec Corp Multilayer wiring semiconductor device
US6476477B2 (en) * 2000-12-04 2002-11-05 Intel Corporation Electronic assembly providing shunting of electrical current

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