JPS58110053A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To obtain the cell element of simple structure suitable for formation of an ROM, etc., by a method wherein a second conductive region is stacked on a first conductive region interposing an insulating film having thin film parts between them, and mixtures with the second conductive regions are formed selectively at the thin film parts to attain conduction. CONSTITUTION:Belt-shaped n<+> type layers 3 of a plural number are formed on an Si substrate 2, and after a thick SiO2 film 4 is stacked and windows are opened selectively, the window parts are covered with thin SiO2 films 4' and evaporated with Al films 1, and patterning is performed in the belt type. A matrix formed with the thin SiO2 films 4' only at the points of intersection of the layers 3 an the films 1 is completed. When a metal mask is applied and the desired points of intersection are scanned at the speed of about 4 inch/sec by the Ar layer beam of then several watts, Al at the irradiated points of intersection only is molten to be mixed with the SiO2 layers, and the films 1 and the n<+> type layers 3 attain conduction. The surface is covered with PSG5 finally to protect. According to the construction thereof, formation in a program can be attained simply, and this method is extremely effective.

Description

DETAILED DESCRIPTION OF THE INVENTION (1) @Ming's technical field My main focus is on semi-four-circle devices and seven-head manufacturing methods, especially on semiconductors with a novel structure that can be easily switched on and off. Regarding the device and its manufacturing method.

(2) Background of technology Semiconductor memories are rapidly becoming popular, with electronic 1. It is used in all kinds of electronic devices such as desks, but each bit of such semiconductor memory is made up of multiple or single semiconductor elements, which leads to the integration of functions, miniaturization, and low cost. In order to achieve this goal, even higher densities and higher integration levels are expected.

(8) Prior art and problems Among semiconductor memories, ROM, (Rea, 10nlyM
10n1y) is read-only, and is set to lll1! in advance. A signal of "0" or "1" is applied to each bit when storing (this is called a mask ROM) or when using (this is called a programmable ROM), and after that it cannot be rewritten. One bit of such a memory consists of, for example, one MO8dO8 polysilicon fuse, and character patterns are often constructed in a matrix-like circuit as a memory array.

Therefore, it has a relatively simple structure, but for high-speed operation and low cost, it is further simplified to 1%T? It goes without saying that being ranked as a B is the most important thing.

(4) Purpose of the Invention The present invention provides a method for implementing such a ROM or its circuit.
111, we propose a cell element with the simplest structure and its manufacturing method.

(5) @ Akira's structure The feature of the present invention is that the second four-electrode region of 1gl is connected to the second four-electrode region through an insulating film having one thin film region or several fJi regions.
A conductive region is provided, and in the thin film thickness region, the first conductive region and the second conductive region are selectively connected to each other through a mixture of the insulating film and the second conductive region. The present invention relates to an electrically connected semiconductor device and a method for manufacturing the same, and will be described in detail below using Examples.

(6) Embodiment of the Invention FIG. 1 illustrates a matrix diagram of a ROM memory array, in which the memory cells are located at coordinate positions (Xi).

(Yl), ・・・・・・・・・・・・(X4L (Y4
) are arranged. The coordinate position of each bit is formed in a cross-sectional structure as shown in FIG. intervening between the two, &
810. Membrane 4 is located at the intersection 4' of A11lll and conductor *ma.
It is formed thinly at each coordinate position, and the film thickness is about 400 people. Other than this intersection 4', the film thickness of Si and 02Fs4 is 6000 mm thick, the Al film is 8000 mm thick, the conductive layer is about 8009 mm thick, and the top surface is made of phosphosilicate glass as a protective layer. PSG) membrane 5 is coated.

In such a structure, as it is, the coordinate positions of the intersections of the Al film 1 and the conductive layer 8 are all insulated, and there is no conduction even if a voltage of several volts to several tens of volts is applied. However, if the desired coordinate position is irradiated from one side with an energy beam such as a laser beam, the irradiated position will melt and become 5i02
yli4 is mixed and electrically connected to the conductive layer to form Ae
A conductive state exists between the membrane 1 and 4wL1114B. In this way, a ROM is created by setting the desired coordinate position of the intersection of a large number of A4$1 and the conductive layer 8 to ON (4dji), and setting the coordinate position not irradiated with laser light to OFF (non-conducting) 1-. Ru.

Such a ROM can be easily manufactured using a known semiconductor device manufacturing method.

In FIG. 2, a large number of NG impurity layers, for example, are formed in strips on the 2 surface of the 81 substrate to form a conductive tm8, and then a thick 5i-02 film 4 is formed by high temperature oxidation treatment.

Next, a desired point on the 5102 film 4 of conductive TMA soil is opened using a photo process, and high-temperature oxidation treatment is performed again to form a window at that position.
Form a thin 5i02[4 part of 00A, and add A on the top surface.
11Ii! 1 is deposited by vaporization 7f method.Next, the Ag film 1 is patterned to form a strip pattern of the Al film 1 (1) that intersects the conductive layer 8 at right angles, and conductive jmB and Al film 1 are formed.
A thin Sin film 4' was formed only at the intersection with 7.
Create Tricks. Then, a PSG film 5 is coated on the upper surface.

Next, the energy beam to be irradiated to turn on is, for example, an argon laser beam, and a power of 10 watts is added to the beam. Formation is easy if the surface is covered with a metal mask that exposes only the coordinate position where the ROM pattern is to be turned on, and the laser beam is scanned at a speed of 4 inches/sheet.

In this way, unlike conventional mask ROMs, there is no need to convert and form mask patterns during the manufacturing process, and the programming operation is easy.

It can also be easily programmed by the user.

Programming A consisting of conventional polysilicon fuses
In the case of /ROM, fuses made of polysilicon are arranged in a planar manner, whereas this structure has a vertical structure, so it is more flexible.

However, in the case of a polysilicon fuse when it is covered with PSG as a recording protection film, there is a problem with reliability due to fragments flying off.

As an example of the pond, a thin 5i02 fi4, A4? Alternatively, a #4 structure with a surface layer of PSG8116 laminated thereon can be provided within the circuit of the integrated circuit and used as a reverse fuse. A fuse is used to break a conductive state, whereas a reverse fuse is used to connect a non-conductive state. For example, in the large memory shown in FIG. 8, the hit line L1 containing the defective memory cell is cut,
Processing is being done to replace the extra bit line LA (!--, but in that case, if the bit line LA is provided with the circuit structure 81 according to Akira Honshi and a beam of light is irradiated to make it conductive, The bit line LL including the defective bit 7μ is cut by cutting the fuse 2 portion made of polycrystalline silicon, as in the conventional case.

Furthermore, in an integrated circuit (C') IIC that constitutes a logic circuit, a circuit structure according to the present invention is provided in each circuit unit such as a gate array or a programmable logic array, and the beam light is selectively applied. It is possible to irradiate the beam and connect it to the desired circuit configuration. Therefore, since it is only necessary to perform the writing process on the completed IC, the delivery time is shortened, and the user can also irradiate the beam and connect it to the desired circuit configuration. It becomes possible to configure

There are many bell circuits in this + invention, but the energy beam can be irradiated not only with a laser beam but also with a beam of light such as an electron beam.

Also, as long as the upper surface 9 [[[ is a transparent insulating material that allows the beam to pass through, it may be any dust other than PSO material. Also, Hiroi Sing
If the film thickness of 1% is in the range of several tens to 1,000 layers, the beam irradiation energy can be increased or decreased to achieve a conductive state.

(7) Effects of the Invention As can be seen from the above explanation, the present invention is the simplest circuit structure element and its manufacturing method. It is extremely effective in that it makes writing easier.

[Brief explanation of drawings]

Figure 1 is a ROM memory array diagram to which the present invention is applied;
Is the diagram related to the invention? Cross section #4 structure, Figure 8 shows an example of the pond application. ing. 7do cxdlj'K 1st 1st 3rd leap Lmnnθn ~, LA

Claims (1)

[Claims] (1) A second conductive region is provided through a thin at-layer having one or more thin film regions on the first (D411) region, and in the thin film region, the insulating film and the A semiconductor device characterized in that the first four-conducting region and the second conductive region are electrically connected selectively through a mixture with a second 41jtvR region. After forming a second conductive et@ implant through an insulator 1111 having at least one thin film region or an integer number of thin film regions on the region, the thin film region is irradiated with an energy beam t. A method for manufacturing a semiconductor device, characterized in that the first conductive region and the second metropolitan area W4 are connected at once.