JPH0343788B2 - - Google Patents
Info
- Publication number
- JPH0343788B2 JPH0343788B2 JP570982A JP570982A JPH0343788B2 JP H0343788 B2 JPH0343788 B2 JP H0343788B2 JP 570982 A JP570982 A JP 570982A JP 570982 A JP570982 A JP 570982A JP H0343788 B2 JPH0343788 B2 JP H0343788B2
- Authority
- JP
- Japan
- Prior art keywords
- fuse
- film
- rom
- blown
- stepped portion
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 claims description 8
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 12
- 229920005591 polysilicon Polymers 0.000 description 12
- 239000000463 material Substances 0.000 description 7
- 238000000034 method Methods 0.000 description 6
- 229910052782 aluminium Inorganic materials 0.000 description 5
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 5
- 239000011159 matrix material Substances 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000002844 melting Methods 0.000 description 2
- 230000008018 melting Effects 0.000 description 2
- 239000007769 metal material Substances 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 238000003491 array Methods 0.000 description 1
- 238000007664 blowing Methods 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 231100000989 no adverse effect Toxicity 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000011179 visual inspection Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
- H01L23/5256—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising fuses, i.e. connections having their state changed from conductive to non-conductive
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Read Only Memory (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
- Semiconductor Memories (AREA)
Description
【発明の詳細な説明】
(1) 発明の技術分野
本発明はヒユーズ型半導体記憶装置において、
特にヒユーズ材料としてポリシリコン膜を用いた
ヒユーズ型半導体記憶装置に関する。[Detailed Description of the Invention] (1) Technical Field of the Invention The present invention provides a fuse-type semiconductor memory device that includes:
In particular, the present invention relates to a fuse-type semiconductor memory device using a polysilicon film as a fuse material.
(2) 技術の背景
ヒユーズ型半導体記憶装置(以後ヒユーズ
ROMと省略する)は電気的な接続回路を半導体
装置にマトリツクス状に作りパルス等による過大
電流により所定の部分を溶断して回路を開くか、
又は溶断せずに閉じたまゝにしておくかにより
「1」、「0」の記憶を行なわせるものである。こ
のためヒユーズROMはその構造がきわめて容易
に作れ、この中では通常のヒユーズのみを使用し
たもの、ダイオードをヒユーズとして使用したも
の、トランジスタのエミツタ、ベース、コレクタ
の各回路をヒユーズとして使用したもの等があ
る。(2) Technical background Fuse-type semiconductor memory devices (hereinafter referred to as fuse)
(abbreviated as ROM) is a process in which electrical connection circuits are formed in a matrix in a semiconductor device and the circuits are opened by melting a predetermined part using excessive current caused by pulses, or by opening the circuit.
Alternatively, "1" and "0" can be stored by keeping it closed without blowing it out. For this reason, fuse ROMs can be constructed very easily, including those that use only ordinary fuses, those that use diodes as fuses, and those that use the emitter, base, and collector circuits of transistors as fuses. There is.
このヒユーズROMはその構造が簡単であるこ
とから同一ビツト数の半導体記憶装置とするの
に、他のP−ROMに比較して数倍、小さい面積
で間に合わせることが出来る利点をそなえている
のが特徴であり、このヒユーズROMを用いた代
表的例を第1図に示す。X1〜X4は各々のビツト
線であり、Y1〜Y4は各々のワード線2であり、
ビツト線とワード線によりマトリツクス状を形成
し、その交点を3,4,5で示すヒユーズで接続
されている。このヒユーズはポリシリコン膜等の
高濃度不純物を含んだもの、又は金属材料やダイ
オード、トランジスタ等で構成されているものが
通常である。 Because this fuse ROM has a simple structure, it has the advantage that it can be made into a semiconductor memory device with the same number of bits in an area several times smaller than other P-ROMs. A typical example using this fuse ROM is shown in Figure 1. X 1 to X 4 are each bit line, Y 1 to Y 4 are each word line 2,
Bit lines and word lines form a matrix, and their intersections are connected by fuses indicated by 3, 4, and 5. This fuse is usually one containing a high concentration of impurities, such as a polysilicon film, or one made of a metal material, a diode, a transistor, or the like.
今たとえば、ビツト線X1とワード線Y1はヒユ
ーズ3により、又ビツト線X2とワード線Y2はヒ
ユーズ4の如く多数にわたりそれぞれ接続されて
いる時、この様な状態は情報が「0」であるとし
て、一方ビツト線X3とワード線Y3との間にパル
ス等による過大電流を流しヒユーズ5を溶断さ
せ、この間を開いた状態にし、この様な状態の情
報を反対に「1」の書き込みとする。 For example, when bit line X 1 and word line Y 1 are connected by fuse 3, and bit line X 2 and word line Y 2 are connected by fuse 4, such a state means that the information is '', on the other hand, an excessive current is applied by a pulse or the like between the bit line ” should be written.
この様にヒユーズROMは任意のマトリクスア
レイの位置をそれぞれ溶断させ電気的に断線させ
るだけの構造で原理的には至つて簡単であり、多
数のマトリツクスアレイを組む事により大きなビ
ツト数の記憶装置を作ることが出来る。 In this way, the fuse ROM has a structure that is extremely simple in principle as it simply fuses and electrically disconnects each position in the matrix array, and by assembling a large number of matrix arrays, it is possible to create a storage device with a large number of bits. can be made.
(3) 従来技術の問題点
現在用いられているヒユーズ材料として半導体
装置内に作り付けられるダイオード、トランジス
タは別として配線用材料としてのヒユーズROM
は主にアルミニウム膜又はポリシリコン膜である
が、一般に半導体装置の配線に広く用いられてい
るアルミニウム膜は電気伝導度が良すぎ、その為
に過大なパルス電流を溶断する時に要する欠点が
ある。又この電流を少なくするために、溶断部の
ヒユーズ形状、特に巾を充分細くする必要があり
微細パターン形成及びフオトエツチング精度向上
の問題に及んで来る。又溶断する電流を下げる他
の方法として、アルミウム膜の厚みを減少させる
方法があるが前記のヒユーズ形状の形成時の必要
な膜厚と外部配線とのコンタクトを取る必要な膜
厚とは異り同一膜厚で両者を満足させることは出
来ない。また膜厚を変えたとしても工程の増加、
両者のエツチング制御方法等の問題も出て来て統
一点を見い出し得ることはさらに困難である。(3) Problems with the conventional technology Apart from the diodes and transistors that are built into semiconductor devices as currently used fuse materials, fuse ROM is used as a wiring material.
is mainly an aluminum film or a polysilicon film, but the aluminum film, which is generally used widely for wiring in semiconductor devices, has too good electrical conductivity and has the disadvantage that it is required to melt an excessively high pulse current. Furthermore, in order to reduce this current, it is necessary to make the shape of the fuse at the blown part sufficiently thin, especially the width, which leads to problems in forming fine patterns and improving photoetching accuracy. Another way to reduce the fusing current is to reduce the thickness of the aluminum film, but the film thickness required when forming the fuse shape is different from the film thickness required to make contact with external wiring. It is not possible to satisfy both requirements with the same film thickness. Also, even if the film thickness is changed, the number of steps will increase,
Problems such as the etching control method for both methods also arise, making it even more difficult to find a common point.
(4) 発明の目的
本発明は以上の欠点を除去したものであり、そ
の目的は絶縁膜上の厚さの差で生じる熱伝導率の
差を利用して段差部分でヒユーズ材のフローによ
り溶断させ、溶断電流を少さくすると共に回路パ
ターンに占有するヒユーズROMの面積を少さく
しようとするものである。(4) Purpose of the Invention The present invention eliminates the above-mentioned drawbacks.The purpose of the present invention is to utilize the difference in thermal conductivity caused by the difference in thickness on the insulating film to blow the fuse material at the stepped portion by flowing. This aims to reduce the fusing current and the area occupied by the fuse ROM in the circuit pattern.
(5) 発明の構成
即ち本発明のヒユーズROMは、段差部が設け
られた絶縁膜であつて、該段差部の下段側より上
段側の方が膜厚が厚い絶縁膜と、該段差部上に設
けられ、該段差部上にて溶断される厚みを持つヒ
ユーズとを有するものである。(5) Structure of the Invention In other words, the fuse ROM of the present invention includes an insulating film provided with a stepped portion, the insulating film being thicker on the upper side of the stepped portion than on the lower side; and a thick fuse that is disposed above the stepped portion and is blown by melting above the stepped portion.
(6) 発明の実施例
以下本実施例を第2図により説明すると、まず
シリコンウエハー6のP型(100)10Ωmに初期
酸化膜7をWetO2、1000℃で1μm程度付ける。
次に窓開きしゲード酸化膜8をHcl酸化により
300〜1000Åを付ける。ポリシリコン膜9を減圧
CVD法により4000Åの膜厚を付けて窓開き及び
パターニングを行う。このポリシリコン膜9とソ
ース及びドレイン10、をイオン注入法により、
例えばAsを5×1015dose、150Kevで所定の濃度
及び深さを形成する。次にPSG膜11を全面に
被膜としてかぶせソート及びドレインの電極窓を
開く。(6) Embodiment of the Invention The present embodiment will be explained below with reference to FIG. 2. First, an initial oxide film 7 of about 1 μm is formed on a P-type (100) 10Ωm silicon wafer 6 at 1000° C. in WetO 2 .
Next, open the window and gate oxide film 8 by HCl oxidation.
Attach 300 to 1000Å. Depressurize polysilicon film 9
Windows are opened and patterned to a film thickness of 4000 Å using the CVD method. This polysilicon film 9 and the source and drain 10 are formed by ion implantation.
For example, a predetermined concentration and depth is formed using 5×10 15 doses of As and 150 Kev. Next, the entire surface is covered with a PSG film 11 to open the sort and drain electrode windows.
次にアルミニウム膜12を配線材料としてパタ
ーニングして最後にPSG膜14を全体に被膜と
してかぶせ完成させる。この時の溶断されるべき
ヒユーズ部分13は最後のPSG膜によりかぶせ
られて、ヒユーズROMとなり第1図の左側の素
子は選択トランジスタの1例を示した。 Next, the aluminum film 12 is patterned as a wiring material, and finally the PSG film 14 is covered as a film to complete the process. The fuse portion 13 to be blown at this time is covered with the last PSG film and becomes a fuse ROM, and the element on the left side of FIG. 1 shows an example of a selection transistor.
上記のポリシリコン膜は減圧CVD法により
4000Åの膜厚に付着し、溶断されるべきヒユーズ
部分の巾Wを2.5μm、長さを10μmとした時の、
この時にポリシリコン膜のヒユーズに100mWの
パルス電流を10μs流すことにより容易に溶断が行
われ任意の位置のプログラミングが可能となる。 The above polysilicon film was created using the low pressure CVD method.
When the width W of the fuse part that is attached to a film thickness of 4000 Å and is to be blown is 2.5 μm and the length is 10 μm,
At this time, by passing a pulse current of 100 mW for 10 μs through the fuse of the polysilicon film, it is easily blown out and programming at an arbitrary position becomes possible.
また、本発明の特徴とする所は、絶縁膜上に形
成された溶断されるべきヒユーズの部分が絶縁膜
の上段と下段との部分に分かれ上段の絶縁膜(主
にSiO2)は膜厚が厚いため比較的下段より熱伝
導率が悪いため、ポリシリコン膜の粘性が熱によ
り流動性が増し段差部より下段部に向け流れる様
に移動し溶断させていく方法が行われる。さらに
本発明では最上部に透明なPSGガラス14が被
膜としてかぶせてあるため溶断したポリシリコン
膜が周囲に飛散して悪影響を及ぼすことがなく、
溶断した部分は白濁して目視出来るため目視検査
には好都合の条件が得られる。 Furthermore, the present invention is characterized in that the part of the fuse formed on the insulating film to be blown is divided into an upper part and a lower part of the insulating film, and the upper part of the insulating film (mainly SiO 2 ) is thinner. Since the polysilicon layer is thicker, its thermal conductivity is relatively lower than that of the lower layer, so a method is used in which the viscosity of the polysilicon film increases its fluidity due to heat, moves in a flowing manner from the stepped portion toward the lower layer, and is fused. Furthermore, in the present invention, since the transparent PSG glass 14 is covered as a film on the top, the melted polysilicon film does not scatter to the surroundings and have no adverse effect.
The melted part becomes cloudy and can be seen visually, providing convenient conditions for visual inspection.
第1図の本発明の1実施例を説明したヒユーズ
ROMのヒユーズ材料をポリシリコン膜に限定し
たが前述した如く溶断されるべきヒユーズ部分が
上段から下段に流動する材料、例えばアルミニウ
ム膜等の金属材料を用いて形成する場合に於ても
本発明の及ぶ所である。 Fuses illustrating one embodiment of the invention shown in FIG.
Although the fuse material of the ROM is limited to a polysilicon film, as described above, the present invention can also be applied when the fuse portion to be blown is formed using a material that flows from the upper stage to the lower stage, for example, a metal material such as an aluminum film. It is a place that can be reached.
(7) 発明の効果
以上説明した如く、初期酸化膜の厚いフイール
ド酸化膜に対しゲート酸化膜の薄い酸化膜の両者
の熱伝導率を利用してその段差部分で溶断させた
場合粘性の相違により従来の約半分の消費電力で
行え、さらに溶断個所が縦形であるためヒユーズ
ROM等パターンレイアウトで面積を縮少出来る
利点がある。(7) Effects of the Invention As explained above, when the initial oxide film is a thick field oxide film and the gate oxide film is a thin oxide film, if the thermal conductivity of both is used to fuse the stepped portion, the difference in viscosity The power consumption is about half that of conventional methods, and the fuse is cut vertically.
It has the advantage of reducing area in pattern layouts such as ROM.
第1図はヒユーズROMの代表的な記憶装置を
示した構成図であり、第2図は本実施例で一点鎖
線左側に選択トランジスタを示しそれに接続され
るヒユーズROMを右側に示した断面図である。
1;ビツト線、2:ワード線、3,4,5;ヒ
ユーズ、6;シリコンウエハー、7;初期酸化
膜、8;ゲート酸化膜、9;ポリシリコン膜、1
0;ゲート、ドレイン領域、11,14;PSG
膜、13;ヒユーズ溶断部。
Fig. 1 is a configuration diagram showing a typical storage device of fuse ROM, and Fig. 2 is a cross-sectional view showing the selection transistor on the left side of the dashed line in this embodiment and the fuse ROM connected to it on the right side. be. 1: Bit line, 2: Word line, 3, 4, 5; Fuse, 6: Silicon wafer, 7: Initial oxide film, 8: Gate oxide film, 9: Polysilicon film, 1
0; Gate, drain region, 11, 14; PSG
Membrane, 13; Fuse blown part.
Claims (1)
部の下段側より上段側の方が膜厚が厚い絶縁膜
と、 該段差部上に設けられ、該段差部上にて溶断さ
れる厚みを持つヒユーズとを有することを特徴と
するヒユーズ型の半導体記憶装置。[Scope of Claims] 1. An insulating film provided with a stepped portion, the insulating film being thicker on the upper side of the stepped portion than on the lower side; 1. A fuse-type semiconductor memory device comprising a thick fuse that is blown at the top.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP57005709A JPS58123759A (en) | 1982-01-18 | 1982-01-18 | Semiconductor memory storage |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP57005709A JPS58123759A (en) | 1982-01-18 | 1982-01-18 | Semiconductor memory storage |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS58123759A JPS58123759A (en) | 1983-07-23 |
JPH0343788B2 true JPH0343788B2 (en) | 1991-07-03 |
Family
ID=11618639
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP57005709A Granted JPS58123759A (en) | 1982-01-18 | 1982-01-18 | Semiconductor memory storage |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS58123759A (en) |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0241046A3 (en) * | 1986-04-11 | 1990-05-16 | Nec Corporation | Semiconductor device having fuse-type memory element |
JP2541533Y2 (en) * | 1990-01-11 | 1997-07-16 | 株式会社クラベ | Anti-fog mirror |
EP0563852A1 (en) * | 1992-04-02 | 1993-10-06 | Siemens Aktiengesellschaft | Zag fuse for reduced blow-current applications |
FR2723663B1 (en) * | 1994-08-10 | 1996-10-31 | Motorola Semiconducteurs | SEMICONDUCTOR FUSE DEVICES |
JPH11154706A (en) * | 1997-11-20 | 1999-06-08 | Mitsubishi Electric Corp | Semiconductor device |
JP4480649B2 (en) * | 2005-09-05 | 2010-06-16 | 富士通マイクロエレクトロニクス株式会社 | Fuse element and cutting method thereof |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5617060A (en) * | 1979-07-23 | 1981-02-18 | Fujitsu Ltd | Semiconductor device |
JPS5633853A (en) * | 1979-08-28 | 1981-04-04 | Nec Corp | Semiconductor device |
-
1982
- 1982-01-18 JP JP57005709A patent/JPS58123759A/en active Granted
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5617060A (en) * | 1979-07-23 | 1981-02-18 | Fujitsu Ltd | Semiconductor device |
JPS5633853A (en) * | 1979-08-28 | 1981-04-04 | Nec Corp | Semiconductor device |
Also Published As
Publication number | Publication date |
---|---|
JPS58123759A (en) | 1983-07-23 |
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