JPH02295155A - Multilayer wiring semiconductor device - Google Patents

Abstract

PURPOSE:To alter a partial circuit without influence to other circuit at all by providing a capacity type program element at an intersection between upper and lower layer interconnections, externally irradiating it with a laser light ray to perform a programming, and breaking down an insulating layer between the upper and lower wirings to short-circuit them. CONSTITUTION:Intersections between first layer Al wirings 12A, 12B, 12C and a second layer Al wiring 11-2 are respectively provided at the output of a delay circuit 14-1, an output of a delay circuit 14-2 and at an output of a delay circuit 14-3 for an input of the circuit 14-1, and the common wiring 11-2 is used as signal output wiring. The intersection is a capacity type program element provided with an insulating layer between Als, being nonconductive as it is, but it is externally irradiated with a laser light ray to locally damage the insulating layer between the first and second layer Al wirings, thereby welding the Als of the upper and lower layers to become conductive. A delay time can be realized in three ways by forming a short-circuit by the radiation of the ray at any of program elements 16-1, 16-2, and 16-3.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a multilayer wiring semiconductor device, and more particularly to a multilayer wiring semiconductor device suitable for confirming or evaluating characteristics at the time of design. [Conventional technology] Conventionally, in prototype-level semiconductor circuits, multiple levels were set for experimental purposes in order to evaluate the performance of unconfirmed circuits, and some patterns were changed to realize circuits of each level. Semiconductor devices of each level were created and evaluated using experimental mask patterns.

This will be explained using an example of delay same path. FIG. 2 shows that three delay circuits are formed on a semiconductor substrate, and in order to realize a three-level delay [j+ path, with the signal delay time as a level, the first layer A . This is an example of changing the Q wiring pattern. The through hole, which is a connection point with the second FAΔg wiring for connection with other circuits, is used in common to switch the connection of three types of delay circuits prepared in the INAρ wiring. Figure 2 (a) shows the series connection of delay circuits 4-1 to 4-3, and (b)
(c) is a three-level circuit connection in which delay circuits 4-1 and 4-2 are connected in series, and (c) is only a delay circuit 71-1. Masks corresponding to the β wiring patterns are prepared for each first layer. , it was necessary to create prototype crystals using each mask individually and evaluate them for each level.

3. Problems to be Solved by the Invention] In the conventional multilayer wiring semiconductor device described above, masks were created for each circuit level and prototypes created using each mask were evaluated. The number of man-hours required to create a mask increases, increasing the number of days and costs for product development. Furthermore, if the difference in circuit performance that is focused on when comparing the performance of prototypes by level is not sufficiently large compared to the difference in characteristics due to manufacturing variations in the prototypes, there is a drawback that sufficient characteristics evaluation cannot be performed. .

[Means to solve the problem]

A multilayer wiring semiconductor device according to the present invention includes a plurality of electrical circuits having wirings in a certain layer, and wirings in another layer intersecting each input signal wiring or output signal wiring of the electric circuit with an insulating layer interposed therebetween. A81 circuits with at least two types of characteristics are realized by programming that destroys the insulating layer of the program element.

〔Example〕 Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a schematic plan view showing a delay circuit according to a first embodiment of the present invention. Delay circuit 14-1.14-2 formed on a semiconductor substrate.
14-3, and the number for connecting each circuit]
Layer Ai! Wiring 12.12A. 12B, 12C and upper second layer AI wiring 11-1, ]1-2 via an interlayer insulating layer such as a silicon oxide film. different 3
Delay circuit 14-1.1 to realize different types of delay time
4-2.14-3 are connected in series with the first layer An wiring 12,
The output section of the delay circuit 14-1 corresponds to the input section of the delay circuit 14-1. Output section of delay circuit 14-2. Delay episode F! @14-
The first layer A-Q wiring 12A, 12 is connected to the output section of 3, respectively.
A common second layer A.B, 12C and the second layer A.rho. The R wiring 11-2 is used as the signal output wiring. The above-mentioned intersection is a capacitive programming element with an insulating layer (interlayer insulating film) between Aρ, and is non-conductive as it is, but by irradiating a laser beam from the outside and adjusting its intensity, 1st layer A.
The Q wiring and the second layer A {dissolve the wiring, locally destroy the insulating layer between them, and dissolve the upper and lower layers A. Q can be welded to make it conductive. Program element 1 to program the short circuit by laser beam irradiation
By performing this in any part of 6-1.16-2.16-3, the desired delay time can be achieved in three ways. The laser beam used to short-circuit and program the AI wiring can usually focus the light to a diameter of about 2 to 3 μm, so an area of about 5 to 6 μm on each side is sufficient for the size of the intersection, and the area is also small. Almost no need. FIG. 3 is a schematic plan view showing a second embodiment of the present invention.

Switching of the electric circuit 27-1.27-2 is performed using the second layer Aρ.
Connection between the wiring and the electric circuits 27-1, 27-2 can be realized by using capacitive program elements 26-1, . . . , and disconnection can be realized by using fuse-type program elements 291 to 29-4, respectively. In other words, the connection can be performed by AIl welding by irradiating the intersection of the first layer Al wiring and the second layer AJ wiring with a laser beam, as described in the first embodiment. For cutting, a fuse-type program element made of a second-layer A film is inserted into the first-layer AII wiring of the signal line, and a laser beam of the same intensity as programming with a capacitive program element is applied to the second layer. This can be achieved by irradiating the AiI film.

In this way, the electric circuit 271.27-
2 switching can be realized, so the effect of this circuit difference can be confirmed without being influenced by other characteristics at all.

〔Effect of the invention〕

As explained above, in the present invention, a capacitive programming element is provided at the intersection of the lower-layer wiring and the upper-layer wiring, and programming is performed by irradiating and irradiating a laser beam from the outside to destroy the insulating layer between the lower-layer wiring and the upper-layer wiring. By short-circuiting the circuit, it becomes possible to change a part of the circuit without affecting the circuit at all. Therefore, only one type of mask is required even if the circuit has many levels. In addition, since the effects of each level can be compared using a single semiconductor device, it is possible to accurately investigate the effects without being affected by variations between samples, which reduces the development cost and time required for prototype-level conductor devices. This has a great effect on reducing
It is clear that the present invention can be applied to trimming the characteristics, in which case it becomes possible to finely tune the characteristics.

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Claims (1)

[Claims] A capacitive program element including a plurality of electrical circuits each having wiring in a certain layer, and wiring in another layer intersecting each input signal wiring or output signal wiring of the electric circuit with an insulating layer interposed therebetween. A multilayer wiring semiconductor device characterized in that integrated circuits having at least two types of characteristics are realized by programming that destroys an insulating layer of the program element.