JPH02239625A - Semiconductor device - Google Patents

Abstract

PURPOSE:To form a contact hole having a conductive film of good coverage and to improve reliability of a device by forming a layer insulating film of a three-film structure which is formed by laminating a silicon oxide film, a silicon/nitride film and a boron/phosphorus/silicic acid glass film successively from the side of a silicon substrate. CONSTITUTION:A silicon substrate 11 of a memory is provided with a contact hole 14 which is opened by applying isotropic and anisotropic etching to a source/drain section 12 and a layer insulating film 13 successively, and a conductive film 15 as a bit line which is deposited on the hole 14 and the layer insulating film 13. Furthermore, the layer insulating film has a three layer structure which is made by laminating an SiO2 film 16 for preventing impurity diffusion, a silicon nitride film 17 which serves as a barrier for isotropic etching, and a silicon oxide film 18 for flattening successively from the side of the substrate 11 upward. Thereby, it is possible to control a depth of a contact section shallow and to form a contact hole having a conductive film of good coverage.

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Industrial Application Field The present invention relates to a semiconductor device, and more specifically, the present invention relates to a semiconductor device, and more specifically, a contact hole formed in an interlayer insulating film is formed in the upper layer of the interlayer insulating film by controlling the depth of the contact hole to be shallow. The present invention relates to a MOS transistor memory in which a bit line can be in good contact with underlying source/drain and gate electrodes.

(Example) Conventional technology In recent years, with the miniaturization of devices, it has become necessary to use highly reflective metals such as AI alloys for the bit lines of this heel memory. The problem is whether to flatten the interlayer insulating film between them. For this reason, a method has been proposed in which planarization is achieved by using a silicon oxide film (hereinafter abbreviated as BPSG) mixed with boron (B) and phosphorus (P), which causes reflow at low temperatures in the interlayer insulating film. has been done.

Conventionally, in memories using BPSG, which uses thermal reflow to planarize the interlayer insulating film, the third
A contact hole is opened by the method shown in the figure.

First, in FIG. 3(a), a silicon base film having an impurity diffusion layer 2, a gate oxide film 3, a gate electrode 4 and a silicon oxide film 5 is formed, and then as shown in FIG. 3(b), , silicon base Fi. A silicon oxide film 6,
BPSG films 7 are stacked, and an interlayer insulating film 30 is formed using these films. At this time, the thickness of the BPSG film 7 becomes extremely thick in regions such as the source/drain region 2 surrounded by the gate electrode 4 and the like.

Next, as shown in FIG. 3(c), after forming a contact pattern using photoresist 8, isotropic etching is performed using Budsfurd hydrofluoric acid to remove the corners of the contact and improve coverage during subsequent metal formation. We are trying to

After that, anisotropic etching is performed by RIE to open a contact and form a contact hole 9. Then, the resist 8 is removed, and after cleaning, barrier metal tO and AI alloy 11 are removed.
(or an AI alloy alone) to form a bit line [see FIG. 3(d)].

(c) Problems to be Solved by the Invention However, since the stacking of the AI alloy 11 or the barrier metal 10 is usually performed by sputtering, the coverage is poor, and the contact hole 9 with a very small opening diameter and deep As shown in d), the contact hole 9
There is a risk that the metal lO will not adhere to the wire and the wire will break.

Moreover, the metal becomes thin locally without causing wire breakage, and electromigration occurs, resulting in poor reliability of the device.

On the other hand, it is possible to reduce the effective depth of the contact by increasing the amount of isotropic etching, or if it is too much, the thickness of the interlayer insulating film with the gate electrode becomes thinner. This results in an increase in leakage current between the upper layer bit line meter and the gate electrode. Therefore, in order to insulate both, the thickness of the silicon oxide film must be about 1000, which limits the amount of isotropic etching.

(2) Means for Solving the Problems This invention provides an impurity diffusion layer formed on a semiconductor substrate in a predetermined region, an interlayer insulating film formed on the entire surface including on the predetermined region, and an impurity diffusion layer formed on the entire surface including on the predetermined region. The interlayer insulating film located on the layer includes a contact hole formed by etching, and a conductive film deposited on the contact hole and on the interlayer insulating film. This semiconductor device is characterized in that it has a three-layer structure in which a silicon oxide film, a silicon nitride film, and a boron-phosphorus-silicate glass film are laminated.

That is, in the present invention, the interlayer insulating film is formed into a three-layer laminated film, and when the upper layer is opened by etching to form a contact hole in the middle layer, a silicon layer that can prevent etching of the lower layer is provided. -Uses an etching barrier layer made of nitride.

In this invention, the lower layer silicon oxide film (Sins film) is used for the purpose of preventing impurity diffusion, and the upper layer BP
The SG film is used for planarization.

The silicon nitride film of the intermediate layer is a film that acts as a barrier against isotropic etching, thereby eliminating the upper limit of the amount of isotropic etching.

The three-layer laminated film described above can be formed using a known method such as the CvD method.

(E) Effect With the above configuration, the interlayer insulating film in which the contact hole is formed is connected to the underlying silicon oxide film for preventing impurity diffusion.
Because it is formed in a three-layer structure consisting of a silicon nitride film that acts as a barrier to etching the intermediate layer and a BPSG film that flattens the upper layer, it is possible to eliminate restrictions on the amount of etching of the upper layer. The depth of the contact hole can be controlled to be shallow, and a contact hole having a conductive film with good coverage can be formed. Furthermore, since a BPSG film is used, an interlayer insulating film with good planarization can be formed.

(f) Example Embodiments of the present invention will be described in detail below with reference to the drawings.

However, the invention is not limited thereby.

FIG. 1(d) shows an MO in which the source/drain part, the gate electrode, and the bit line are brought into contact with each other through a contact hole formed by opening the interlayer insulating film to establish conduction.
A memory of an S transistor is shown.

In FIG. 1(d), the memory is silicon-based! i11
Above, source/drain parts formed in predetermined areas! 2
A contact is opened by sequentially isotropically etching and anisotropically etching the interlayer insulating film l3 formed on the entire surface including the above-mentioned predetermined region, and the interlayer insulating film l3 located on the source/drain part l2. It mainly includes a hole l4 and a conductive film l5 as a bit line deposited over the contact hole and on an interlayer insulating film l3.

Furthermore, the interlayer insulating film includes, in order from the side of the silicon substrate 11 upwards, an SIOz film 16 for preventing impurity diffusion, a silicon nitride film 17 serving as a barrier for isotropic etching, and a BPSG film 18 for planarization. It has a three-layered structure.

Further, the conductive film is composed of a barrier metal layer [9] made of titanium tungsten or titanium nitride, and an aluminum alloy 20 laminated thereon. 2
1 and 22 are a gate oxide film and a silicon oxide film, respectively, and 23 is a gate electrode.

Next, the first manufacturing method will be explained.

In FIG. 1, FIG. 1(a) shows a silicon substrate 11 after forming a gate electrode 23 and a source/drain part 12.
It shows. Next, approximately 1000% of SiOx was deposited using the CVD method.
~2000 people are coated to form a silicon oxide film l6.

This is to insulate the bit line metal and the gate electrode, and the above film thickness is required due to its ability.

Next, this SiO. IlIl6 upper +: L P -
About 100 to 200 layers of StsN+ are coated by CVD method to form a silicon nitride film 17. 4000 to 6000 layers of BPSG are formed thereon by the CVD method, and heat treated at 900°C for about 30 to 40 minutes in a nitrogen atmosphere to form a flattened BPSGWA18 [Fig. 1(b)] reference]. After that, photoresist 2
4. Form a contact pattern and mask it with water:
Ammonium fluoride = 10:1 buffered hydrofluoric acid (
Perform an isotropic etch of BPSGII l 8 in BHF') [see FIG. 1(c)]. At this time, the St of LP-CVD
Since sNa has a selectivity ratio of BHF to BPSG of about 40, if the StsN4 film l7 has a thickness of 100 to 200 nm, it is sufficient to act as a barrier for isotropic etching, and at this time, If the amount of etching is set such that the thickness d of the remaining BPSG film 182L in the contact portion is about 60% of the contact diameter D, then the portions t7a and 17b of the SisNa film can be etched. There is no problem even if it is exposed.

Then, in this state, the remaining BPSG film 18a, silicon nitride film portion 17c, and Sif2 film portion 16a are anisotropically etched by reactive ion etching on the shallow contact portion, and the depth is A contact hole 14 is formed by opening a contact with a controlled depth, and after cleaning, a barrier metal 19 and an aluminum alloy 20 are formed by sputtering [Fig. 1(d)
) Reference ko.

In this example, in the process of opening the interlayer insulating film to bring the source/drain portions and gate electrode portions into contact with the bit line for conduction, the opening of the contact hole is formed by isotropic and anisotropic etching. When performing isotropic etching, a material that acts as a barrier to isotropic etching is used as the lower layer of the BPSG film as the reflow insulating film, so it is possible to eliminate the upper limit on the amount of isotropic etching, and it is possible to It is possible to improve metal cabareno.

In this example, the upper layer BPSG film l8 is isotropically etched to form a shallow contact portion, and the BPSG@l 8 a remaining in the contact portion is further removed by anisotropic etching. However, the Noricon nitride film as the intermediate barrier layer is further thickened and the BPSG film 18a is also subjected to isotropic etching, and the subsequent anisotropic etching is performed from the barrier layer. You can do it as well.

That is, as shown in Fig. 2, isotropic etching is performed using silicon nitride@27 stacked to a thickness of 1000 to 2000 mm as a barrier layer, and an opening is made by RIE to a depth of The shallow contact portion may be composed of the barrier layer portion 27a and the Sins film portion l6λ. As a result, the amount of etch in RIE can be reduced by B
By eliminating the need to remove the PSG film 18a, the Sing film thickness 16a directly below the pariah layer portion 27a can be made uniform. It has the effect of suppressing etching on the surface.

(G) Effects of the Invention As described above, according to the present invention, in a MOS transistor memory, good contact can be achieved through a contact hole formed by opening an interlayer insulating film located between a source/drain line and a bit line. The interlayer insulating film is composed of a three-layer laminated film, and the middle layer is a silicon nitride film that can prevent etching of the lower layer when etching is performed to form a contact hole in the upper layer. Since it is used, an interlayer insulating film with good planarization can be formed, and a contact hole having a conductive film with good coverage can be formed, which has the effect of improving the reliability of the device.

[Brief explanation of drawings]

FIG. 1 is an explanatory diagram of a manufacturing process for explaining one embodiment of the present invention, FIG. 2 is an explanatory diagram of another manufacturing process, and FIG. 3 is an explanatory diagram of a manufacturing process for explaining a conventional example. 1...Silicon substrate, 2...Source/drain section, 3...Interlayer insulating film, 4...Contact hole, 5... Conductive film, 6...Sign film, 7.27...Silicon nitride film, 8.
...BP! 3G film, 9... Barrier metal layer, O... Aluminum alloy, 3... Gate electrode.

Claims (1)

[Claims] 1. An impurity diffusion layer formed in a predetermined region on a semiconductor substrate, an interlayer insulating film formed on the entire surface including above the predetermined region, and an interlayer insulating film located on the impurity diffusion layer are opened by etching. The interlayer insulating film includes a contact hole formed and a conductive film deposited on the contact hole and an interlayer insulating film, and the interlayer insulating film is made of a silicon oxide film, a silicon nitride film, a boron phosphorous film, and a silicon nitride film in order from the silicon substrate side. A semiconductor device characterized by having a three-layer structure in which silicate glass films are laminated.