JPH04155963A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To improve the reflow shape of a layer insulation film to prevent unnecessary aluminum from remaining by providing a normal pressure CVD insulating film being a sidewall on both sides of floating gate and control gate. CONSTITUTION:After a gate oxide film 2 is formed on a P-type silicon substrate 1 and then a floating gate 3, second gate oxide film 4 and control gate 5 are patterned to form a polysilicon oxide film 6, N<+>-layer 7 is formed by arsenic ion implantation. Subsequently, a CVD oxide film 8 to be a sidewall is grown on the whole surface of a wafer. At that time, the CVD oxide film in the stepped part of the control gate is thicker than that in the flat part thereof. Therefore, when anisotropic etching is conducted for the film thickness of the flat part, the desired side wall of CVD oxide film 8 is formed on both sides of the floating gate and control gate. After that, BPSG film 9, silicon oxide film 10 and BPSG film 11 are formed successively.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a semiconductor integrated circuit device, and in particular to an EPROML device.
SI et al., relates to the surface structure of a semiconductor integrated circuit device having an interlayer insulating film having a good flow shape.

[Conventional technology]

In recent years, semiconductor integrated circuit devices have become increasingly smaller due to the demand for higher integration and higher speed, and the dimensions of the elements included in them have become increasingly finer. It is strongly desired to have a structure. Conventional E
In PROM, after forming the floating gate and control gate as shown in Figure 2(a),
A normal pressure CVD insulating film, a thin silicon nitride film, and a normal pressure CVD insulating film were formed as interlayer insulating films. Therefore, since the floating gate and the control gate are made of polysilicon in two stages, the gate polysilicon is higher than that of a normal MO8LSI, and the flow shape of the interlayer insulating film is poor.

[Problem to be solved by the invention]

In the conventional EPROM semiconductor integrated circuit device described above, the flow shape of the interlayer insulating film is poor as shown in FIG. In dry etching when patterning aluminum, there was a risk that aluminum would remain in areas where aluminum should originally be etched, resulting in defects such as short circuits.

Due to such an unstable structure, at the mass production level, variations in the manufacturing process, etc. have caused a decrease in yield.

An object of the present invention is to be able to form a stable flow shape without being affected by manufacturing variations in the interlayer insulating film forming process, and as a result, to improve aluminum sputter coverage in the aluminum wiring forming process. Another object of the present invention is to provide a semiconductor integrated circuit device having a structure in which no unnecessary aluminum remains during aluminum dry etching.

[Means to solve the problem]

The semiconductor integrated circuit device of the present invention includes a first gate oxide film on a plurality of element active regions on one principal surface of a semiconductor substrate, and a first layer of polyester, which becomes a floating gate, formed on the gate oxide film. In a semiconductor integrated M circuit having silicon and a second layer of polysilicon serving as a control gate formed on the second gate oxide film, the above-mentioned first layer floating gate and second layer A normal pressure CVD insulating film is provided on both sides of the control gate as a sidewall to improve the flow shape of the interlayer insulating film, and the first layer of floating gate, second layer of control gate and sidewall are formed. A normal pressure CVD insulating film as an interlayer insulating film on the surface of the semiconductor substrate,
The structure is characterized in that a thin silicon nitride film and an atmospheric pressure CVD insulating film are formed.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1<a) and (b) are EPROMs of one embodiment of the present invention.
FIG. 3 is a cross-sectional view showing the steps of the semiconductor integrated circuit device.

As shown in FIG. 1(a), a gate oxide film 2 is formed on a P-type silicon substrate 1 by the same process as in the conventional method, and then a floating gate 3. Second gate oxide film 4. After patterning the control gate 5 and forming a polysilicon oxide film 6, an N+ layer 7 is implanted by arsenic ion implantation.
A CVD oxide film, which is to become a zero-order sidewall, is grown over the entire surface of the wafer. At this time, the thickness of the CVD oxide film is thicker in the step part of the control gate than in the flat part, so if anisotropic etching is performed by the thickness of the flat part, the desired thickness will be formed on both sides of the floating gate and the control gate. 0-order BPSGg9. on which CVD oxide film sidewalls are formed. Silicon oxide film 10.
The entire BPSG film 11 is made 11.

FIG. 1(b) is a cross-sectional view after patterning the aluminum wiring 12. Since the reflow shape of the interlayer insulating film is good, no aluminum remains and the etching is performed without any problem.

〔Effect of the invention〕

As explained above, conventional EPROM semiconductor integrated circuits have two layers of polysilicon as floating gates and control gates, so ordinary MO3LSI
However, in the present invention, CVD oxide film sidewalls are formed on both sides of the floating gate and control gate, so that the interlayer insulation film forming process is not as high as the gate polysilicon. It is not affected by variations and can form stable flow shapes. This has the effect that it is possible to improve the coverage of aluminum sputtering in the step of forming aluminum wiring, and it is also possible to solve the problem of unnecessary aluminum remaining during aluminum dry etching.

[Brief explanation of drawings]

FIGS. 1(a) and 1(b) are process sectional views of an embodiment of the present invention, and FIGS. 2(a) and 2(b) are process sectional views of an example of a conventional semiconductor integrated circuit device. 1...P-type silicon substrate, 2...gate oxide film, 3
...Floating gate, 4...Second gate oxide film, 5...Control gate, 6...Polysilicon oxide film, 7...N+ layer, 8...CVD oxide film (side wall) , 9.11... BPSGM, 10...
Silicon nitride film, 12... Aluminum wiring, 13...
・Remaining aluminum.

Claims (1)

[Claims] a first gate oxide film formed on a plurality of device active regions on one main surface of a semiconductor substrate; a first layer of polysilicon forming a floating gate formed on the first gate oxide film; A semiconductor integrated circuit having a second gate oxide film formed on the first layer polysilicon, and a second layer polysilicon serving as a control gate formed on the second gate oxide film. In the device, an atmospheric pressure CVD insulating film is provided as a tapered sidewall formed on both sides of the first layer floating gate and the second layer control gate, and the first layer floating gate A normal pressure CVD insulating film as an interlayer insulating film, a thin silicon nitride film, and a normal pressure CVD insulating film are formed on the surface of the semiconductor substrate on which the gate, second-layer control gate, and sidewalls are formed. Features of semiconductor integrated circuit devices.