JP3132847B2 - Method for manufacturing semiconductor device - Google Patents

Method for manufacturing semiconductor device

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Publication number
JP3132847B2
JP3132847B2 JP03153283A JP15328391A JP3132847B2 JP 3132847 B2 JP3132847 B2 JP 3132847B2 JP 03153283 A JP03153283 A JP 03153283A JP 15328391 A JP15328391 A JP 15328391A JP 3132847 B2 JP3132847 B2 JP 3132847B2
Authority
JP
Japan
Prior art keywords
element isolation
nitride film
silicon nitride
semiconductor substrate
insulating film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP03153283A
Other languages
Japanese (ja)
Other versions
JPH053248A (en
Inventor
俊 保坂
Original Assignee
セイコーインスツルメンツ株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by セイコーインスツルメンツ株式会社 filed Critical セイコーインスツルメンツ株式会社
Priority to JP03153283A priority Critical patent/JP3132847B2/en
Publication of JPH053248A publication Critical patent/JPH053248A/en
Application granted granted Critical
Publication of JP3132847B2 publication Critical patent/JP3132847B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【産業上の利用分野】この発明は、半導体装置の素子分
離層の作成方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming an element isolation layer of a semiconductor device.

【0002】[0002]

【従来の技術】従来の素子分離層は、図2に示すように
素子分離層23、反転防止層22および不純物拡散層2
4は半導体表面21に平面的に形成されており、素子分
離領域として一定の距離・面積を有していた。
2. Description of the Related Art As shown in FIG. 2, a conventional element isolation layer includes an element isolation layer 23, an inversion prevention layer 22, and an
Reference numeral 4 is formed in a plane on the semiconductor surface 21 and has a certain distance and area as an element isolation region.

【0003】[0003]

【発明が解決しようとする課題】上述したように、従来
の素子分離層は半導体の平面に素子分離領域として一定
の距離、面積を有しているため、半導体装置の微細化、
高集積化の妨げとなっていた。
As described above, the conventional device isolation layer has a certain distance and area as a device isolation region on the plane of the semiconductor, so that the size of the semiconductor device can be reduced.
This hindered high integration.

【0004】[0004]

【課題を解決するための手段】半導体基板表面に段差を
形成し、その段差に素子分離領域を形成する。
A step is formed on the surface of a semiconductor substrate, and an element isolation region is formed on the step.

【0005】[0005]

【作用】段差を素子分離領域として利用するので、平面
的(マスク上)には素子分離領域を小さくできる。また
自己整合的に素子分離領域を形成し、素子分離層の厚み
まで素子分離領域を小さくできる。
Since the step is used as the element isolation region, the element isolation region can be reduced in plan (on the mask). Further, the element isolation region is formed in a self-aligned manner, and the element isolation region can be reduced to the thickness of the element isolation layer.

【0006】[0006]

【実施例】以下に、本発明の不揮発性半導体メモリの製
造方法の実施例を図面に基づいて詳細に説明する。はじ
めに図1(a)に示すように半導体基板1にフォトレジ
スト2等でパターニングを行う。半導体基板1は、シリ
コン、ゲルマニウム等の単一半導体基板あるいはガリウ
ム砒素(GaAs)、インジウムリン等の化合物半導体
基板あるいは一般的な半導体基板をさす。
DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the method for manufacturing a nonvolatile semiconductor memory according to the present invention will be described below in detail with reference to the drawings. First, as shown in FIG. 1A, a semiconductor substrate 1 is patterned with a photoresist 2 or the like. The semiconductor substrate 1 refers to a single semiconductor substrate such as silicon or germanium, a compound semiconductor substrate such as gallium arsenide (GaAs), indium phosphide, or a general semiconductor substrate.

【0007】次に図1(b)に示すように、フォトレジ
スト2等でパターニングされた領域3の半導体基板1を
エッチングする。この半導体基板1の深さが本発明にお
ける素子分離幅となる。半導体基板1のエッチング方法
として、ドライエッチング法とウエットエッチング法が
ある。前述したように半導体基板1のエッチング量は素
子分離幅から決定される。
Next, as shown in FIG. 1B, the semiconductor substrate 1 in a region 3 patterned with a photoresist 2 or the like is etched. The depth of the semiconductor substrate 1 is the element isolation width in the present invention. As a method of etching the semiconductor substrate 1, there are a dry etching method and a wet etching method. As described above, the etching amount of the semiconductor substrate 1 is determined from the element isolation width.

【0008】次にフォトレジスト等を除去した後に、図
1(c)に示すように絶縁膜4を薄く形成した後、シリ
コン窒化膜5を積層する。絶縁膜4はシリコン酸化膜や
シリコン酸窒化膜等の絶縁膜である。この絶縁膜4の厚
みは100〜1000Åの間にあることが望ましい。シ
リコン窒化膜5は耐酸化性マスクとなるものである。従
って耐酸化性の材料であれば、シリコン窒化膜でなくて
もよい。またシリコン窒化膜5の厚みはピンホールがな
く、しかも耐酸化性があれば充分であり、通常は200
〜10000Åである。シリコン窒化膜5の形成方法と
して化学気相成長法(CVD法)あるいは物理気相成長
法(PVD法)がある。
Next, after removing the photoresist and the like, an insulating film 4 is formed thin as shown in FIG. 1C, and a silicon nitride film 5 is laminated. The insulating film 4 is an insulating film such as a silicon oxide film or a silicon oxynitride film. Desirably, the thickness of the insulating film 4 is between 100 and 1000 degrees. The silicon nitride film 5 serves as an oxidation resistant mask. Therefore, the material may not be a silicon nitride film as long as it is an oxidation resistant material. It is sufficient that the silicon nitride film 5 has no pinholes and has oxidation resistance.
〜1010000Å. As a method for forming the silicon nitride film 5, there is a chemical vapor deposition method (CVD method) or a physical vapor deposition method (PVD method).

【0009】CVD法あるいはPVD法で形成したシリ
コン窒化膜5において、段差部に積層した膜は平坦部に
積層した膜に比較し弱く、図1(d)に示すようにエッ
チングを行うと段差部の膜が速く除去され、シリコン窒
化膜5のない領域6が段差部に形成される。このエッチ
ングの方法として、異方性エッチングより等方性エッチ
ングの方が効果が大きい。つまり、ウエットエッチング
あるいは等方性のドライエッチングを行うことにより、
平坦部のシリコン窒化膜を残し、段差部のシリコン窒化
膜のみをエッチングすることができる。特にシリコン窒
化膜5がプラズマCVDやスパッタ法で形成した場合、
段差部の膜質が特に弱いので上記の方法が効果的に作用
する。
In the silicon nitride film 5 formed by the CVD method or the PVD method, the film laminated on the stepped portion is weaker than the film laminated on the flat portion. Is quickly removed, and the region 6 without the silicon nitride film 5 is formed at the step. As an etching method, isotropic etching is more effective than anisotropic etching. In other words, by performing wet etching or isotropic dry etching,
The silicon nitride film in the flat portion is left, and only the silicon nitride film in the step portion can be etched. In particular, when the silicon nitride film 5 is formed by plasma CVD or sputtering,
Since the film quality of the step portion is particularly weak, the above method works effectively.

【0010】次に図1(e)に示すように、段差部のシ
リコン窒化膜5の除去された領域にフィールドの反転防
止のための不純物を導入し反転防止層7を形成する。こ
の不純物元素の導入の方法としてイオン注入法や拡散法
がある。次に図1(f)に示すように、半導体基板1を
酸化して、シリコン窒化膜5のない段差部の領域6に素
子分離用の絶縁膜8を形成する。基板がシリコンの場
合、素子分離用の絶縁膜8はシリコン酸化膜となる。
Next, as shown in FIG. 1E, an impurity for preventing field inversion is introduced into the region where the silicon nitride film 5 at the step is removed to form an inversion prevention layer 7. As a method for introducing the impurity element, there are an ion implantation method and a diffusion method. Next, as shown in FIG. 1F, the semiconductor substrate 1 is oxidized to form an insulating film 8 for element isolation in the step region 6 where no silicon nitride film 5 exists. When the substrate is silicon, the insulating film 8 for element isolation becomes a silicon oxide film.

【0011】次に、シリコン窒化膜5および絶縁膜4を
除去し、図1(g)を得る。ここで素子分離絶縁膜8で
覆われていない領域は活性領域となる。この活性領域に
各種の不純物拡散層やトランジスタ等が形成される。例
えば、図2に示すように薄い絶縁膜9を形成した後、イ
オン注入等の方法により不純物拡散層10を形成する。
この後にトランジスタや配線や保護膜が形成され半導体
デバイスが完成する。
Next, the silicon nitride film 5 and the insulating film 4 are removed to obtain FIG. Here, the region not covered with the element isolation insulating film 8 is an active region. Various impurity diffusion layers, transistors and the like are formed in this active region. For example, after forming a thin insulating film 9 as shown in FIG. 2, an impurity diffusion layer 10 is formed by a method such as ion implantation.
Thereafter, a transistor, a wiring, and a protective film are formed to complete a semiconductor device.

【0012】[0012]

【発明の効果】以上説明したように、本発明の半導体装
置の製造方法によれば半導体基板の表面に形成された段
差に素子分離領域を形成できるので、素子分離層の幅お
よび面積を小さくできる。特に平面的には素子分離層の
幅は素子分離層の厚みまで小さくできる。さらに自己整
合的に段差部分に素子分離領域を形成できる。従って、
半導体装置の微細化、高集積化には最高の効果がある。
As described above, according to the method of manufacturing a semiconductor device of the present invention, an element isolation region can be formed at a step formed on the surface of a semiconductor substrate, so that the width and area of an element isolation layer can be reduced. . In particular, in plan view, the width of the element isolation layer can be reduced to the thickness of the element isolation layer. Further, an element isolation region can be formed in a step portion in a self-aligned manner. Therefore,
The greatest effect is achieved for miniaturization and high integration of semiconductor devices.

【図面の簡単な説明】[Brief description of the drawings]

【図1】(a)〜(g)は本発明の実施例を示す半導体
装置の工程順断面図である。
FIGS. 1A to 1G are cross-sectional views illustrating a semiconductor device according to an embodiment of the present invention in the order of steps; FIGS.

【図2】本発明の半導体装置のできあがり図である。FIG. 2 is a completed diagram of the semiconductor device of the present invention.

【図3】従来の半導体装置の素子分離を示す断面図であ
る。
FIG. 3 is a sectional view showing element isolation of a conventional semiconductor device.

【符号の説明】[Explanation of symbols]

1 半導体基板 2 フォトレジスト 4 絶縁膜 5 シリコン窒化膜 7 反転防止層 8 素子分離絶縁膜 10 不純物拡散層 DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 Photoresist 4 Insulating film 5 Silicon nitride film 7 Inversion prevention layer 8 Element isolation insulating film 10 Impurity diffusion layer

Claims (1)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】 半導体基板の表面にフォトレジストをパ
ターニングして形成し、前記半導体基板の表面を段差部
を有する所望の形状にエッチングする工程と、前記フォ
トレジストを除去した後、前記半導体基板の表面に絶縁
膜を形成する工程と、前記絶縁膜の上にシリコン窒化膜
を形成する工程と、前記シリコン窒化膜を等方性エッチ
ングにより前記段差部に形成されたシリコン窒化膜のみ
を選択的に自己整合的にエッチング除去する工程と、
記段差部を局部的に酸化して素子分離用の絶縁膜を形成
する工程と、前記シリコン窒化膜を除去する工程とから
なることを特徴とする半導体装置の製造方法。
1. A photoresist is coated on the surface of a semiconductor substrate.
And turning the surface of the semiconductor substrate to a stepped portion.
And etching into a desired shape having, after removing the photoresist, forming an insulating film on a surface of the semiconductor substrate, forming a silicon nitride film on the insulating film, the silicon Isotropic etch of nitride film
A step of selectively self etched away only the silicon nitride film formed on the stepped portion by ring, before
A step of locally oxidizing the step portion to form an insulating film for element isolation, and a step of removing the silicon nitride film.
A method for manufacturing a semiconductor device, comprising:
JP03153283A 1991-06-25 1991-06-25 Method for manufacturing semiconductor device Expired - Lifetime JP3132847B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP03153283A JP3132847B2 (en) 1991-06-25 1991-06-25 Method for manufacturing semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP03153283A JP3132847B2 (en) 1991-06-25 1991-06-25 Method for manufacturing semiconductor device

Publications (2)

Publication Number Publication Date
JPH053248A JPH053248A (en) 1993-01-08
JP3132847B2 true JP3132847B2 (en) 2001-02-05

Family

ID=15559090

Family Applications (1)

Application Number Title Priority Date Filing Date
JP03153283A Expired - Lifetime JP3132847B2 (en) 1991-06-25 1991-06-25 Method for manufacturing semiconductor device

Country Status (1)

Country Link
JP (1) JP3132847B2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103665629A (en) * 2012-09-19 2014-03-26 中国石油化工股份有限公司 Flame-retardant plastic shell composition for electric vehicle and preparation method thereof

Also Published As

Publication number Publication date
JPH053248A (en) 1993-01-08

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