JPS6245165A - Manufacture of semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To form a thin film conductive layer easily by a method wherein an impurity, which controls the resistance value of a high melting point metal silicide film, is introduced into a polycrystalline silicide film, composed of a polycrystalline Si film and the high melting point metal silicide film formed on the polycrystalline Si film, and source and drain films. CONSTITUTION:Field oxide films 2 and 4 are channel stopper regions 3 are formed on a substrate 1 and an FET Qm, which composes a memory cell of an EF-ROM, and MISFET's Q1 and Q2, which compose peripheral circuits, are formed between them. A floating gate electrode 5 and a control gate electrode 7 are provided in the FET Qm, the gate electrode 5 is provided in the FET Q1 and the gate electrode 7 is provided in the FET Q2. Among those electrodes, the gate electrode 7 is composed of a polycrystalline silicide film which is composed of a polycrystalline Si film 7A and a high melting point metal silicide film 7B formed on the film 7A and an impurity which controls the resistance value is introduced into the polycrystalline silicide film when the source and drain regions are formed to control the resistance value.

Description

[Detailed Description of the Invention] [Technical Field] The present invention relates to a semiconductor integrated circuit device, and particularly to a semiconductor integrated circuit device having a conductive layer whose resistance value is controlled by diffusion of impurities. It's about technology.

[Background technology] In a semiconductor integrated circuit device having MISFET.

There is a tendency to use a polycide film, in which a refractory metal silicide film is layered on top of a polycrystalline silicon film, as a gate electrode material. This is because the specific resistance value is smaller than that of a single-layer polycrystalline silicon film, so gate and wiring delay times can be shortened.

The polycide film is obtained by thermally diffusing phosphorus to a high concentration into a polycrystalline silicon film in which phosphorus, which controls the resistance value, is not diffused, and forming a high melting point metal silicide film on top of this polycrystalline silicon film. .

The polycide film formed by this method is, for example, 200
0 [polycrystalline silicon film with a film thickness of 3000 [
It is composed of a relatively thick film of high melting point metal silicide film having a film thickness of about λ.

Such a thick polycide film causes the following problems.

(1) Controllability of anisotropic etching is difficult.

(2) During the oxidation process or anisotropic etching, the side portions of the polycide film tend to be formed into an overhanging shape, and etching remains of the upper conductive layer are left in these portions.

Short circuits between conductive layers are likely to occur. Therefore, a side etching step is required to remove the etching residue, resulting in reduced processing dimensional accuracy and difficulty in microfabrication.

(3) Since the step coverage of the upper layer aluminum wiring is deteriorated at the stepped portion of the polycide film, the electrical (y3 reliability) is decreased.

Therefore, it is necessary to reduce the thickness of the polycide film. Since the resistance value is determined by the high melting point metal silicide film, the polycide film must be made thinner by making the polycrystalline silicon film thinner.

Therefore, techniques for thinning polycide films, especially polycrystalline silicon films, are known [IEE Transactions on Electron Devices, Vol. 31, 1].
No. 0 (IEEE Transac 1 on El
ecron Devices, νo1. ED
31. No.10.1984) p1432- ρ1439
). This technology forms a high melting point metal silicide film on top of the polycrystalline silicon film in which phosphorus is not diffused,
Thereafter, phosphorus was introduced into the polycrystalline silicon film through the high melting point metal silicide film by ion implantation, and after patterning, the phosphorus was activated to form a polycide film having a polycrystalline silicon film with a high degree of impurity a. .

The polycide film formed by this technique has the following characteristics.

(1) By forming a high melting point metal silicide film with a low impurity concentration in the polycrystalline silicon film, especially at a low surface concentration, the grain size of the polycrystalline silicon film is small, so the high melting point metal is applied to the grain boundary surface. Diffusion of silicide can be suppressed.

This alleviates mechanical stress and prevents damage and destruction of the gate insulating film used in MISFETs.
Its dielectric strength can be improved.

(2) By reducing the grain size in (1) above, it is possible to suppress the formation of a natural oxide film on the surface of the polycrystalline silicon film, so it is possible to prevent the generation of mechanical stress between the film and the high melting point metal silicide film. Deterioration of adhesion.

It is possible to prevent abnormal reactions from occurring at the joint. Thereby, electrical reliability can be improved.

(3) Since the polycrystalline silicon film and the refractory metal silicide film are patterned before activating the phosphorus, anisotropic etching can be performed while the grain size of the polycrystalline silicon film is small. Thereby, the processing dimensional accuracy of anisotropic etching can be improved.

(4) Since the impurity concentration of the polycrystalline silicon film can be made high when the polycide film is completed, the work function Φms in the MO3 structure can be stabilized. This allows MISFE
The controllability of the threshold voltage of T can be improved.

(5) When forming the high melting point metal silicide film and patterning, the impurity concentration of the polycrystalline silicon film was formed at a low concentration, and when completed, the impurity concentration of the polycrystalline silicon film was formed at a high concentration. It can have the characteristics of 1) to (4). That is, the polycrystalline silicon film is
Since it can be formed to a thin film thickness of ~1000 [in],
As a result, the polycide film can be made thinner.

However, as a result of experiments and studies on this technology, the present inventor found a problem in that the manufacturing process for thinning a polycrystalline silicon film could not be sufficiently shortened. Furthermore, when this technique is applied to an ultraviolet erasable nonvolatile memory bag ml (EPROM), the thinning described above is effective.

We found a problem in that the manufacturing process becomes extremely complicated.

[Purpose of the present invention] An object of the present invention is to provide a semiconductor integrated circuit device in which a conductive layer whose resistance value is controlled by diffusion of impurities is made thinner and the number of manufacturing steps is reduced.

Another object of the present invention is to provide a technique that can improve the processing dimensional accuracy of a conductive layer whose resistance value is controlled by impurity concentration and reduce the number of manufacturing steps.

Another object of the present invention is to provide a semiconductor integrated circuit device having an ultraviolet erasable nonvolatile memory function and having a conductive layer whose resistance value is controlled by impurity concentration.

It is an object of the present invention to provide a technique capable of reducing the manufacturing process while reducing the thickness of the groove 11M.

Another object of the present invention is to provide a semiconductor integrated circuit device having an ultraviolet erasable nonvolatile memory function and having a conductive layer whose resistance value is controlled by impurity concentration, by reducing the manufacturing process by reducing the thickness of the conductive layer. Another object of the present invention is to provide a technology that can improve the efficiency of writing and reading information.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Summary of the Invention] A brief overview of typical inventions disclosed in this application is as follows.

That is, in a semiconductor integrated circuit device having a conductive layer whose resistance value is controlled by diffusion of impurities, a high melting point metal silicide film is formed on top of a polycrystalline silicon film in which no impurities are diffused or in which impurities are diffused at a low concentration. A polycide film is formed.

An impurity for controlling the resistance value of the polycrystalline silicon film is introduced into the polycide film and a region other than the polycide film, such as a source region or a drain region of the MISFET.

This allows the polycide film to be made thinner and the number of manufacturing steps to be reduced.

The structure of the present invention will be described below as a semiconductor integrated circuit device (hereinafter referred to as EPRO) equipped with an ultraviolet erasable nonvolatile memory function.
This will be explained along with an example in which the present invention is applied to a computer (referred to as M).

It should be noted that in all the examples, parts having the same functions are given the same reference numerals, and repeated explanations thereof will be omitted.

[Example! ] Example of the present invention! The EPROM shown in FIG. 1 is shown in cross-section.

In FIG. 1, 1 is a P-type semiconductor substrate (or well region) made of single crystal silicon, 2 is a field insulating film, and 3 is a p-type channel stopper region. The field insulating film 2 and the channel stopper region 3 are provided on the upper or main surface of the semiconductor substrate 1 between the semiconductor element formation regions, and are configured to electrically isolate the semiconductor elements.

A field effect transistor Qm constituting a memory cell of an EPROM is constructed as shown on the left side of FIG.

That is, the field effect transistor Qm has a semiconductor substrate 1
, first gate insulating film 4, floating gate electrode 5
．． second gate insulating film 6, control gate electrode 7.
It is composed of a pair of n-type semiconductor regions 8 and a pair of d-type semiconductor regions 11, which constitute source or drain regions.

MISFETQ8, which constitutes the peripheral circuit of EFROM, is
It is constructed as shown in the center of FIG. That is, M I S F E T Q s is the semiconductor substrate 1.
Gate insulating film 4. A pair of n-type semiconductor regions 9 constituting a gate electrode 5, a source or drain region, and a pair of n-type semiconductor regions 9
It is composed of a type semiconductor region 11.

Other MISFE T constituting the peripheral circuit of EPROM
Q2 is constructed as shown on the right side of FIG. That is, the 1Mr 5FETQ2 has a semiconductor substrate 1. It is composed of a gate insulating film 6, a gate electrode 7, a pair of n-type semiconductor regions 9 and a pair of rl'-type semiconductor regions 11 that constitute a source or drain region.

The gate electrode 5 is made of, for example, a polycrystalline silicon film whose resistance value is controlled by diffusing phosphorus (or arsenic) at a high concentration.

The gate electrode 7 is configured integrally with a word line extending in a predetermined direction. This gate electrode 7.

For example, a high melting point metal silicide (MoS
is, Ta5iz, TiSi2. WSi2) fXI
It is composed of a polycide film provided with A7B. In addition to the polycide film, the gate electrode 7 is made of a single-layer single-crystalline, non-crystalline (amorphous) or polycrystalline silicon film,
Alternatively, it may be composed of a composite film with a high melting point metal film provided thereon.

The semiconductor regions 8 and 9 are LDD (lightly doped)
edDrai, n) structure, and is provided on the main surface of the semiconductor substrate 1 between the semiconductor region 11 used as a source region or a drain region and a channel formation region. The semiconductor region 8 of the field effect transistor Qm has a higher impurity concentration than the semiconductor region 9 of the MISFET Q+, Q2. This patent application was previously filed by the applicant in 1983.
M I 5FE as described in No.-102555
Compared to TQ+ and Q2, the electric field strength near the drain region (semiconductor region 11) of the field effect transistor Qm is increased.

Constructed to improve the information writing efficiency (electron injection efficiency) and reduce the resistance value of the semiconductor region 8 (LDD section) to improve the reading efficiency (preventing a decrease in gm of the memory cell) has been done.

Further, since the semiconductor region 8 forms a pn junction with the semiconductor substrate 1 having a higher impurity concentration than the semiconductor region 9, the extension of the depletion region formed on the channel formation region side can be suppressed. That is, the short channel effect can be suppressed and the area occupied by the field effect transistor Qm can be reduced. The semiconductor region 9 has an optimum impurity concentration to suppress the generation of hot carriers in the MISFETs Q+ and Q2.

That is, the impurity concentration of each of semiconductor regions 8 and 9 can be optimized.

Reference numeral 10 denotes impurity introduction masks provided on both sides of the gate insulating films 5 and 7, which constitute the LDD structure field effect transistor Qm and the MI 5FETs Ql and Q2.

12 is an insulating film that covers semiconductor elements such as the field effect transistor Qm, and 13 is an insulating film 1 above a predetermined semiconductor region 11.
This is a connection hole provided by removing 2.

A conductive layer 14 is provided on the insulating film 12 so as to be electrically connected to a predetermined semiconductor region 11 through a contact hole 12 and to extend in a predetermined direction. Conductive layer 14 within the memory cell array, ie.

The conductive layer 14 connected to the field effect transistor Qm is
It extends in a predetermined direction intersecting the word line and forms a data line DL or a source line SL.

Next, a method of manufacturing the EPROM configured as described above will be explained.

A method for manufacturing an EPROM, which is Embodiment I of the present invention, is shown in cross-sectional views at each manufacturing step in FIGS. 2 to 8.

First, a p'' type semiconductor substrate 1 is prepared, and a field insulating film (SiO2 film) 2 and a p''
A channel stopper region 3 of the mold is formed.

After this, as shown in FIG.
m and M I S F E T Q 1. A first gate insulating film 4 is formed on the upper main surface of the semiconductor substrate 1 in the Q2 formation region. The gate insulating film 4 is formed of, for example, a silicon oxide film formed by thermal oxidation technology.

After the step of forming the gate insulating film 4 shown in FIG. 2, a first layer of polycrystalline silicon film in which no impurity for controlling the resistance value is diffused or a low concentration impurity is diffused is deposited on the entire surface by CVD. Form.

Phosphorus (or arsenic) is then thermally diffused into this polycrystalline silicon film at a high impurity concentration to reduce its resistance value. Note that as the first conductive layer, a single crystal silicon film or an amorphous silicon film may be used instead of the polycrystalline silicon film.

Thereafter, the polycrystalline silicon film is patterned in a predetermined manner to form a conductive layer 5A that will form a floating gate electrode in the field effect transistor Qm formation region.
A gate electrode 5 is formed in the I S F E T Q I formation region. With this patterning.

When the polycrystalline silicon film is removed, the gate insulating film 4 formed under it is also removed. M
Since the ISFET QI has electrodes made of polycrystalline silicon and an insulating film 4 that is thicker than an insulating film 6 to be described later, it is used as, for example, a high breakdown voltage MISFET.

As shown in FIG. 3, the conductive layer 5A,
A second gate insulator [6 is formed to cover the semiconductor substrate 1 in the gate electrode 5 and MISFET Q 2 forming region. For the gate insulating film 6, for example, a silicon oxide film formed by thermal oxidation technology is used. In addition.

Polycrystalline silicon film 5. The oxide film 6 on the SA is thicker than the oxide film 6 on the surface of the substrate 1.

After the step of forming the gate insulating film 6 shown in FIG. 3, a second step is performed to form a gate electrode, as shown in FIG.
A layer of polycide [7C is formed on the entire surface. In the polycide ITIA 7C, a high melting point metal silicide film 7B is formed on a polycrystalline silicon film 7A in which no impurity for controlling the resistance value is diffused or a low concentration impurity is diffused.

The polycrystalline silicon film 7A is formed by, for example, CVD technology,
It is formed to have a thin film thickness of approximately 500 to 500 cλ.

The high melting point metal silicide film 7B, for example, a tungsten silicide film, is formed by sputtering technology, CVD technology, etc.
It is formed with a film thickness of about 500 to 3500 [λ]. In addition, in the polycide film 7C, the polycrystalline silicon film 7A
Instead, a single crystal silicon film or an amorphous silicon film may be used.

In this way, impurities (phosphorus or arsenic) that control the resistance value
By forming a high melting point metal silicide film 7B on top of a polycrystalline silicon film 7A in which impurities are not diffused or low concentration impurities are diffused.

Since the grain size, especially in the surface portion of the polycrystalline silicon film 7A, is small, it is possible to suppress diffusion of refractory metal silicide to the grain boundary surface.

As a result, the mechanical stress caused by the diffusion of the high melting point metal silicide is relaxed, and the field effect transistor Qm and MISFET Q2 existing under the polycide film 7C
Since damage and destruction of the gate insulating film 6 can be prevented, its dielectric strength voltage can be increased.

In addition, the grain size is small, and the polycrystalline silicon film 7A
Since it is possible to suppress the formation of a natural oxide film on the surface of the polycrystalline silicon film 7A and the high melting point metal silicide film 7,
It is possible to prevent the occurrence of mechanical stress, deterioration of adhesion, and abnormal reaction at the bonded portion. by this,
The electrical reliability of the polycide film 7C can be improved.

After the step of forming the polycide film 7C shown in FIG.
Polycide M7C in memory cell array.

The conductive layer 5A is patterned to form the floating gate electrode 5 and control gate electrode 7 (and word line) of the field effect transistor Qm. This patterning is performed with the MISFET Ql and Q2 formation regions, that is, the peripheral circuit of the memory cell, covered with a resist mask.

The polycide film 7C of the peripheral circuit remains as it is.

This patterning is done in order to increase the precision of processing dimensions.
This is done using an anisotropic etching technique such as reactive ion etching.

In this way, the grain size of the polycrystalline silicon film 7A can be changed by applying anisotropic etching technology to the polycrystalline silicon film 7A in which the impurity that controls the resistance value is not diffused or in which the impurity at a low concentration is diffused. Since the processing is performed in a small state, the influence is small and the gate electrode 7 (
It is possible to improve the processing dimensional accuracy of polycide film).

After this, as shown in FIG. 5, gate 1M!
Polycrystalline silicon film 7 of pole 7 and polycide 1Ilu7c
Phosphorus (or arsenic) 7D, which reduces the resistance value of A, is introduced over the entire surface. Since this phosphor D is introduced by ion implantation technology, it is also introduced through the gate insulating film 4 into the main surface of the semiconductor substrate 1 in the source region or train region forming region of the field effect transistor Qm in the memory cell array.

This phosphor D is introduced in a self-aligned manner to the gate +-m pole 7, and the L of the L D D 41j structure of the transistor Qm is
A DD portion is formed.

The phosphor D is preferably introduced so that the maximum impurity concentration (peak impurity concentration) is distributed on the gate electrode 7 and the high melting point metal silicide film 7B side of the polycide film 7C. This suppresses the leakage of the phosphor D into the semiconductor substrate 1 and improves the controllability of the threshold voltage in the MIS structure.
1 is to do 6 again. The phosphor D is formed on the gate electrode 7 and the polycide film 7C in advance by forming a layer, for example, a CV
A silicon oxide film formed by technique D may be formed in advance, and the silicon oxide film may be introduced into the gate electrode 7 and the polycide film 7C through this silicon oxide film.

In this way, the phosphor D that controls the resistance value is connected to the gate electrode 7.
and the polycide film 7C (M I S FET Q2 formation region), and also into the main surface portion of the semiconductor substrate 1 below them (field effect transistor Qm formation region), thereby increasing the LD of the field effect transistor Qm.
Since there is no need for an impurity introduction step to form the D portion, the number of manufacturing steps can be reduced.

Further, by forming the polycide film 7C so as to cover the M I 5FET QI formation region of the peripheral circuit, phosphor D is not introduced into the gate electrode 5 and the main surface portion of the semiconductor substrate 1. That is, the polycide film 7C
is M i S F E T Q r .

In the Q2 formation region (peripheral circuit region), an impurity introduction mask is formed.

After the step of introducing the phosphor D shown in FIG. 5, the polycide film 7C of the peripheral circuit is patterned, and the MISF
A gate electrode 7 is formed in the ETQ2 formation region. Patterning is performed using an anisotropic etching technique such as reactive ion etching in order to improve the precision of processing dimensions. Since the MISFE TQ 2 has a gate electrode made of a polycide film, it is used, for example, as a high-speed MISFE'.

This patterning is similar to the field effect transistor Q described above.
Similarly to the patterning in the m formation region, by applying an anisotropic etching technique to the polycrystalline silicon film 7A, even if the phosphor D is introduced, it is not activated and the grain size of the polycrystalline silicon film 7A is reduced. Processing is done in a small state.

Since this influence is small, the processing precision of the gate electrode 7 can be improved.

Thereafter, as shown in FIG.
Polycrystalline silicon film 7 with high impurity concentration diffused into A
Form A. At the same time, the phosphor D introduced into the semiconductor substrate 1 is stretched and diffused to form an n-type semiconductor region 8 that will become the LDD portion of the field effect transistor Qrn.

Polycrystalline silicon film 7 with high impurity concentration shown in FIG.
After the step of forming A and the semiconductor region 8, mainly,
M I S F E T Q 1. An n-type semiconductor region 9, which will become an LDD section, is formed on the main surface of the semiconductor substrate 1 in the source region or drain region formation region of Q2. The semiconductor region 9 is formed with a lower impurity concentration than the semiconductor region 8. This semiconductor region 9 is formed by introducing phosphorus (or arsenic) using an ion implantation technique and then performing stretching and diffusion. The phosphorus forming the semiconductor region 9 is used to mask the semiconductor region 8 with an impurity introduction mask (for example,
It may be covered with a resist film (resist film) to prevent introduction, or it may be introduced into the semiconductor region 8. This is because the impurity concentration of the semiconductor region 8 is determined in the step of introducing the phosphor D shown in FIG.

After the step of forming the semiconductor region 9 shown in FIG. 7, impurity doping is formed on both sides of the gate electrodes 5 and 7 in self-alignment to form a substantial source or drain region. Form mask 0. This impurity introduction mask 10 is as follows.

For example, it is formed by performing reactive ion etching on a silicon oxide film formed over the entire surface of a substrate using CVD technology.

Thereafter, in the step of forming the impurity introduction mask 10, the insulating films 4 and 6 on the semiconductor regions 8 and 9 are removed, and a new insulating film 10A is formed in these parts. Insulating film 10A
is formed mainly for the purpose of preventing contamination by a buffer layer and heavy metal when introducing impurities to form a source region or a drain region.

Mainly, the field insulating film 2, the gate electrode 5
, 7 and the impurity introduction mask 10 as a mask,
As shown in FIG. 8, an n-type semiconductor region 11, which is used as a substantial source or drain region, is formed on the main surface of the semiconductor substrate 1.

The semiconductor region 11 and the semiconductor regions 8 and 9 are formed in self-alignment with respect to the gate electrodes 5 and 7.

In this step of forming the semiconductor region 11, the field effect transistor Qm and the M I 5FETQ+, Q2 are completed.

In this way, the gate electrode 7 is connected to the field effect transistor Q
By forming the polycrystalline silicon film 7A with a high impurity concentration when completing the M and M T 5FETQ+, Q2, the work function Φms in the MIS structure is stabilized, so the controllability of their threshold voltages can be improved. .

According to the above explanation, the high melting point metal silicide film 7
During the step of forming B and the step of patterning the polycide film 7C, a low concentration is applied to the field effect transistor Q.
m and MI 5FETQ+.

When Q2 was completed, the gate electrode 7 was formed using a polycrystalline silicon film 7A with a high impurity concentration, so the polycrystalline silicon film 7A of the gate electrode 7 (polycide film) was heated by 500 to 1000 people as described above. It can be formed with a moderate thickness.

Furthermore, since the gate electrode 7 can be made thinner, the controllability of anisotropic etching becomes better.

In addition, by making the gate electrode 7 thinner, it is possible to reduce the overhang shape on the sides and prevent the formation of two-notch residues in this part, so there is no need for processes such as side etching, and the processing dimensional accuracy can be improved. can be improved.

Also, by making the gate electrode 7 thinner.

Since the step shape caused by the gate electrode 7 can be relaxed, step coverage of 1ffi aluminum wiring or the like can be improved and electrical reliability can be improved.

After the step of forming the semiconductor region 11 shown in FIG. 8, an insulating film 12 and a connection hole 13 are formed, and then the first
As shown in the figure, a conductive layer 14 made of aluminum or the like is formed.

By performing these series of manufacturing steps, the EPROM of Example I is completed.

Note that the present invention relates to the lymph D shown in FIG. 6 of the first embodiment.
The step of activating may be performed in the step of forming the semiconductor region 9 shown in FIG. 7 or the step of forming the semiconductor region 11 shown in FIG. 8.

[Embodiment 2] Embodiment 2 is another embodiment in which the present invention is applied to an EFROM having a conductive layer in which a refractory metal silicide film is selectively formed on a patterned polycrystalline silicon film.

An EPROM which is Embodiment 2 of the present invention is shown in a sectional view in FIG.

The EPROM of this embodiment (2) is constructed as shown in FIG. That is, the gate electrode 7 of the field effect transistor Qm. Gate electrode 5 and M of MI S FETQ+
The gate electrode 7 of ISFETQ2 is made of polycrystalline silicon film 7.
A high melting point metal silicide film 7B selectively formed on top of A or 5A is provided. Furthermore, field effect transistor Qm, MI 5FETQ+ and M I S
A selectively formed refractory metal silicide film 7B is provided on the surface of the semiconductor region 11 used as the source region or train region of the FETQ2.

In the EPROM configured in this way, the gate electrode 5,
Since the resistance value of the semiconductor region 7 and the semiconductor region 8 used as a substantial source region or train region can be reduced, the operating speed can be increased.

Next, a method of manufacturing the EPROM configured as described above will be explained.

The method for manufacturing an EPROM, which is Embodiment 1 of the present invention, was
It is shown in cross-sectional views at each manufacturing process in FIGS.

After the step of forming the gate insulating film 6 shown in FIG. 3 of Example I, as shown in FIG. to form. In the polycrystalline silicon film 7A, no impurity for controlling the resistance value is diffused, or a low concentration impurity is diffused.

After the step of forming the polycrystalline silicon 1 (17A) shown in FIG.
, 7A to form floating gate electrodes 5 and control gate electrodes 7 of field effects 1 to transistors Qm.

As in Example I, an anisotropic etching technique is applied to the polycrystalline silicon film 7A in which no impurity for controlling the resistance value is diffused or a low concentration impurity is diffused into the polycrystalline silicon film 7A. Processing is carried out with fm having a small grain size.

Since this influence is small, the processing precision of the gate electrode 7 can be improved.

As shown in FIG. 11, similar to the step shown in FIG. 5 of Example I, phosphorus ( or arsenic) 7D. By introducing this lymph D, substantially the same effect as in Example I can be obtained.

After the step of introducing lymph D shown in FIG.

The polycrystalline silicon film 7A of the peripheral circuit is patterned to form the gate electrode 7 in the MISFETQ2 formation region. Patterning is used to increase processing dimensional accuracy.
This is done using an anisotropic etching technique such as reactive ion etching.

In this pattern Jung 1, similar to the patterning in the field effect transistor 0m formation region described above, by applying an anisotropic etching technique to the polycrystalline silicon film 7A, even if phosphor D is introduced, it is not activated. figure,
Processing is performed in a state where the grain size of the polycrystalline silicon film 7A is small, and the influence thereof is small, so that the processing dimensional accuracy of the gate electrode 7 can be improved.

After this, as shown in FIG. 12, heat treatment is performed to activate the phosphor D, and the gate electrode 7 and LD with high impurity concentration are
An n-type semiconductor region 8 that will become part D is formed.

Gate voltage tlii7 and semiconductor region vj shown in FIG.
After the step of forming 8, MI
An n- type semiconductor region 9 is formed on the main surface of the semiconductor substrate 1 in the 5FET Q+ and Q2 forming region.

And the gate? Impurity introduction masks 1O are formed on both sides of t15.7. In the step of forming this impurity introduction mask 10, the other portions of the insulating films 4 and 6 are removed, and the surface portions of the goo 1-2t electrodes 5 and 7 and the semiconductor region 11 are exposed.

After that, a high melting point metal film is formed on the entire surface, impurity implantation is performed to form a substantial source or drain region, and heat treatment is performed, so that the exposed silicon and the high melting point metal are combined. , a high melting point metal silicide film 7B is partially formed. After implanting impurities to substantially form the source region or drain region, a high melting point metal may be formed over the entire surface. By removing the uncombined high melting point metal film, the gate voltage If! is removed as shown in FIG. A high melting point metal silicide film 7B is selectively formed on the top of the semiconductor region 5.7 and the top of the semiconductor region 8.

By forming this high melting point metal silicide film 7B, field effect transistors Qm, MI S FET
QI and MISFETQ2 are almost completed.

After the step of forming the refractory metal silicide film 7B shown in FIG. 13, the insulating film 12. A contact hole 13 is formed, and then, as shown in FIG. 9, a conductive layer 14 of aluminum or the like is formed.

By performing these series of manufacturing steps, the EFROM of Example 2 is completed.

In addition, the above-mentioned Example 1. In TI, polycrystalline silicon film 7A
The control of the resistance value and the formation of the semiconductor region 8 which becomes the LDD part were performed by introducing the phosphor D. However, in the present invention, the phosphor D is introduced to control the resistance value of the semiconductor region 8 for direct contact, the semiconductor region for the resistor, etc. may be formed.

Furthermore, the present invention is not limited to simultaneously introducing impurities for controlling the resistance value into the upper layer polycrystalline silicon film 7A and the lower layer semiconductor substrate 1, but also forms two layers of polycrystalline silicon films on the top of the semiconductor substrate. The impurities may be simultaneously introduced into each of these two layers of polycrystalline silicon films.

[Effects] As explained above, according to the new technology disclosed in this application, the following effects can be obtained.

(1) 'I': In the method for manufacturing a conductor integrated circuit device,
A polycide film in which a high melting point metal film or a high melting point metal silicide film is formed on top of a single crystal, amorphous or polycrystalline silicon film in which impurities that control the resistance value are not diffused or low concentration impurities are diffused. 2, by introducing an impurity to control the single crystal, amorphous or polycrystalline silicon film into the polycide film and other parts, a manufacturing process is required to introduce impurities into parts other than the polycide film. Therefore, the polycide film can be made thinner and the number of manufacturing steps can be reduced.

(2) In a method for manufacturing a semiconductor integrated circuit device.

An amorphous or polycrystalline silicon film in which impurities that control the resistance value are not diffused or low-degree impurities are diffused, or a polycide film on which a high melting point metal film or a high melting point total bending silicide film is formed. An impurity for controlling the resistance value is introduced into the amorphous or polycrystalline silicon film and other parts.

Before activating the impurity, a manufacturing process is required in which the impurity is introduced into a portion other than the amorphous, polycrystalline silicon film or polycide film by patterning the amorphous or polycrystalline silicon film or polycide film. Therefore, the number of manufacturing steps can be reduced, and the amorphous or polycrystalline silicon film can be processed with a small grain size, so that the processing dimensional accuracy of the polycide film can be improved.

(3) In an EPROM, it is possible to obtain the same effect as in (1) or (2) above, and in the step of introducing the impurity, the source of the field effect transistor of the memory cell and the MI S FET of the peripheral circuit is Since the impurity concentration of the region or the drain region can be changed, the efficiency of writing and reading information can be improved and the number of manufacturing steps can be reduced.

(4) In EPROM, the same effect as in (1) or (2) above can be obtained, and in the step of introducing the impurity, the amorphous, polycrystalline silicon film or polycide film can be used as a mask for impurity introduction. Since it can be used
Manufacturing steps can be reduced.

Although the inventions made by the present inventors have been specifically explained based on the above embodiments, the present invention is not limited to the above embodiments, and can be modified in various ways without departing from the gist thereof. Of course.

For example, in the above embodiment, M I S F ETQ+
.

Q2 may have a single drain structure. The transistor Qm of the memory cell may also have a single drain structure, and in this case, ions are implanted into the polycide film during ion implantation to form the source and drain regions of the transistor Qm.

In addition, the semiconductor regions formed using the same process as ion implantation into the polycide film are MISFETQs, Q
2 source or drain region or a part thereof (L
DD section). That is, the semiconductor region may constitute an M I S FET of a peripheral circuit outside the memory cell.

In addition, one or both of MI 5FETQ+ and Q2,
It may be a P-channel MISFET;
5FETQ+, P channel MIS in addition to Q2
It may also include an FET. That is, the peripheral circuit of the memory cell may be a complementary MIS circuit. In this case, when implanting ions into the polycide film, P channel M I S
Since the FET can be covered with a polycide film, a mask is not required and there is no additional process. Note that in this case, for example, the n-channel and p-channel MISFETs are each
A P-type well region is formed in the n-type semiconductor substrate and a p-type well region is formed in the n-type semiconductor substrate.

The present invention is also effective for semiconductor devices other than EPROMs.

For example, the source or drain region of the r1 channel or P channel MISFET, or a portion thereof (LDD portion) may be formed using an ion implantation process into the polycide film. When forming n-channel and p-channel MISFETs, the implanted ions are, for example, phosphorus and boron, respectively. Also, n-channel and p-channel MIS
Needless to say, this method is also effective when FETs are formed on the same substrate.

In the various examples described above, a single crystal, amorphous or polycrystalline silicon film may be used instead of the polycide film.

That is, the source and drain regions of the MI S FET are formed using the process of 5 implanting ions into these films. In this case, these films are processed (patterned) by etching, especially anisotropic dry etching, before activating (annealing) the ions implanted in these films.
This is what we do.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view of an EFROM which is a first embodiment of the present invention, and FIGS. 2 to 8 are a cross-sectional view of an EPRO which is a first embodiment of the present invention.
9 is a sectional view of an EPROM which is an embodiment (1) of the present invention, and FIGS. An EP
FIG. 3 is a cross-sectional view of each manufacturing process for explaining a ROM manufacturing method. In the figure, 1... semiconductor substrate, 4, 6... gate insulating film. 5.7... Gate electrode, 7A... Polycrystalline silicon film, 7B... High melting point metal silicide film, 7C... Polycide film, 7D... Phosphorus, 8,9.10... Semiconductor Region, Qm...field effect transistor, QI, Q2...
...MISFET. Agent Patent Attorney Katsuma Ogawa 1. Par-1”h.

Claims (1)

[Claims] 1. In a method for manufacturing a semiconductor integrated circuit device, a first layer made of single crystal, amorphous or polycrystalline silicon whose resistance value is controlled by diffusion of impurities is provided in the first and second regions. A step of forming a second conductive layer, and a single crystal with no impurities diffused or with impurities diffused at a low concentration, on the top of the first conductive layer in the first region, via an insulating film. , a step of forming a second conductive layer in which an amorphous or polycrystalline silicon film, or a high melting point metal film or a high melting point metal silicide film is formed on the amorphous or polycrystalline silicon film; An impurity for controlling the resistance value is introduced into the first conductive layer of the second region, and the impurity concentration of the single crystal, amorphous or polycrystalline silicon film of the second conductive layer is increased to a high concentration. A method of manufacturing a semiconductor integrated circuit device, comprising the steps of: 2. In the step of increasing the impurity concentration of the single crystal, amorphous or polycrystalline silicon film of the second conductive layer, the impurity concentration of the first conductive layer of the second region is simultaneously increased. 2. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein the semiconductor region is formed at a high concentration or a low concentration, or at a portion into which an impurity is introduced. 3. The first conductive layer forms the source region or drain of the MISFET, and the second conductive layer
2. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein a gate electrode, wiring, etc. of a MISFET are formed. 4. The method of manufacturing a semiconductor integrated circuit device according to any one of claims 1 to 3, wherein the impurity for controlling the resistance value is introduced by ion implantation technology. 5. In a method for manufacturing a semiconductor integrated circuit device, a first conductive layer made of single crystal, amorphous or polycrystalline silicon whose resistance value is controlled by diffusion of impurities is formed in the first and second regions. A single crystal, amorphous or polycrystalline silicon film with no impurities diffused or with impurities diffused at a low concentration, or its A step of forming a second conductive layer having a high melting point metal film or a high melting point metal silicide film formed thereon, and a step of removing the second conductive layer in the second region by an etching technique. and introducing an impurity to control the resistance value into the second conductive layer in the first region and the first conductive layer in the second region, and A method for manufacturing a semiconductor integrated circuit device, comprising the step of increasing the impurity concentration of an amorphous or polycrystalline silicon film. 6. The step of increasing the impurity concentration of the amorphous or polycrystalline silicon film of the second conductive layer is at the same time increasing the impurity concentration of the first conductive layer of the second region to a high concentration or 6. The method of manufacturing a semiconductor integrated circuit device according to claim 5, wherein the semiconductor region is formed at a low concentration or in a portion into which an impurity is introduced. 7. The first conductive layer forms the source region or drain region of the MISFET, and the second conductive layer forms the gate electrode, wiring, etc. of the MISFET. A method for manufacturing a semiconductor integrated circuit device according to claim 5. 8. The method of manufacturing a semiconductor integrated circuit device according to any one of claims 5 to 7, wherein the impurity for controlling the resistance value is introduced by ion implantation technology. 9. The method for manufacturing a semiconductor integrated circuit device according to claim 5, wherein the second conductive layer in the second region is removed by an anisotropic etching technique. . 10. A patent characterized in that the second conductive layer in the second region is removed by an etching technique before introducing the impurity or activating the introduced impurity. Each of the methods for manufacturing a semiconductor integrated circuit device according to claims 5 to 9. 11. In a method for manufacturing a semiconductor integrated circuit device having an ultraviolet erasable nonvolatile memory function, the device has a first field effect transistor constituting a memory cell and a second field effect transistor constituting a peripheral circuit. An impurity is not diffused or impurities are formed on the upper main surface of the semiconductor substrate in the first region forming the first field effect transistor and the second region forming the second field effect transistor through an insulating film. forming a conductive layer whose resistance value is controlled by diffusion of impurities diffused at a low concentration; patterning the conductive layer in the first region while the second region is covered; forming a first gate electrode, a first gate electrode, a main surface portion of a semiconductor substrate in a first region, and a second gate electrode;
A method for manufacturing a semiconductor integrated circuit device, comprising the step of introducing an impurity for controlling a resistance value into a conductive layer in a region. 12. Claim 11, wherein the conductive layer is a single crystal, amorphous or polycrystalline silicon film, or a high melting point metal film or a high melting point metal silicide film formed thereon. A method for manufacturing a semiconductor integrated circuit device according to paragraph 1. 13. The conductive layer is characterized in that an impurity for controlling the resistance value is introduced into a single crystal, amorphous or polycrystalline silicon film, and then a high melting point metal or a high melting point metal silicide film is formed on top of the impurity. A method for manufacturing a semiconductor integrated circuit device according to claim 11. 14. According to claim 11, the impurity introduced into the main surface of the semiconductor substrate in the first region constitutes a source region or a drain region of a first field effect transistor. A method of manufacturing the semiconductor integrated circuit device described above. 15. Manufacturing a semiconductor integrated circuit device according to claim 11, wherein the conductive layer in the second region forms a second gate electrode of a second field effect transistor. Method. 16. Claim 11, wherein the conductive layer in the second region is formed by forming an impurity introduction mask to prevent impurities from being introduced into the main surface of the semiconductor substrate.
A method for manufacturing a semiconductor integrated circuit device according to paragraph 1.