JPS62194662A - Manufacture of semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To shorten a process by forming memory cells consisting of MISFETs having offset structure in a mask ROM, introducing an impurity to an offset section for the predetermined memory cell in the memory cells and wiring an information by shaping a memory cell having no offset structure. CONSTITUTION:Field insulating film 2, p-type channel stopper regions 3 and gate insulating films 4 are formed to the main surface of a semiconductor substrate 1, and gate electrodes 5, word lines 5A and source regions and drain regions 6 consisting of n<+> type semiconductor regions 6A are shaped, thus forming an MISFETQ2 having offset structure to which no information is written. Predetermined sections in a layer insulating film 7 are removed to shape connecting holes 8, nd source lines and data lines 9 are formed. A mask 10 for introducing an impurity is used, an n-type impurity 6b is introduced, and activated, and an MISFETQ1 to which an information in written is formed in a process in which semiconductor regions 6B are shaped.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a semiconductor integrated circuit device, and is particularly applicable to a semiconductor integrated circuit device having a read-only nonvolatile memory function (hereinafter referred to as a mask ROM). It is about effective techniques.

[Conventional technology]

In the horizontal mask ROM, memory cells are configured with MISFETs. Memory cell “01”, II
1 zr information is M I S FE in the information writing process.
This is done by changing the threshold voltage of T.

In this type of mask ROM, the information writing process is performed using electronics (ElccLonics May 31
．． +983°p50. The following manufacturing process is used as described in page 51).

First, a MISFET (memory cell) having a first threshold voltage is formed. After that, an interlayer insulating film covering the MISFET is formed, and a data line and a source line (aluminum film) connected to the MISFET are formed. After that, a photo-dissist 1 to a mask is formed in which the channel forming region of the MISFET Tr in which information is to be written is opened. and,
Using this photoresist mask, impurities (boron or phosphorus) are introduced into the channel forming region through the interlayer insulating film and the gate electrode in the opened portions. By introducing this impurity, an MTSFET having a second threshold voltage different from the first threshold voltage is formed, and information is not included. Thereafter, a passivation film is formed to complete the manufacturing process of the mask ROM.

In this mask ROM, information can be written after forming the data lines and source lines, which is the final manufacturing process, so the time required to complete the manufacturing process can be shortened (
Hereinafter, it has a characteristic called shortened address.

[Problem that the invention seeks to solve]

As a result of studies on this technology, the present inventor found that the following problems occur.

The introduction of the impurity for writing information is carried out at an impurity of 200 to 300 [
KeV] Fl, is introduced at a high energy of degrees.

Therefore, a large ion implantation device is required. Further, a double-charged impurity (B'') can be introduced with a low energy of about 100 to 200 [KeV], but since the amount of this double-charged impurity is small, the impurity introduction time becomes long.

Furthermore, when impurities are introduced with high energy, crystal defects are generated in the pn1g junction of the channel forming region, source region, and drain region. Crystal defects in the pn junction portion occur because the opening in the photoresist film is configured to have a larger dimension than the channel forming region in consideration of mask misalignment. These crystal defects cannot be sufficiently recovered because heat treatment can only be performed at a low temperature of about 450 C to prevent the data line made of the aluminum film from melting. Alternatively, leakage current increases at the pn junction surface of the drain region.This leakage current causes an increase in power consumption and latch-up due to a parasitic thyristor.

SUMMARY OF THE INVENTION An object of the present invention is to provide a technique in which it is possible to shorten the manufacturing time and introduce impurities for writing information with low energy in a mask ROM.

Another object of the present invention is to provide a technique that can reduce leakage current due to crystal defects in a mask ROM, thereby reducing power consumption or preventing latch-up.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means for solving problems]

A brief overview of typical inventions disclosed in this application is as follows.

That is, in the mask ROM, M with an offset structure
A memory cell consisting of an ISFET is formed.

Information is written by introducing impurities into the offset portion of a predetermined memory cell among these memory cells to form a memory cell that does not have an offset structure.

[Function] According to the above-mentioned means, since information can be written at the final stage of the manufacturing process after forming the memory cell, it is possible to shorten the processing time and to write information without passing through the gate electrode of the MI 5FET. Since impurities for writing information are introduced into the offset portion, the impurities can be introduced with low energy.

Introduction using low energy can reduce the size of the ion implantation device, shorten the impurity introduction time, and reduce crystal defects.

[Example ■]

Hereinafter, regarding the configuration of the present invention, the present invention will be described as n-channel M
An example will be described in which the present invention is applied to a horizontal mask ROM using a T S FET as a memory cell.

In addition, in the planning of the embodiment, parts having the same functions are given the same reference numerals, and repeated explanations thereof will be omitted.

Example of the present invention! A memory cell array of a horizontal mask ROM is shown in FIG.
A cross section taken along the line is shown in Figure 2. In FIG. 1, insulating films other than the field insulating film provided between each conductive layer are not shown in order to make the structure of this embodiment easier to understand.

In FIG. 1, reference numeral 1 denotes a p-type i conductor substrate (or well region) made of single crystal silicon. Reference numeral 2 represents a field insulating film, and reference numeral 3 represents a p-type channel stopper region, which are configured to electrically isolate the conductive elements.

MISFE T that constitutes the memory cell of mask ROM
QI and Q2 are provided on the main surface of the semiconductor substrate 1 in a region surrounded by the field insulating film 2, respectively.

M I S F E T Q I where information is written
As shown on the right side of FIG. 1 and FIG. It is composed of a source region and a drain region 6. In the semiconductor region 6A, the elements G1 to W3 . It is provided at a position separated from the pole 5 (with an offset portion interposed), and forms an offset structure. The semiconductor region 6B is provided on the outer side of the semiconductor substrate 1 at a so-called offset portion between the semiconductor region 6A and the channel formation region, and is formed by M I S F E '
The configuration is such that r Q + does not have an offset structure. That is, this MISFET Q + is conductive when the word line is at the selection level, and II Ocl
(or 1''') information.

Note that the impurity concentration of the semiconductor region 6B is configured to be lower than that of the semiconductor region 6A.

Lightly Doped
A MIS FET Q + having a Drain) structure may be configured.

Information is not written M I S F E T Q
2 is.

The semiconductor region 6B is not provided in the offset portion, and the source region or drain region 6 is formed by the semiconductor region 6A. The MI 5FETQ2 has a so-called offset structure in which conduction does not occur between the source region and the drain region 6 even if a word line is selected. In other words, M I
In S F E T Q 2, the potential of the source line (for example, O[V]) does not appear on the data line.

It is configured so that it does not substantially change from the precharge potential (for example, 3 [V]) during the read period. That is, this M T S F E T Q 2 is HI
II (or "o"> information).

The gate electrodes 5 of the MISFET Q1 and Q2 are made of polycrystalline silicon films. Further, the gate electrode 5 may be made of, for example, a single layer of high melting point metal silicide (
MoSi2. TiSi2. Ta5iz, WSiz)I
II or high melting point metal (Mo, Ti, Ta
, W) Ill, or a composite film in which it is provided on top of a polycrystalline silicon film.

The gate electrode 5 is connected to other MISFs arranged in the column direction.
It is configured integrally with the gate it pole 5 of E T Q I or Q2, and constitutes a word line (WL) 5A.

The source or drain region 6 of M I S F E T Q I or Q2 in this embodiment is integrated with the source or drain regions 6 of the other three adjacent M I S F E T Q + or Q2. has been done.

Reference numeral 7 designates an interlayer insulating film covering M I S F E T Q + and Q2, 8 a contact hole, and 9 a source line SL or data line vr extending in the row direction. The interlayer insulating film 7 is.

For example, it is composed of a silicon oxide film formed by CVD and a PSA film formed by CVD on top of the silicon oxide film.

A source line (S L) or data line (DI, ) 9 is electrically connected to a predetermined source or drain region 6 through a connection hole 8 . The source line or data IX9 is made of a conductive layer with a low specific resistance value, such as an aluminum film or an aluminum film doped with predetermined impurities. However, it is covered with a passivation film and sealed with resin.

Next, the manufacturing method of this embodiment will be briefly explained.

Embodiment 1 A method for manufacturing a mask ROM according to the first embodiment of the present invention is shown for each manufacturing process in FIGS. 3 to 6 (cross-sectional views).

First, on the main surface of the semiconductor substrate 1 between the semiconductor element formation regions,
Field insulating film 2 and P-type channel stopper region 3
form.

Thereafter, as shown in FIG. 3, a gate insulating film 4 is formed on the main surface of the semiconductor substrate 1 in a region surrounded by the field insulating film 2. The gate insulator 114 is formed of, for example, a silicon oxide film formed by thermal oxidation technology.

After the step of forming the gate insulating film 4 shown in FIG. 3, a gate electrode 5 and a word Aft (WL) 5A (not shown) are formed on a predetermined portion of the gate insulating film 4. The gate electrode 5 and the word line 5Δ are, for example, 2000 to 3000
It is formed of a polycrystalline silicon film with a film thickness of about [ON].

As shown in FIG. 4, a source region and a drain region 6 consisting of an n+ type semiconductor region 6A are provided on the main surface of the semiconductor substrate l on the side of the gate electrode 5 in the memory cell array.
form. The source region and drain region 6 are separated from the gate electrode 5, so that an offset portion is formed in the MISFETQ2. Although not shown in the figure, the source and drain regions 6 are formed by forming an impurity introduction mask covering the gate electrode 5 and introducing n-type impurities by ion implantation.

For n-type impurities, for example, I
[at, oms/cm2]Fi! Use a degree of arsenic. For example, a photoresist film is used as a mask for impurity introduction.

In the step of forming this source region and drain region 6,
A MISFET Q 2 having an offset structure in which no information is written in the memory cell array is formed.

After the step of forming the source region and drain region 6 shown in FIG. 4, an interlayer insulating film 7 covering the MI 5FETQ2 is formed. For example, the glabella insulating film 7 is 1.

It is formed with a film thickness of about 4500 [λ].

Thereafter, a predetermined portion of the glabella insulating film 7 is removed to form a connection hole 8, and as shown in FIG. form. The source line and data 1/lA9 are formed of, for example, an aluminum film.

After the step of forming the source line and data line 9 shown in FIG.
An impurity introduction mask lo is formed on the interlayer insulating film 7 to cover the offset portion of the ISFETQ2. The impurity introduction mask 1o is formed in a region indicated by the symbol 1O in FIG. 1 and surrounded by a dashed line. The impurity introduction mask IO is formed of, for example, a photoresist film.

Then, using the impurity introduction mask 10, as shown in FIG.
An n-type impurity 6b is introduced through the gate insulating film 17 and the gate insulating film 4. This impurity 6b is, for example, lXl0'' [
atoIls/cm"] of arsenic (or phosphorus),
It is introduced by ion implantation with low energy of about 150 to 200 [KeV]. At this time, impurity 6b is not introduced into the channel forming region through gate electrode 5.

Then, by activating the introduced impurity 6b, a semiconductor region 6B constituting the source region and drain region 6 is formed as shown in FIG. 2. In the step of forming this semiconductor region 6B, the M
I S F E T Q + is formed.

In this way, an offset structure M I S F r': TQ2 in which no information is written is formed, and this M
MIS in which information is written by introducing n-type impurities into the offset part of FETQ2 (not an offset structure)
By forming the FET Q + and writing information, the impurity 6b is introduced into the offset portion through the interlayer insulation m7 and the gate insulating film 4 without passing through the gate electrode 5 of the MI 5FETQ2. can be introduced with low energy. Therefore, a low energy ion implanter can be used. Furthermore, since single-charged impurities can be used, the impurity introduction time can be reduced. That is,
Information writing time can be shortened.

In addition, by introducing impurity 6b with low energy,
Since damage to the main surface of the semiconductor substrate 1 at the offset portion can be reduced, crystal defects can be reduced. Moreover, since the damage can be reduced, crystal defects can be sufficiently recovered by performing heat treatment at 400 to 450 ["C] after forming the source line and data line 9. Therefore, MISFETQ Drain region 6 of I
Since it is possible to reduce the leakage current at the pn junction surface between the semiconductor substrate 1 and the semiconductor substrate 1, it is possible to reduce power consumption and prevent latch-up caused by a parasitic thyristor.

Moreover, since the information writing process can be performed after the process of forming the source line and data line 9, which is the final stage of the manufacturing process, it is possible to shorten the completion time of the mask ROM.

After the step of forming the MISFET Ql shown in FIG. 2, a passivation film is formed to complete the mask ROM.

Note that in the present invention, the impurity 6b for writing information is introduced after the step of forming the semiconductor region 6A, and the semiconductor region 6B is formed in the offset portion before the step of forming the source line and the data line 9. It's okay.

Further, in the present invention, the impurity 6b for writing information is added to the pad page 1 after forming the passivation film.
The semiconductor region 6B may be formed in the offset portion by introducing the semiconductor layer through the gate insulating film 7 and the gate insulating film 4.

[Example ■] This Example ■ is an example of the present invention in which the source region and drain region 6 of the MTS FET Q 2 having an offset structure in which no information is written are formed in self-alignment with the gate electrode 5. This is another example.

A method for manufacturing a mask ROM, which is Embodiment (2) of the present invention, is shown for each manufacturing process in FIGS. 7 to 1O (cross-sectional views). In the figure, the left side shows the MISFET QI formation region where information in the memory cell array is written, and the right side shows the MI forming area forming the peripheral circuit (for example, a decoder circuit).
5FETQ3 is shown.

First, as in Example I, on the main surface of the semiconductor substrate 1,
Field insulation film 2. Channel stopper region 3. A gate insulating film 4 and a gate electrode 5 are sequentially formed.

After this, as shown in FIG.
A single-hole type (low impurity concentration) semiconductor region 11 is formed on the main surface of the semiconductor substrate l on the side of the gate electrode 5 in the T S F E TQ3 formation region. Semiconductor region 11 is not formed within the memory cell array.

This semiconductor region 11 is used as the Ll)L) section.

A MI S FET having a so-called LDD structure is configured.

After the step of forming the semiconductor region 11 shown in FIG. 7, an impurity introduction mask 12 is formed on the side of the gate electrode 5. The impurity introduction mask 12 is 1, for example, 0.2 to 0.3
It is formed with a film thickness of about [μm].

The impurity introduction mask 12 can be formed, for example, by subjecting a silicon oxide film formed by CVD to anisotropic etching such as reactive ion etching.

This anisotropic etching removes the gate insulating film 4 on the gate electrode 5 and in the source and drain region forming regions. This removed part is not marked, but
A silicon oxide film is formed by thermal oxidation. This silicon oxide film acts as a barrier against contaminants (heavy metals).

Thereafter, an n-type impurity is introduced using the impurity introduction mask 12 to form an n'-type semiconductor region 6A as shown in FIG. This semiconductor region 6A forms the source region and drain region 6 of the M I S F E T Q 2 having an offset structure in which no information is written in the memory cell array. Further, the semiconductor region 6A and the semiconductor region 11 are the M of the LDD structure constituting the peripheral circuit.
ISFET Q 3 /- large region and drain region 6 are formed.

In the process of forming this semiconductor region 6A, MTS FET Q2 in which no information is written is completed, and MTS FET Q2 with an LDD structure constituting one peripheral circuit is completed.
T Q 3 is completed.

In this way, the M I S l? of the LDD structure of the peripheral circuit?
In the same manufacturing process as the impurity introduction mask 12 of ETQ3,
By forming the impurity introduction mask 12 constituting the offset structure of MISFET Q2 in which no information is written, the process of forming a mask for the offset structure is eliminated, so that the number of manufacturing steps can be reduced. Moreover,
The impurity introduction mask 12 has good film thickness controllability,
Since it can be formed in a self-aligned manner with respect to the gate t@5,
Mask misalignment in the manufacturing process can be reduced. This can reduce the area occupied by the 1Ml5FETQ2 and improve the degree of integration of the mask ROM.

Mata, peripheral circuit (7) LDD structure +7) MISFETQ
By forming the semiconductor region 6A of M I S F E T Q 2 in which no information is written in the same manufacturing process as the semiconductor region 6 A of M I S F E ',
Since the step of forming the 1"Q2 semiconductor region 6A is eliminated, the number of manufacturing steps can be reduced.

After the step of forming the semiconductor region 6A shown in FIG. 8, the impurity introduction mask 12 is removed as shown in FIG. This is M I S F E where no information is written.
This is to introduce impurities for writing information into the offset portion of TQ2. Removal of the impurity introduction mask 12 simultaneously removes the insulating film on the source and drain regions 6, so a new insulating film is formed in the removed portions, although no reference numerals are given.

After the step of removing the impurity introduction mask 12 shown in FIG.
and a wiring 9A.

Then, an n-type impurity 6b is introduced into the offset portion of a predetermined M I S F E T Q 2 to form a semiconductor region 6B.
As shown in FIG. 1O, a non-offset structure M I S F E T Q I in which information is written is formed. That is, information is written.

After the information writing step shown in FIG. 1O, a passivation film is formed in the same manner as in the embodiment (2), thereby completing the mask ROM of the present embodiment (2).

The invention made by the present inventor has been specifically explained above based on the above embodiments, but the present invention is as follows.

It goes without saying that the embodiments are not limited to the embodiments described above, and that various modifications can be made without departing from the spirit of the embodiments.

For example, the present invention can be applied to a mask ROM using a p-channel MTS FET as a memory cell.

〔Effect of the invention〕

As explained above, the effects obtained by one of the representative inventions disclosed in this application will be briefly explained as follows.

In the mask ROM, the MlSFE of Offcella 1 ~ structure
Forming a memory cell made of T, doping impurities into the offset portion of a predetermined memory cell among the memory cells,
By writing information by forming a memory cell that does not have an offset structure, it is possible to write information at the final stage of the manufacturing process after forming the memory cell. Since the impurity for writing information is introduced into the offset portion without passing through the electrode, the impurity can be introduced with low energy. This low-energy introduction can reduce the size of the ion implantation device, shorten the impurity introduction time, and reduce crystal defects.

[BRIEF DESCRIPTION OF THE DRAWINGS] FIG. 1 is a plan view of a main part of a memory cell array of a mask ROM which is Embodiment I of the present invention. FIG. 2 is a sectional view taken along the line ■-11 in FIG. 3 to 6 are cross-sectional views for each manufacturing process of a mask ROM that is an embodiment (2) of the present invention, and FIGS. 7 to 10 are sectional views for each manufacturing process of a mask ROM that is an embodiment (2) of the present invention. It is a sectional view for each process. In the figure, 1... semiconductor substrate, 2... field insulating film, 3... channel stopper region, 4... gate insulating film, 5... gate flttii, 6... source region or drain region , 6A, 6B... semiconductor region, 7.
...Interlayer insulating film. 9... Source line, data line, 10.12... Impurity introduction mask, QI, Q2. Q3...MISFET.

Claims (1)

[Claims] 1. A method for manufacturing a semiconductor integrated circuit device with a non-volatile memory function in which a memory cell is configured by MISFET, comprising:
forming the memory cell in an offset structure having an offset portion in which a source region or a drain region and a gate electrode are separated from each other; 1. A method of manufacturing a semiconductor integrated circuit device, comprising the step of introducing an impurity of the same conductivity type as a drain region to form a memory cell that does not have an offset structure. 2. The source region or drain region of the memory cell having the offset structure is formed by forming a gate electrode, then forming an impurity introduction mask that covers the gate electrode, and introducing an impurity using this mask. A method for manufacturing a semiconductor integrated circuit device according to claim 1, characterized in that: 3. The source region or drain region of the memory cell having the offset structure is formed by forming a gate electrode, forming an impurity introduction mask on the side of the gate electrode, and introducing impurities using this mask. A method for manufacturing a semiconductor integrated circuit device according to claim 1. 4. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein the impurity is introduced into the offset portion after forming a data line connected to a memory cell.