JPH01276757A - Manufacture of semiconductor memory device - Google Patents

Abstract

PURPOSE:To enable data writing process of ROM to be shifted to a later time by forming a gate electrode of MOS transistor (TR), masking the gate electrode according to the memory data and introducing impurities, and forming two types of transistors with different effective channel length. CONSTITUTION:A gate electrode 4 is formed on a gate insulation film 2 of a semiconductor substrate 1 and an A ion is implanted using a mask where a resist 5 remains at an electrode 4 of cell of a part which becomes an enhanced type TR. Then, a ROM is obtained where effective channel length becomes longer depending on the width M of the resist 5 and an enhanced type TR and depletion type TR area formed. As a result, data writing process of ROM can be shifted to a later time, thus reducing time until shipment as compared with formation of gate electrode after writing data.

Description

[Detailed Description of the Invention] [Summary] The present invention relates to a method for manufacturing a semiconductor memory device that stores information in accordance with the threshold voltage of an MO8-transistor, and the period from receiving an order to delivery is as short as possible. A step of forming gate electrodes of a plurality of MOS transistors that will become memory cells, a step of masking only the gate electrodes of the MOS transistors storing one of information 1'' and ''O'', and a mask. A step of introducing impurities for forming source and drain regions onto the masked gate electrode and the unmasked gate electrode, and forming a MOS transistor having an effective channel length of 2 psi according to the information to be stored. Contain and compose.

[Industrial application field]

The present invention relates to a semiconductor memory device that stores information in accordance with the threshold voltage of an MO8 transistor/transistor, and a method for manufacturing the same.

Mask ROM, which is a type of semiconductor memory device, writes the user's memory information (ROM data) into the memory element using a mask during the process, and the period from order receipt to delivery should be as short as possible. requested.

Therefore, on the process side, it is necessary to position the ROM data writing process as late as possible to reduce the number of days until process out.

[Conventional technology]

Figure 6 is an equivalent circuit diagram of a NAND type MASKROM, where E is an enhancement WMO8 transistor, D is a chip reduction type MO8 transistor, and information
1″ +++ 0* is supported.

7 is a plan view of the conventional example, and FIG. 8 is a Y-Y' cross-sectional view of FIG. 7, where 2 is a gate insulating film, 4 is a gate electrode, 6 is a source/drain region, and 9 is an impurity diffusion The region, IO, is an opening, and 11 is a resist.

[Conventional technology]

Conventionally, in a mask ROM of a NAND type cell as shown in FIG. 6, writing of ROM data is performed by using either an enhancement type or a depressing type of memory cell transistor. Whether to use a transistor or not was determined by an ion implantation method using a mask before forming the gate electrode 4. As shown in FIG. 7 (plan view) and FIG. 8 (cross-sectional view), before forming the gate electrode 4, make a photoresist (1) in which an opening 10 is provided only in the cell area where the depressurized transistor is to be formed.
1, an impurity diffusion region 9 is formed by ion implantation to lower the threshold voltage and become a depressing transistor, and then a gate electrode 4 is formed.

However, with this conventional method, the writing process is
This happens before e is formed.

[Problem to be solved by the invention]

Therefore, with the conventional method, there was a problem that orders could not be received if the period until the delivery date was short.

In addition, in the conventional method, depletion and John transistors were formed by ion implantation, so lateral diffusion by heat treatment after ion implantation was used to avoid affecting the bottom channel of the enhancement transistor adjacent to the Depressure transistor. It was necessary to provide a wide space between adjacent elements. In addition, since a depressing region is created in the program layer before gate formation, the gate electrode and the program layer are indirectly aligned. Therefore, taking into account misalignment, the aperture area in the program layer is the gate length x gate width. It was necessary to open holes larger in the misaligned area than in the area. The specifications between the gate electrodes have been restricted due to consideration of this lateral diffusion and positional deviation.

Therefore, an object of the present invention is to position the mask ROM data writing process as late as possible to reduce the number of days until process out. A further object of the present invention is to provide a method in which the programming layer can be directly aligned with the gate electrode, without having to take into account the effects of lateral diffusion.

[Means to solve the problem]

The above-mentioned problems include the process of forming gate electrodes of a plurality of MOS transistors that will become memory cells, and then the process of forming the information l1
A process of masking only the gate electrode of a MOS transistor that stores one of 1M and wO'', and introducing impurities to form the north and drain regions from the top (the masked gate electrode and the unmasked gate electrode).
The problem is solved by a method of manufacturing a semiconductor memory device characterized by including a step of forming a MOS transistor having an effective channel length of Zfl class depending on the information to be stored.

[Effect]

FIGS. 3(a) to 3(f) are diagrams explaining the principle of the present invention.
1 is a semiconductor substrate, 2 is a gate insulating film, 3 is a polysilicon film, 4 is a gate electrode, 5 is a resist, 6 is a source/drain region, 7 is a CVD5Slot film, and 8 is a PSG film.

In the present invention, after channel dosing (a) with B+ of an enhancement type transistor, a Polysi film 3 is grown on the gate insulating film 2 (b), and electrical penetration (punching) between the source and drain is completed with the voltage applied to the gate electrode 4K.・The polysilicon film 3 is patterned [7] to form the gate electrode 4 (C) so that the effective channel length is such that the through-flow can occur. Then, when performing ion implantation to form the north/drain 6, the enhancement type transistor E
As+ ions are implanted using various masks (d) that leave resist 5 on the gate electrode of the cell in the desired area (e).
. Then, the transistor D without the resist 5 becomes a depletion type transistor, and the transistor in the cell where the resist is left becomes an enhancement type transistor EK because the effective channel length becomes longer due to the resist @M.

Next, badge Pageron films such as the CVDeSiOt film 7 and the PSG film 8 are formed (f).

〔Example〕

FIG. 2 is a plan view showing an embodiment of the present invention, and FIG. 3 is a plan view taken along line xx' in FIG. 2. In FIG. 0, the same symbols as in FIG. 1 indicate the same parts.

In order to form an enhancement type transistor and a depressing type transistor based on the circuit diagram of Fig. 6,
In the present invention, two types of transistors, short and long, with different effective channel lengths are used. That is, the element to be the enhancement type transistor E forms a transistor with a long effective channel length, and the element to form the depressing type transistor D forms a transistor with a short effective channel length.

In the present invention, when the designed gate length is set to match a transistor with a short channel length, and the effective channel length is changed, the gate electrode 4 is covered with a resist 5 or the like only in the cell where the effective channel length is desired, as shown in FIG. Compensate for gate length. When source/drain diffusion layers 6 are formed by ion implantation in this state, transistors E with two types of effective channel lengths, short and long,
D can be formed at the same time. In order to make a transistor with a short effective channel length a depletion type transistor, the gate length must be designed to a length that causes punch-through. In addition, in order to make a transistor with a long effective channel length an enhancement type transistor, the effective channel length is determined by the width of the resist covering the gate, so the width of the resist must be set to a width that prevents punch-through. It won't happen.

In the transistor forming process, first a gate oxide film 2 is formed, then a polysilicon or silicide film is formed, and a gate electrode pattern 4 is formed by photoetching or the like. Thereafter, a photoresist 5 is left using a mask on the gate of the element to be enhanced transistor EK.

In this state, ion implantation is performed to form sources and drains. If the gate electrode pattern is patterned using a 7-photoresist, it will be removed afterwards, but if it is formed using an insulating film or the like, it may be left as long as disconnection of the wiring layer due to the step does not pose a problem.

Regarding the gate electrode pattern 4, there is no problem even if cells on the same word line are connected pattern-wise, but if adjacent cells on the bit line are connected pattern-wise, the diffusion layer region between the two cells will be Since it cannot be formed, it must be differentiated.

The transistor D having a short effective channel length formed in this manner is normally turned on because a current flows between the source and drain due to punch-through when a voltage is applied to the drain even when the gate voltage Ov is applied.

In a transistor with a long effective channel length, no current flows between the source and the drain when the gate voltage Ov is applied, and current flows between the source and the drain only when the gate voltage is applied, so that the transistor is normally in an off state.

Assuming that the drain diffusion layer is connected to the bit line and the gate is connected to the word line, when selected with the bit line H level and the word line L level, the transistor E with a long effective channel length is turned on. No bit #i
! Since the potential does not drop, information ``1'' can be stored. In addition, in a transistor with a short effective channel length, the transistor is turned on, the bit line potential decreases, and information "0" can be stored.In this way, 1m and @θ" can be distinguished and stored based on the difference in effective channel length. can.

Note that it is preferable to determine the length of the resist used as a mask and the gate electrode in the channel length direction as follows, taking into account misalignment. Figure 4 is a cross section showing the case where there is no misalignment of the resist. FIG. 5 is a sectional view showing a case where there is a positional shift of the resist.

Considering the control of the gate electrode width, a polysi gate is formed to have a good etching shape and the minimum width that can be controlled. The value X of the distance between the resist and the gate (on one side of the fog) determines the length of the source/drain under the gate (lateral diffusion length): y1 and the maximum positional deviation value: 2.

In order to prevent an offset transistor from becoming an offset transistor when there is a maximum deviation of yμ on one side, it is necessary to ensure that X+Z≦y.

[Effects of the Invention] As explained above, according to the present invention, a program layer for distinguishing between an enhancement type and a depression type can be positioned after forming a gate electrode. This is because the program position in the present invention is later than the conventional method, that is, the method in which chromium is applied before gate formation as shown in FIG. 7 (plan view) and FIG. 8 (cross section). This has the effect of reducing the turnaround time.

In addition, in the conventional method, the depletion write transistor was formed by ion implantation, so lateral diffusion due to heat treatment after ion implantation affected the channel bottom of the second write transistor adjacent to the depletion transistor. It was necessary to provide a wide space between adjacent elements so as not to cause damage. In addition, since the depressing region is created in the program layer before Gate formation, the Gate electrode and the program layer are indirectly aligned, so the opening area of the program layer is the area of Gate length x Gate width, taking into account misalignment. It was necessary to open a hole larger in the misaligned area.

The specifications between the gate electrodes were limited due to consideration of this lateral diffusion and positional deviation, but in the method of the present invention, the programming layer can be directly aligned with the gate electrode, and since it is not an ion-implanted layer, the influence of lateral diffusion is taken into consideration. Since it is not necessary, it greatly contributes to integration.

[Brief explanation of the drawing]

Figure M1 is a diagram explaining the principle of the present invention, (a) to (f) are sectional views, respectively, Figure 2 is a plan view showing an embodiment of the present invention, and Figure 3 of the hole is wL.
XX' cross-sectional view in Figure 2, Figure t44 is a cross-sectional view showing the case where there is no positional shift of the resist, Figure 5 is a cross-sectional view showing the case where there is positional shift of the resist, and Figure 6 is the equivalent of a NAND MASK ROM. The circuit diagram, FIG. 7 is a plan view of the conventional example, and FIG. 8 is a YY' sectional view of FIG. 7. 1; Semiconductor substrate; 2; Gate insulating film; 3; Polysilicon film; 4; Gate electrode; 5; Resist film; 6; Source/drain region; 7; CVD@SiO* film; 8; PSG film. 10. V-2 Figure 2 x-g' sectional view Figure 3 NAND type MAsKRoM etc. 1 convex circuit diagram 16 Leap

Claims (1)

[Claims] A step of forming gate electrodes of a plurality of MOS transistors serving as memory cells, and then a step of masking only the gate electrodes of the MOS transistors that store either information "1" or "0"; A process of introducing impurities to form source and drain regions onto the masked gate electrode and unmasked gate electrode to form a MOS transistor having two types of effective channel lengths depending on the information to be stored. A method of manufacturing a semiconductor memory device, comprising: