JPH05218328A - Nand-type mask rom - Google Patents

Abstract

PURPOSE: To provide an NAND-type mask ROM capable of accurate readout, in the case that a string selection transistor and a cell transistor are in a submicron class. CONSTITUTION: Layout is performed in such a manner that the channel length of a string selection transistor of an enhanced type channel, defined by widths of string selection lines 42, 43 is made longer than the other transistors. The enhanced channel length is set to a degree that a punch through is not generated, when a drain voltage higher than or equal to Vcc is applied. Thereby a leakage current of a string which is not selected can be restrained, so that malfunctions of a storage device can be prevented.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a NAND type mask programmable read only memory (mask ROM).

[0002]

2. Description of the Related Art Generally, a NAND mask ROM has a structure in which a large number of depletion type transistors and a large number of enhancement type transistors are connected in series through diffusion layers. One group of cells connected in series between the bit line and the ground voltage terminal is one string
Defined as (string). The depletion type transistor is a by-product and is a functionally simple connecting line.

FIG. 2 is a partial equivalent circuit diagram of a NAND type mask ROM, showing two strings connected to one bit line B / L. As shown in the figure, one string includes a first string selection transistor 1 (2) and a second string selection transistor 3 (4) connected in series from a bit line, and a source side of the string selection transistor and ground. It is composed of n MOS transistors 5, ..., 7, 9 (6, ..., 8, 10) connected in series with the voltage terminal (GND) and operating as memory cells. A large number of strings form a parallel column group, and among a large number of rows orthogonal to the columns, the gates of the string selection transistors in the same row share the string selection line 11 or 12, and the gates of the memory cells in the same row are One of the word lines 13, ..., 14, 15 is shared.

The operation of the NAND type mask ROM will be briefly described below with reference to FIG. When a predetermined memory cell is selected to perform reading, 1 V to Vcc (power supply voltage) is applied to the selected bit line and word line.
The read voltage and 0 V (ground voltage) are applied respectively. The gate of the string selection transistor of the string to be read is 0 V in the case of the depletion type and Vcc in the case of the enhancement type.
Is applied. In addition, Vc is applied to unselected word lines.
Apply c. As a result, when the selected memory cell is of the depletion type, it is turned on by the ground voltage (0V) applied to its gate, so that the read voltage applied to the bit line is transmitted, which causes the logic "1". "Is read out. On the other hand, when the selected memory cell is of the enhancement type, it is turned off by the ground voltage (0V) applied to its gate, so that the read voltage applied to the bit line is not transmitted and the logic "0" is output. Read out. That is, the ground voltage (0 V) is applied to the gate of the memory cell to be read, and the characteristic difference between the normally-on type depletion type transistor and the normally-off type enhancement type transistor is used to make a logic “1” or a logic “0”. "Is read out.

FIG. 3 is a layout diagram of a conventional NAND type mask ROM (mask form for processing) and is a layout diagram for the equivalent circuit shown in FIG. An active line 20 extending in the first direction (length direction of the string) and forming two strings formed of n + type diffusion regions (mask form for processing) in the semiconductor substrate, and an upper portion of the active line 20. The string selection lines 22 and 23 and the word lines 24 to 2 extended in the second direction (the length direction of the word line) and arranged in parallel in the first direction.
6 and n + type ground lines 28, bit lines 30 extending in the first direction above the word lines 24, and contact regions 32 for contacting the active lines 20 and the bit lines 30. .. Reference numeral 3 in FIG.
The portions indicated by 4, 35 (for string selection) and 36 (example of cell) indicate depletion type MOS transistors.
Further, a portion of the active line 20 that does not overlap the word lines 24 to 26 becomes an actual n + diffusion region.

Due to the recent trend of increasing the capacity of memory devices, the channel lengths of the string selection transistor and the cell transistor in the cell array have been reduced to the submicron unit. In such a memory device, a malfunction occurs due to a leakage current in an unselected string among a plurality of strings connected to a bit line. That is, as the size of a transistor is reduced to increase the capacity, its channel length and doping concentration profile in the channel are
It becomes sensitive to environmental changes in the manufacturing process such as the pattern forming process of polycrystalline silicon used for gates and word lines, the etching process of polycrystalline silicon, and the ion implantation process for adjusting the threshold voltage. Therefore, as shown in FIG. 3, when the string selection transistor and the cell transistor have the same size, a leakage current flows in the unselected string selection transistor, and a malfunction occurs when reading the turned off cell. There are cases. This problem is 1
When connecting many strings to a bit line of a book, the potential of the bit line is set to Vc for high-speed reading.
It becomes even more serious when precharging to c.

[0007]

SUMMARY OF THE INVENTION Therefore, it is an object of the present invention to perform a read operation accurately even if a plurality of strings are connected to one bit line and the size of a cell transistor is submicron. It is an object of the present invention to provide a NAND type mask ROM capable of suppressing a leakage current caused by punch through of a string selection transistor.

[0008]

In order to achieve such an object, a NAND type mask ROM according to the present invention has a channel length of the enhancement type string selection transistor among the string selection transistors of each string constituting the mask ROM. , The depletion type string selection transistor, and in some cases, the channel length of the cell transistor may be made longer.

[0009]

As described above, by making the channel length of the enhancement type string selection transistor longer than the channel lengths of the other transistors, the effective channel length of the transistor and the doping concentration for adjusting the threshold voltage in the channel are controlled depending on the environment of the manufacturing process. Even if the profile changes a little, punch-through of the enhancement type string selection transistor can be effectively prevented, so that the leakage current can be suppressed.
In addition, since only the enhancement type transistor of the enhancement type and depletion type string selection transistors only increases the channel length, there is almost no effect on the layout area in the string extending direction.

[0010]

Embodiments of the present invention will now be described in detail with reference to the accompanying drawings. FIG. 1 is a layout diagram of an embodiment of a NAND type mask ROM according to the present invention (processing mask form).
And corresponds to the equivalent circuit shown in FIG. An active line 40 extended in a first direction (length direction of the string) and formed of an n + type diffusion region in the semiconductor substrate, and a second active line 40 above the active line 40.
Direction, that is, the length direction of the word line, and the string selection lines 42 and 43 arranged in parallel in the first direction.
The word lines 44, ..., 45, 46 and the ground line 4
8, bit lines 50 extending in the first direction above the word lines, and contact regions 52 for contacting the active lines 40 and the bit lines 50. The portions indicated by reference numerals 54, 55 and 56 in the figure indicate depletion type MOS transistors.

As can be seen from FIG. 1, the channel length of the string select transistor of the enhancement type channel defined by the width of the string select line is:
It is laid out to be longer than other transistors. The extended channel length is such that punch through does not occur even when a high drain voltage of Vcc or more is applied. In the case of this embodiment, the channel length of the enhancement type string selection transistor is about 0.1 μm to 0.2 μm as compared with other string selection transistors.
μm (when operating voltage is 2.5 to 5.5 V). That is, for example, in a memory device of 16 mega or more that uses an operating voltage of 2.5 to 3.5 V, the voltage of approximately 0.
In a memory device of 4 Meg or less using an operating voltage of 1 μm and 4.5 to 5.5 V, the memory device has a length of about 0.2 μm. As a result, punch through of the string selection transistor of the unselected string can be prevented, and malfunction due to leakage current can be prevented.

[0012]

As described above, the NA according to the present invention
The ND type mask ROM can effectively prevent punch-through of the enhancement type string selection transistor by making the channel length of the enhancement type string selection transistor in the string selection transistor longer than that of the other transistors, and thus the unselected string is not selected. Since the leakage current of the memory device can be suppressed, it is possible to prevent the malfunction of the memory device. In addition, since the channel length of only the enhancement type transistor of the enhancement type and depletion type string selection transistors is increased, the operation reliability of the memory device is ensured without significantly affecting the integration degree of the memory device. There is also the effect that you will be able to.

[Brief description of drawings]

FIG. 1 is a layout diagram showing an embodiment of a NAND mask ROM according to the present invention.

FIG. 2 is a partial equivalent circuit diagram of a NAND mask ROM.

FIG. 3 is a layout diagram showing an example of a conventional NAND mask ROM.

[Explanation of symbols]

 40 active line 42, 43 string selection line 44-46 word line 48 ground line 50 bit line 52 contact area 54-56 depletion type transistor

Claims (2)

[Claims] 1. A string selection transistor group composed of depletion type and enhancement type string selection transistors connected in series from a bit line, and connected in series between the string selection transistor group and a ground voltage terminal. A NAND-type mask ROM including a large number of cell transistors, wherein the channel length of the enhancement-type string selection transistor is longer than that of the depletion-type string selection transistor. 2. The NAND type mask RO according to claim 1, wherein the channel length of the enhancement type string selection transistor is such that punch through does not occur even with a drain voltage higher than the power supply voltage.
M.