JPH05136373A - Semiconductor integrated circuit and its manufacture - Google Patents

Abstract

PURPOSE:To make small the area of an element isolating area and also, elevate the flexibility of a circuit. CONSTITUTION:In the channel region 8 of an MOS transistor 6a, the threshold voltage is elevated to approximately 6V by ion implantation, and the MOS transistor 6a ceases to operate with 5V power, thus the MOS transistors 6 and 6 on both sides are isolated. The wiring efficiency is elevated by arranging the wiring 14 on the MOS transistor 6a, or using a gate electrode as wiring.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a master slice type semiconductor integrated circuit device in which a plurality of basic cells including MOS transistors are regularly arranged, and more particularly to a MOS gate array and a MOS composite gate array (part of a semiconductor chip). A semiconductor integrated circuit device having a gate array structure),
Alternatively, the present invention relates to a CMOS type or BiCMOS type master slice type semiconductor integrated circuit device in which a basic cell includes a P channel type MOS transistor (hereinafter referred to as a PMOS transistor) and an N channel type MOS transistor (hereinafter referred to as an NMOS transistor).

[0002]

2. Description of the Related Art (1) A field insulating film is used for element isolation used in MOS transistors.
(2) A non-conductive MOS transistor having a gate electrode connected to a power supply is used. In the element isolation using the field insulating film, as shown in FIG. 10A, the diffusion layer 3 is self-aligned by the gate electrode 30 in the region surrounded by the element isolation region 34 of the field insulating film.
2 is formed. In the element isolation in which the gate electrode is connected to the power source, as shown in FIG. 10B, the gate electrode 40 a in the element isolation region 48 is connected to the power source wiring 44 via the contact 46. 42 is a diffusion region, and 40 is a gate electrode of another MOS transistor.

In a MOS transistor, the gate insulating film is generally vulnerable to a surge from the outside, and it is necessary to provide a protection circuit. As a protection circuit, it is widely practiced to connect a protection element having a withstand voltage lower than the gate withstand voltage of a MOS transistor to a gate electrode to absorb a surge from the outside. As a surge protection circuit for MOS transistors, protection elements 56, 5 as shown in FIG.
8 is used. These protective elements are M of the internal circuit 52.
A transistor having a breakdown voltage lower than the gate breakdown voltage of the OS transistor is used, and the protection resistor 5 is provided between the input terminal 50 and the internal circuit 52.
4 together.

In the CMOS type master slice, the PMOS transistor and the NMOS transistor included in the basic cell are set to their own sizes. Therefore, when a certain logic circuit is constructed using the basic cell, the logic circuit is The threshold voltage is uniquely determined.

FIG. 14A shows one memory cell portion of a static RAM (hereinafter referred to as SRAM).
A pair of inverters 50 and 52 and access gates Ma and M
The memory cell 54 is configured by including b. A word line WL is provided for selecting the access gates Ma and Mb, and bit lines BL and BLB (B represents inversion) are connected to a sense circuit, respectively, and
Gate Mp for precharging bit lines
It is connected to the power source via a and Mpb.

[0006]

In the element isolation by the field insulating film 34 as shown in FIG. 10 (A), the space required for the isolation is large and the flexibility of the circuit is lacking. That is, the basic gate separated by the field insulating film generally has two inputs. Therefore, when configuring a circuit with 3 inputs or 5 inputs, there is an unused gate electrode, which means that there is no flexibility with respect to the number of input signals. FIG. 10 (B)
In the element isolation region of, the gate electrode 40a is connected to the power supply wiring 44
Area is required, and wiring efficiency is poor. Further, the gate electrode 40a cannot be used for wiring, and the wiring efficiency is poor in this respect as well.

With the recent miniaturization of devices,
The gate insulating film is becoming thinner according to the scaling rule. Since the gate breakdown voltage depends on the thickness of the gate insulating film,
As the gate insulating film becomes thinner, the gate breakdown voltage becomes lower. On the other hand, since the conventional surge protection element is composed of the same MOS transistor as the MOS transistor that realizes the internal logic circuit, the drain withstand voltage of the protection element has not decreased due to various measures for ensuring reliability. .. Therefore, as shown in FIG. 11B, with the miniaturization of the element, a reversal phenomenon occurs in which the gate breakdown voltage becomes lower than the drain breakdown voltage of the protection element, and it becomes impossible to function as the protection element.

The conventional diode having a PN junction has a reverse breakdown voltage that depends on temperature and cannot be used as a constant voltage circuit. When changing the threshold voltage of a logic circuit using a conventional CMOS basic cell, a plurality of PMOS transistors and a plurality of NMOS transistors are connected in series or in parallel and combined, and the PMOS
The threshold voltage must be set by the ratio of the number of transistors and NMOS transistors. For example, in FIG.
(A) is an inverter configured to have a desired threshold voltage and includes three PMOS transistors P11,
It is composed of P12 and P13 and one NMOS transistor N11. The equivalent circuit is shown in FIG. A ROM sense amplifier is shown in FIG. 13A as an example of a logic circuit that requires more basic cells. This sense amplifier includes six PMOS transistors P21 to P26 and six NMOS transistors N.
21 to N26, and an equivalent circuit thereof is shown in FIG.
It is shown in (B).

As described above, when a logic circuit is constructed by using the conventional CMOS master slice, a plurality of PMOS transistors and a plurality of NMOS transistors are required in order to change the logic threshold voltage thereof. The occupied area on the master slice chip becomes large. In addition, since the numbers used between the PMOS transistor and the NMOS transistor do not necessarily match, unused MOS transistors are formed, which further increases the circuit scale. PM included in basic cell
Since the sizes of the OS transistor and the NMOS transistor are constant, the size is larger than the minimum transistor size required to pass the necessary current, and an extra direct current flows.

A precharge method is one of the methods for increasing the memory speed. This is a method in which, as shown in FIG. 14B, the bit lines BL and BLB are precharged to an intermediate potential, and the word line WL is raised from that state to start reading. In that case, since the data of the memory cell is read by raising the word line WL while charging the bit lines BL and BLB, for example, if the node na is at a low level, "0" of the node na is inverted to "1". Do not do, that is, node na
Potential Vna of the inverter 50 of the latch portion of the memory cell
It is important that the threshold voltage is not exceeded. The potential of the node na when the word line WL rises is, as shown in FIG. 14C, the resistance Rpa of the precharge MOS transistor Mpa, the resistance Rm of the access gate Ma, and the NMOS transistor of the inverter section of the memory cell. It depends on the ratio of the resistance Rn. That is, Vna = Vcc × Rn / (Rpa + Rm + Rn). Here, Rpa cannot be increased so much because it needs to be precharged at a high speed in order to speed up reading in the next cycle after the reading is completed, and it is about a fraction of Rm and Rn. is there. Therefore, the potential Vna of the node na is substantially determined by Rm and Rn. if,
If Rm and Rn are equal, the potential Vna of the node na becomes about 2.5 V (the power supply Vcc is 5 V), which exceeds the threshold voltage. In order to prevent such data inversion of the memory cell, Rm is increased or Rn is decreased. It is necessary to take either or both of these measures, but in order to prevent an increase in the area of the memory cell, the usual measures are taken.

On the other hand, in the master slice type semiconductor integrated circuit device, the PMOS transistor and the NMOS transistor are set to have a unique channel width. Therefore, if the memory cell of FIG. 14A is to be realized on the master slice type semiconductor integrated circuit device, the countermeasure of FIG.
As shown in FIG. 15A, the MOS transistors are connected in series, and as a countermeasure, the MOS transistors are connected in parallel as shown in FIG. Whichever method is used, the number of used gates increases and the area of the memory cell increases.

On the other hand, in addition to the PMOS transistor and the NMOS transistor to the basic unit cell, an NMOS transistor having a smaller size is added to the basic unit cell as a basic unit of the master slice type semiconductor integrated circuit device. A method of using a small NMOS transistor as an access gate has been proposed ("Monthly publication"
Semiconductor World "February 1990, 92-95.
See page). However, in the proposed method, the area of the basic unit cell is increased by the addition of the small size NMOS transistor.

In the SRAM, generally complementary signals (BL and BLB) are required in the write operation as shown in FIG. As one method of increasing the density of SRAM,
There is a method of reducing the number of data lines (bit lines) and the number of MOS transistors by using a single signal as a complementary signal for write operation. A memory cell according to the method is shown in FIG. 6B which is shown as an equivalent circuit of one embodiment of the present invention. However, if an attempt is made to realize this memory cell in a master slice type semiconductor integrated circuit, P
Since the MOS transistor and the NMOS transistor are set to their own transistor sizes, there is a possibility that erroneous writing may occur during the read operation. Therefore, normally, the reading is performed by the precharge method in the synchronous method. Further, a configuration such as inserting an inverter between the access gate and the latch unit is required so that the read operation is not fed back to the memory cell. Therefore, the SRAM using the master slice type semiconductor integrated circuit
Therefore, the purpose of high density cannot be achieved.

In some SRAMs, the initial state can be set when the power is turned on in order to prevent the initial state of the memory cell from becoming undefined when the power is turned on. One example is to set the initial state by changing the characteristics of the memory cell. There, the transistor size is changed by changing the width of the diffusion layer of the MOS transistor forming the memory cell, and the characteristics of the memory cell are arbitrarily set to set the initial state.
As another memory cell for setting the initial state, there is one for changing the circuit of the memory cell. For example, a memory circuit in which a load transistor forming a memory cell is a depletion type (see Japanese Patent Publication No. 2-30118) or a CMOS
There is reported a memory circuit (see Japanese Patent Publication No. 2-17875) in which the circuit is changed so that the gate electrode of the PMOS transistor of the memory cell having the structure is grounded. However, the method of changing the width of the diffusion layer in order to change the characteristics of the memory cell cannot be applied to the master slice type semiconductor integrated circuit device. In the method of changing the circuit of the memory cell, the circuit must be changed according to the set value.

A first object of the present invention is to provide element isolation that requires a small area. A second object of the present invention is to provide element isolation with high circuit flexibility. A third object of the present invention is to provide a protection element having a drain breakdown voltage lower than the gate breakdown voltage of the internal circuit. A fourth object of the present invention is to provide a constant voltage circuit having small temperature dependence. A fifth object of the present invention is to set the logical threshold voltage of a configured logic circuit arbitrarily without using many basic cells, and to effectively use MOS transistors to reduce the circuit scale. It is an object of the present invention to provide a master slice type semiconductor integrated circuit device which can be reduced in size and further reduce power consumption without flowing an extra direct current. A sixth object of the present invention is to realize a high speed memory which does not malfunction without increasing the number of used gates. A seventh object of the present invention is to realize an SRAM capable of writing with a single signal and capable of achieving high density in a master slice type semiconductor integrated circuit. An eighth object of the present invention is to realize a static RAM realized by a master slice type semiconductor integrated circuit device, which realizes an SRAM in which characteristics of memory cells are changed and an initial state at power-on can be set. is there.

[0016]

According to the present invention, a part or all of the channel region of at least one MOS transistor in the basic cell region is a channel region of another same conductivity type MOS transistor in the same basic cell. Have different impurity concentrations. In the present invention, in order to reduce the area of the element isolation region, the MOS having different impurity concentrations is used.
The transistor is made to have a threshold voltage that does not operate at the power supply voltage of this semiconductor integrated circuit device and used for element isolation.

In order to achieve element isolation with high circuit flexibility, the present invention uses the gate electrode of a MOS transistor used for element isolation with different impurity concentrations as wiring. In order to obtain a protection element having a drain breakdown voltage lower than the gate breakdown voltage of the internal circuit, in the present invention, the diffusion region to be the protection element is deeply doped with impurities of the opposite conductivity type to the diffusion region,
In addition, by injecting at a high concentration, PN between the diffusion region and the substrate
The breakdown voltage of the junction is made smaller than the breakdown voltage of other PN junctions of the same conductivity type. A PN junction with a reduced breakdown voltage is used as a surge protection element for the terminal portion.

In order to obtain a constant voltage circuit having a small temperature dependence, according to the present invention, an impurity having a conductivity type opposite to that of the diffusion region is deeply and highly implanted into the diffusion region until the PN junction exhibits zener characteristics. Set the logical threshold voltage arbitrarily,
In order to reduce the circuit scale and suppress an excessive direct current, in the present invention, a part of the channel of at least one MOS transistor is ion-implanted to narrow the effective channel width of the MOS transistor. In order to obtain a high-speed memory that does not malfunction, the present invention uses a MOS transistor whose effective channel width is narrowed by ion implantation as an access gate of a memory cell.

In order to achieve an SRAM capable of writing with a single signal, in the present invention, a part of the channel of at least one MOS transistor is ion-implanted to narrow the effective channel width of the MOS transistor, and the memory is One bit line is connected to the latch portion of the cell through one access gate to form an SRAM that performs a write operation with a single signal. In order to realize an SRAM capable of setting an initial state when power is turned on, in the present invention, a memory cell is set to an initial state when a predetermined voltage is applied from a bit line through an access MOS transistor. In this way, the channel of at least one MOS transistor of the memory cell and the access MOS transistor is ion-implanted to change the characteristics of the memory cell. Ion implantation reduces the effective channel width by preventing a part of the channel region from forming a channel, or it is applied to the entire channel region to set a threshold value so that the channel is formed at a specific voltage within the normal power supply potential. Do to control.

The manufacturing method of the present invention includes a master process for forming a source / drain diffusion region and a gate electrode, or a source / drain diffusion region and a gate electrode and a part of wiring, and a custom process for forming the wiring. In this custom process, the impurity concentration of a part or all of the channel region of at least one MOS transistor is changed to another same conductivity type M.
The process includes controlling the impurity concentration to be different from that of the channel region of the OS transistor. The step of controlling the impurity concentration is performed, for example, after the gate electrode is formed and before the wiring is formed, or after the wiring is formed.

[0021]

When the MOS transistor is ion-implanted for channel doping, the NMOS transistor is implanted with boron at a dose of 1 × 10 ^{12 to} 3 × 10 ¹² / cm ² and an acceleration energy of about 30 KeV.
The threshold voltage of the transistor is 0.7 to 1.0 V, but the ion implantation amount is 4 × 10 ^{13 to} 5 × 10 ¹³ / cm ² ,
If the acceleration energy is about 180 KeV, the NMO
The threshold voltage of the S transistor becomes about 6V, and the latter NMOS transistor does not operate at the power supply voltage of 5V normally used for the operation of the semiconductor integrated circuit device.

Similarly, in the PMOS transistor, when phosphorus or arsenic is ion-implanted into the channel, the implantation amount is 1
0 ¹⁰ to 10 ¹³ / cm ² , acceleration energy 100 to 20
When it is set to 0 KeV, the threshold voltage of the PMOS transistor becomes about 6V, and the PMOS transistor cannot operate with a 5V power supply.

When the ion implantation for increasing the threshold voltage as described above is performed on all the channels of a certain MOS transistor, the MOS transistor plays a role of element isolation. A diode having a PN junction exhibits zener characteristics when the P-type and N-type concentrations of the junction become high. If this junction is used as a Zener diode, a constant voltage circuit with little temperature change can be realized. If ion implantation for increasing the threshold voltage is performed on a part of the channel of the MOS transistor, the effective channel width of the MOS transistor changes. A MOS transistor having a changed effective channel width can be combined with another MOS transistor to adjust the logical threshold value. Further, by using the MOS transistor having a reduced effective channel width for the access gate, a precharge type high speed memory which does not malfunction can be realized.

[0024]

FIG. 1 shows an embodiment in which the element concentration is changed by changing the impurity concentration of the channel region. In (A), the diffusion regions 4 are formed in a self-aligned manner by the gate electrodes 2 and 2a to form the MOS transistors 6 and 6a, respectively. The impurity concentration of the entire region of the channel region 8 of the MOS transistor 6a is different from that of the channel regions of the other MOS transistors 6 of the same conductivity type. When the MOS transistor 6a is an NMOS transistor, boron has an acceleration energy of about 180 in the region 8.
KeV, ion implantation is performed so that the implantation amount is 4 × 10 ^{13 to} 5 × 10 ¹³ / cm ^2, and the MOS transistor 6 is formed.
The threshold voltage of a is increased to about 6V, and
When the MOS transistor 6a is a PMOS transistor, phosphorus or arsenic has an acceleration energy of 1 in the region 8.
00-200 KeV, injection amount 4 × 10 ^{13 to} 5 × 10 ¹³
/ Cm ² and so as to be ion-implanted, the threshold voltage of the MOS transistor 6a is raised to about 6V. As a result, the MOS transistor 6a does not operate with the 5V power supply, and the presence of this MOS transistor 6a causes the MOS transistors 6 and 6 on both sides thereof to operate.
6 are separated from each other.

In the MOS transistor 6a used for element isolation, it is not necessary to connect anything to the gate electrode 2a, so in (B) the MOS transistor 6a is connected.
The wiring 14 is arranged on the top of the wiring to improve the wiring efficiency. Other M
In the OS transistor 6, the gate electrode 2 has a contact 1
The wiring 12 is connected via 0. (C) uses the gate electrode 2a of the MOS transistor 6a used for element isolation as a wiring, and in order to improve wiring efficiency,
The wiring 18 is connected to the gate electrode 2a via the contact 16.
Connected to.

In FIG. 2A, as a surge protection circuit for the internal circuit 22, protection diodes 24 and 28 are connected to the input terminal 20 together with the protection resistor 24. The protection diodes 26 and 28 extend the ion implantation for channel-doping the NMOS transistor to the diffusion portion to allow the P-type impurities to reach the bottom of the diffusion portion and form a high-concentration PN junction. It was used as. The PMOS transistor can be similarly formed.

The breakdown voltage of the PN junction decreases as the injection amount increases. FIG. 2B shows the relationship between the injection amount and the breakdown voltage. A protection diode having a desired breakdown voltage can be realized by appropriately setting channel doping conditions. Therefore, the MOS transistor can be protected from the surge by adding a protection diode having a breakdown voltage lower than the gate breakdown voltage without hindering the operation.

Further increasing the impurity concentration, for example, an ion implantation amount of about 6 × 10 ¹⁵ / cm ² , an acceleration energy of 70 KeV.
1 × 10 ^{14 to} 5 × 10 in the N-type diffusion layer in which arsenic is implanted by
If BF ₂ is implanted at ¹⁴ / cm ² and an acceleration energy of 150 KeV, the obtained high-concentration PN junction exhibits zener characteristics. If this PN junction is used as a Zener diode, a constant voltage circuit with little temperature change can be realized.

3 to 5 show an embodiment of the present invention in which a desired circuit is constructed by ion-implanting a part of the channel to control the channel width. Ion implantation conditions for controlling the channel width are as follows. When the target MOS transistor is an NMOS transistor, boron is partially accelerated in the channel region with an acceleration energy of about 180 KeV and the implantation amount is 4 × 10 ^{13 to} 5 ×. Ion implantation is performed at 10 ¹³ / cm ^2, and the target MOS transistor is PM.
In the case of an OS transistor, phosphorus or arsenic is ion-implanted into the region 8 so that the acceleration energy is 100 to 200 KeV and the implantation amount is 4 × 10 ^{13 to} 5 × 10 ¹³ / cm ² . As a result, a portion of the channel of the MOS transistor, which has been subjected to such ion implantation, does not operate with the 5V power supply, and the effective channel width of the MOS transistor becomes narrow. On the other hand, as a method of controlling the channel width, there has been proposed a method of controlling the source / drain regions by changing the ion implantation mask for forming the source / drain (Japanese Patent Laid-Open No. 61-23).
No. 4546). However, the proposed method is not suitable for miniaturization because the source / drain regions must be aligned along the gate electrode. Since the contact hole must be aligned with the source / drain region, if the source / drain region is narrow, the degree of freedom of the position of the contact hole is lost, and the channel width is narrowed only to the extent that the contact hole can be formed. However, there is a limit to the channel width that can be selected.

FIG. 3A shows an example in which an inverter is constructed by ion-implanting a part of the channel to control the channel width according to the present invention. This inverter is shown in Figure 3.
As shown in the equivalent circuit in (B), one PMO
It is composed of an S transistor P and one NMOS transistor N, and the NMOS transistor N has 2 /
Channel 3 is channel-doped to increase the threshold voltage, and the effective channel width is reduced to 1/3 of the NMOS transistor included in the basic cell. As a result, the PMOS transistor P and the NMOS transistor N
The ratio of the channel widths is 3: 1.

The threshold voltage with respect to the ratio of the channel widths of the PMOS transistor and the NMOS transistor is shown in FIG.
It shows in (C). The threshold voltage Vth increases as the proportion of the PMOS transistor increases. Figure 3
3A shows a channel width changed by ion-implanting a part of the NMOS transistor in order to set the threshold voltage indicated by a on the curve of FIG. 3C. FIG. 11A shows an inverter having a threshold voltage composed of a conventional basic cell. FIG. 3A and FIG.
Comparing 1 (A), four MOs were required in the past.
In this embodiment, only two S transistors are required, and the power consumption is small.

FIG. 4A shows an embodiment in which a ROM sense amplifier is constructed by using the present invention. In this example, two PMOS transistors P1 and P2 and two NMOs are used.
S-transistors N1 and N2 are used and one PMOS
The threshold voltage of the transistor P2 and one NMOS transistor N1 corresponding to 4/5 of the channel width is increased by ion implantation so that the portion does not operate with a 5V power supply, and the effective channel width is reduced to 1/5. Has been made.

The equivalent circuit of FIG. 4A is shown in FIG. 4B and constitutes a NAND circuit. When a NAND circuit is composed of two PMOS transistors and two NMOS transistors using the conventional basic cell, the threshold voltage becomes the level of a shown in FIG. 4 (C). On the other hand, if the input signal of the bit line changes as shown by D, there will be a large difference in the speed of reading the L level and the H level, and the speed of the sense amplifier will be determined by the slower one. I will end up. Figure 4
The sense amplifier of (A) has the logical threshold voltage raised to the level of b so that the read speeds of the L level and the H level are almost the same. If a conventional master slice is used so that the logic threshold voltage is at the level of b in FIG. 4C, the structure shown in FIG. The number of basic cells required for the amplifier increases, the circuit scale required for the sense amplifier increases, and power consumption also increases.

Similarly, when a sense amplifier of another memory or a logic circuit having a different ratio of a PMOS transistor and an NMOS transistor is required, the effective channel width is changed to the minimum circuit scale according to the present invention. Can be reduced.

Another example of controlling the effective channel width by ion implantation according to the present invention is shown in FIG. FIG. 5 shows FIG.
The memory cell 54 shown in (A) is realized. The shaded portion in FIG. 5 is a portion which is channel-doped by ion implantation and does not operate with a 5V power supply. Such channel dope is NMOS
By providing the access gates Ma and Mb composed of transistors, the channel width is limited from W to W / 2, and a circuit equivalent to that in FIG. 15A is realized without increasing the number of used gates.

FIG. 6 shows an embodiment in which the present invention is applied to an SRAM capable of writing with a single signal. (A) is a schematic plan view in which a part of the channel of the NMOS transistor is ion-implanted to limit the channel width. The shaded area is an area where ion implantation prevents operation with a 5V power supply. FIG. 6B is FIG. 6A.
Represents the equivalent circuit of. The write operation of the memory cell of FIG. 6 will be described. The threshold voltage of the inverter IN ₁ of the latch section is Vinv. Now, consider the case of writing "0" as data. In this case, the equivalent circuit can be expressed as shown in (C). At this time, the voltage Vm of the node M _1
1 is the on-resistances R ₁ and R ₂ of the related MOS transistors
From the relationship of: Vinv> V · R ₂ / (R ₁ + R ₂ ) (= Vm ₁ ) (1) If “1” can be satisfied, “0” can be written. When writing "1", the equivalent circuit is (D)
The on-resistances R ₂ and R _{3 of} the related MOS transistors can be expressed as follows: Vinv <VR ₂ / (R ₂ + R ₃ ) (= Vm ₁ ) ... (2) If satisfied, "1" can be written.

In FIG. 6 (A), the channel region of the NMOS transistor is limited by ion implantation. The width of the limitation depends on the relationship between the on-resistances of the respective MOS transistors expressed by the equations (1) and (2). It is set to satisfy. In one example, the channel width of the MOS transistor (left end) that serves as the access gate in FIG.
, The channel width of the NMOS transistor on the right side is limited to ⅕, and the channel width of the NMOS transistor on the right side is limited to ⅓.

An embodiment of the SRAM in which the initial state is set is shown in FIG. FIG. 7 shows a memory cell of a complete CMOS type SRAM together with an access MOS transistor. The equivalent circuit diagram of FIG. 7 is the one shown in FIG. This memory cell has a channel width adjusted so that binary "0" is set as an initial state. Figure 7
The shaded area is the normal power supply potential (eg 5V)
Is a region that is channel-doped so that the threshold voltage does not operate. This memory cell is a master slice type semiconductor integrated circuit device, and the basic channel width of each MOS transistor is W, and is adjusted to a predetermined channel width by performing channel doping. MOS
The channel width of the transistors Tr ₂ , Tr ₃ and Tr ₄ is limited to 2/3, and the channel width of Tr ₆ is limited to 1/3. Channel doping is not performed on Tr ₁ and Tr ₅ .

The operation of this embodiment will be described with reference to the equivalent circuit diagram of FIG. (A) is an example when "0" is set as the initial state, and (B) is an example when "1" is set as the initial state. However, in FIG. 8, the channel width is represented by a relative value. First, a case where a normal write operation is performed in these memory cells will be described. When writing "0", a low voltage is applied to the bit line BL, and a high voltage is applied to the other bit line BLB as its complementary signal.
The access gates Tr ₁ and Tr ₄ are turned on from the word line WL. The potential of the storage node M ₁ is determined by the on-resistance ratio of the MOS transistors Tr ₁ and Tr _2, and the potential of the node M ₁ is lower than the threshold voltage of the inverter formed by the MOS transistors T ₅ and T _6. Then, "0" is written. The write voltage can be changed by changing the transistor size of the MOS transistors Tr ₁ and Tr ₂ .

Further, the case of writing "1", the bit line BL to the high voltage, the other bit line BLB low voltage is applied, is from the word line WL access gate Tr ₁ and Tr ₄ are turned on .. In this case, by using complementary signals, the potential of the other storage node M ₂ is determined by the ratio of the on resistances of the MOS transistors Tr ₄ and Tr ₅ .
The potential of the node M ₂ is equal to that of the MOS transistors Tr ₂ and Tr.
_The voltage becomes lower than the threshold voltage of the inverter formed in ₃ and "1" is written. The write voltage can be changed by changing the transistor size of the MOS transistors Tr ₄ and Tr ₅ . By utilizing this difference in write voltage, the information in the memory cell can be set to the initial state at any time. That is, by setting the voltage of the data line (bit line) between the two write voltages, the information of the memory cell is set to the initial state determined by the size of each MOS transistor.

7 and 8 for setting the initial state to "0"
In (A), when the data line is set to the set voltage, the node M
The voltage of ₁ becomes lower than the threshold value of the inverter formed by the MOS transistors Tr ₅ and Tr ₆ , and the voltage of the node M ₂ becomes higher than the threshold value of the inverter formed by the MOS transistors Tr ₂ and Tr _3. The transistor sizes of the MOS transistors Tr _{1 to} Tr ₆ are set to. Further, in FIG. 8B in which the initial state is set to “1”, when the data line is set to the set voltage, the voltage of the node M ₁ is higher than the threshold value of the inverter formed by the MOS transistors Tr ₅ and Tr _6. Becomes higher and the voltage of the node M ₂ becomes MO.
Each MOS transistor Tr is set to be lower than the threshold value of the inverter formed by the S transistors Tr ₂ and Tr _3.
The transistor size of _{1 to} Tr ₆ is set. Figure 8
The channel dope pattern corresponding to (B) is a pattern symmetrical to that in FIG.

According to the present invention, instead of narrowing the channel width of the MOS transistor by channel doping in order to change the characteristics of the memory cell, the threshold voltage of the NMOS transistor and the PMOS transistor is set to a predetermined value within the range of operating at the power supply voltage. The initial state can be set by setting the value of. The adjustment of the threshold voltage in that case can be realized by performing a controlled amount of ion implantation over the entire channel.

Next, FIG. 9 shows a manufacturing process including ion implantation in the present invention. In the master process, a well is formed in a substrate, an active region is formed by a field oxide film, a gate oxide film is formed, a polysilicon film is deposited, and a gate electrode is formed by photolithography and etching. Further, the first layer metal wiring may be formed. Next, in the custom process, an ion implantation process for performing channel doping in the present invention to change the threshold voltage, control the effective channel width, and change the breakdown voltage is performed. A contact hole is formed in and a metal wiring is formed. Finally, a passivation film is formed and bonding pads are provided. The channel doping ion implantation step may be performed after the metal wiring is formed.

[0044]

According to the present invention as set forth in claims 1 to 3, since element isolation is performed by ion implantation, there is no field oxide film between adjacent basic gates of the same conductivity type, and the circuit is dense and flexible. A highly reliable master slice type semiconductor integrated circuit device can be obtained. In addition, M used for element isolation
Since it is not necessary to connect the gate electrode of the OS transistor to the power supply, wiring can be formed on the gate electrode, the gate electrode can be used for wiring, and the wiring efficiency is improved. According to the present invention of claim 4, since an element having a breakdown voltage lower than the gate breakdown voltage can be used as the protection element, the tolerance for surge is increased.

According to the present invention of claim 5, since a junction having zener breakdown characteristics can be formed, a diode having a small temperature dependency can be realized. Claim 7
According to the present invention, since a part of the MOS transistors forming the logic circuit is ion-implanted to narrow its effective channel width, a logic circuit having an arbitrary threshold voltage can be obtained with a small number of MOS transistors. Therefore, the circuit scale can be reduced. In addition, the same number of PMOS transistors and N logic circuits as the logic threshold voltage is changed.
Since the MOS transistors can be used, the number of unused MOS transistors that are not used is reduced, and the circuit scale can be improved in this respect as well. By reducing the effective channel width of the MOS transistor, power consumption is also reduced. According to the present invention of claim 8, the on-resistance of the access gate of the memory cell can be arbitrarily adjusted, so that it is possible to realize a high-speed memory that does not malfunction without increasing the number of used gates.

According to the present invention of claim 9, the transistor size in the memory cell of the SRAM formed on the master slice type semiconductor integrated circuit can be arbitrarily set.
It is possible to realize an SRAM capable of writing with a single signal, which realizes a high-density memory, without increasing the number of used gates. According to the present invention of claims 9 to 11, since the initial state of the SRAM can be set during the manufacturing process of channel doping, the manufacturing time can be shortened and the design can be performed without changing the circuit configuration of the memory cell itself. You can make changes. This can also be realized in the master slice type semiconductor integrated circuit device.

[Brief description of drawings]

FIG. 1 illustrates an embodiment in which the present invention is applied to element isolation, and (A), (B), and (C) represent different embodiments.

2A and 2B show an embodiment in which the present invention is applied to a protection element, FIG. 2A is a circuit diagram, and FIG. 2B is a diagram showing an injection amount and a withstand voltage.

3A and 3B show an embodiment in which the present invention is applied to control of an effective channel width. FIG. 3A is a schematic plan view, FIG. 3B is an equivalent circuit diagram thereof, and FIG. 3C is a PMOS transistor and NM.
It is a figure which shows the logic threshold voltage with respect to the ratio of the channel width of an OS transistor.

FIG. 4 shows another embodiment in which the present invention is applied to control of an effective channel width, (A) is a schematic plan view,
(B) is an equivalent circuit diagram thereof, and (C) is a diagram showing a relation between a bit line signal and a logical threshold voltage in the sense amplifier of the ROM.

FIG. 5 is a schematic plan view showing an embodiment in which the present invention is applied to an access gate of a memory cell.

FIG. 6 is a diagram showing an embodiment in which the present invention is applied to a single signal writable SRAM, FIG.
(B) is an equivalent circuit diagram thereof, (C) is an equivalent circuit diagram in a state where "0" is written, and (D) is an equivalent circuit diagram in a state where "1" is written.

FIG. 7 is a schematic plan view showing an embodiment in which the present invention is applied to an initial state SRAM.

FIG. 8 is an equivalent circuit diagram of an SRAM in an initial state setting,
(A) has binary "0" set as the initial state,
In (B), binary "1" is set as the initial state.

FIG. 9 is a process drawing showing the manufacturing process of the present invention.

10A and 10B are views showing conventional element isolation, in which FIG. 10A is a schematic plan view of element isolation by a field oxide film, and FIG. 10B is a schematic plan view of element isolation in which a gate electrode is connected to a power supply.

11A and 11B are diagrams showing a conventional protection circuit, in which FIG. 11A is a circuit diagram and FIG. 11B is a diagram showing a relationship between miniaturization of an element and breakdown voltage.

12A and 12B are diagrams when the circuit corresponding to FIG. 3A is configured with a conventional master slice, FIG. 12A is a schematic plan view, and FIG. 12B is an equivalent circuit diagram thereof.

FIG. 13 is a diagram showing an example of a case where the logic circuit corresponding to FIG. 4A is configured with a conventional master slice,
Is a schematic plan view thereof, and (B) is an equivalent circuit diagram thereof.

FIG. 14 is a diagram showing a static RAM, (A)
Is a circuit diagram showing one memory cell portion, (B) is a voltage diagram showing reading by the precharge method, and (C) is 1
FIG. 6 is an equivalent circuit diagram of a circuit including a plurality of access gates.

15A and 15B are diagrams of a conventional method showing a measure for preventing malfunction in the memory cell of FIG. 13, FIG. 15A is a schematic plan view showing an example of increasing the resistance of an access gate, and FIG. 15B is an NMOS of an inverter. It is a schematic plan view which shows the example which makes a transistor low resistance.

[Explanation of symbols]

2a gate electrode of MOS transistor used for element isolation 6a element isolation MOS transistor 8 controlled channel dope region 14 wiring on element isolation MOS transistor 18 wiring connected to gate electrode of element isolation MOS transistor 26, 28 Surge protection diode N, N ₁ , P ₂ , Tr ₂ , Tr ₃ , Tr ₄ , Tr ₆ MOS transistor with narrow channel width

 ─────────────────────────────────────────────────── ─── Continuation of front page (72) Inventor Seiji Yamanaka 1-3-6 Nakamagome, Ota-ku, Tokyo Stock company Ricoh Co., Ltd. (72) Hideyuki Aota 1-3-6 Nakamagome, Ota-ku, Tokyo Stock Company Ricoh

Claims (14)

[Claims] 1. A basic cell including a MOS transistor including a source / drain diffusion region formed on a semiconductor substrate and a gate electrode formed on a channel region between these regions via a gate insulating film. In a semiconductor integrated circuit device having a plurality of basic cell regions arranged side by side in the vertical and horizontal directions, a part or all of the channel region of at least one MOS transistor in the basic cell region is in the same basic cell. A semiconductor integrated circuit device having an impurity concentration different from that of channel regions of other MOS transistors of the same conductivity type. 2. The semiconductor integrated circuit device according to claim 1, wherein the MOS transistors having different impurity concentrations have a threshold voltage that does not operate at the power supply voltage of the semiconductor integrated circuit device and are used for element isolation. 3. The semiconductor integrated circuit device according to claim 2, wherein the gate electrodes of the MOS transistors having different impurity concentrations are used as wirings. 4. A basic cell including a MOS transistor comprising a source / drain diffusion region formed on a semiconductor substrate and a gate electrode formed on a channel region between these regions via a gate insulating film. In a semiconductor integrated circuit device having a plurality of basic cell regions arranged in the vertical and horizontal directions, at least one diffusion region is implanted with an impurity of a conductivity type opposite to that of the diffusion region in a deep and high concentration. A semiconductor integrated circuit device characterized in that the breakdown voltage of the PN junction between the diffusion region and the substrate is smaller than the breakdown voltage of other PN junctions of the same conductivity type. 5. The semiconductor integrated circuit device according to claim 4, wherein the PN junction having a reduced breakdown voltage is used as a surge protection element for a terminal portion. 6. The semiconductor integrated circuit device according to claim 4, wherein the PN junction having a reduced breakdown voltage exhibits zener characteristics. 7. A basic cell including a MOS transistor having a source / drain diffusion region formed on a semiconductor substrate and a gate electrode formed on a channel region between these regions via a gate insulating film. In a semiconductor integrated circuit device having a basic cell region formed by arranging a plurality of cells in the vertical and horizontal directions, a part of the channel of at least one MOS transistor is ion-implanted to reduce the effective channel width of the MOS transistor. A semiconductor integrated circuit device characterized by being provided. 8. The semiconductor integrated circuit device according to claim 7, wherein a MOS transistor having a narrowed effective channel width is used as an access gate of the memory cell. 9. A P-channel type MO on the same semiconductor chip.
In a static RAM formed on a master slice type semiconductor integrated circuit formed by arranging a plurality of basic cells composed of S transistors and N channel type MOS transistors in the vertical and horizontal directions, a pair of CMOS inverter circuits are provided with flip-flops. Ion implantation is performed on the channel of at least one MOS transistor of the access MOS transistors that are connected to the MOS transistors of the memory cells connected to each other and each storage node and use the word line signal as a gate input. A static RAM whose characteristics are changed and is set to an initial state when a predetermined voltage is applied from a bit line through an access MOS transistor. 10. In the ion-implanted MOS transistor, the ion-implantation is performed on a part of a channel region, and the ion-implanted part is set to a threshold voltage at which a channel is not normally formed at a power supply potential. 10. The static RAM according to claim 9, wherein the effective channel width is narrowed by ion implantation. 11. In the ion-implanted MOS transistor, the ion implantation extends over the entire channel region, and the threshold voltage of the MOS transistor reaches a predetermined value at which a channel is formed at a normal power supply potential. 10. The static RAM according to claim 9, which is applied as described above. 12. A P-channel type M on the same semiconductor chip.
At least one M in a static RAM formed on a master slice type semiconductor integrated circuit formed by arranging a plurality of basic cells composed of an OS transistor and an N channel type MOS transistor in the vertical and horizontal directions.
A part of the channel of the OS transistor is ion-implanted to narrow the effective channel width of the MOS transistor, and one bit line is connected to the latch portion of the memory cell via one access gate to write data. Static RAM whose operation is performed by a single signal. 13. A master process of forming a part of wiring between a source / drain diffusion region and a gate electrode, or a source / drain diffusion region and a gate electrode, and a custom process of forming a wiring. At least 1
A method of manufacturing a semiconductor integrated circuit device, comprising the step of controlling an impurity concentration of a part or all of a channel region of each MOS transistor to be different from that of a channel region of another MOS transistor of the same conductivity type. 14. The method for manufacturing a semiconductor integrated circuit device according to claim 10, wherein the step of controlling the impurity concentration is performed after the gate electrode is formed and before the wiring is formed or after the wiring is formed.