KR100201813B1 - Breaking curcuit and method of duble control in exchange system - Google Patents

Abstract

The present invention relaxes the limit voltage limit in nonvolatile memory devices such as flash type EEPROM, enables low voltage operation of, for example, about 3V, and attains high integration of the nonvolatile memory device.

A plurality of nonvolatile memory elements 4 formed by stacking the floating gate 14 and the control gate 17 between the output terminals of the data lines 38 and 39 and the ground terminal are formed in a source / drain region ( 22 through the gate insulating film 31 on the upper surface of the control gate 17, and the channel forming region 33 is formed on the upper surface of the control gate 17, and on both sides of the channel forming region 33 and the nonvolatile memory device. A source / drain region 34 for the thin film transistor formed by connecting to the source / drain region 22 is formed.

Description

Nonvolatile memory

1 is a schematic cross-sectional view of an embodiment.

2 is a layout diagram of an embodiment.

3 is a manufacturing process diagram of the embodiment.

4 is a manufacturing process diagram of the embodiment.

5 is a manufacturing process diagram of the embodiment.

6 is a manufacturing process diagram of the embodiment.

7 is a manufacturing process diagram of the embodiment.

8 is a manufacturing process diagram of the embodiment.

9 is a manufacturing process diagram of the embodiment.

10 is a manufacturing process diagram of the embodiment.

11 is a manufacturing process diagram of the embodiment.

12 is a manufacturing process diagram of the embodiment.

13 is a manufacturing process diagram of the embodiment.

14 is a layout diagram of a conventional example.

15 is a schematic cross-sectional view taken along the line A-A in FIG.

* Explanation of symbols for main parts of the drawings

1: EEPROM 4: Nonvolatile Memory

5: thin film transistor 14: floating gate

17: control gate 22: source / drain area

31 gate insulating film 33 channel formation region

34: source / drain area 36: output terminal side contact hole

37: Ground terminal side contact hole 38: Data line

39: data line

The present invention relates to a nonvolatile memory device such as flash EERPOM.

EEPROM (Electrically Erasable Programmable ROM) is an electronically erasable ROM that can simultaneously erase data written to a memory cell. This EERPOM does not need to erase the write data by irradiating ultraviolet rays like the EPROM at the time of rewriting of data, and it can be accommodated in a memory card or the like since the stored data can be written or written by an electric signal.

The EEPROM will be described in accordance with the schematic sectional view taken along the line A-A in FIG. 14 shown in the layout diagram of FIG. 14 and FIG.

The figure shows a flash-type EEPROM composed of a plurality of basic blocks of NAND type.

In other words, the device isolation region 54 is formed on the upper layer of the P-type silicon substrate 53 except for the transistor formation regions 51 and 52 in which the basic blocks are formed by the LOCOS method. Further, gate insulating films 55 and 56 of the nonvolatile memory device are formed on the upper surfaces of the silicon substrates 53 in the transistor formation regions 51 and 52.

In the transistor formation region 51, a floating gate formation pattern 57 is formed on an upper surface of the gate insulating film 55 on the side of the isolation region 54 (54a) and a part of the upper surface of the isolation region 54a. At the same time, the floating gate formation pattern 58 is formed in the transistor formation region 52 on the upper surface of the gate insulating film 56 on the side of the isolation region 54 (54b) and on the upper surface of the isolation region 54b.

In addition, the gate interlayer insulating films 59 and 60 are formed on the upper surfaces of the floating gate forming patterns 57 and 58. The upper surface of the silicon substrate 53 between the floating gate formation pattern 57 and the device isolation region 54a and the silicon between the floating gate formation pattern 58 and the device isolation region 54 (54c). The gate switching films 61 and 62 of the enhancement transistor are formed on the upper surface of the substrate 53.

Then, a poly-Si film to be a word line is formed on the entire surface of the floating gate forming patterns 57 and 58, and the word line and each floating gate 63 and 64 are self-aligned by photolithography and etching. It is formed by (自 體 自 合 的). This word line becomes the control gates 65 and 66 on the floating gates 63 and 64 and the transfer gates 67 and 68 on the gate insulating films 61 and 62.

In addition, when forming the plurality of control gates 65 and 66, the first selection gate 69 and the second selection gate 70 are also formed.

Further, a source / drain region of an LDD structure having an LDD diffusion layer (not shown) on top of each of the floating gates 63 and 64 and the silicon substrates 53 on both sides of the transfer gates 67 and 68. (71) and (72) are formed. The source region 75 is formed on the first select gate 69 on the silicon substrate 53 on the side opposite to the control gates 65 and 66.

In addition, an interlayer insulating film 76 is formed on the entire surface of the control gates 65 and 66 side, and contact holes 77 and 78 are disposed on the drain regions 73 and 74. Data lines 79 and 80 which are connected to the drain regions 73 and 74 through the contact holes 77 and 78 are formed.

However, in the EEPROM having the above structure, the nonvolatile memory element and the enhancement transistor are formed in an adjacent state. Therefore, since it is difficult to individually control and set the LDD diffusion layer concentrations of the source and drain regions of each transistor, the LDD diffusion layer concentrations of the respective transistors are set to the same concentration. As a result, since the timing of writing and the timing of erasing are shifted, it is difficult to stabilize timing characteristics.

In addition, when the LDD diffusion layer is formed at a normal concentration, the concentration of the LDD diffusion layer of the nonvolatile memory element is too thin and cannot be written. Further, when the concentration of the LDD diffusion layer is made thicker than usual to facilitate writing, the enhancement type transistor causes a malfunction due to the hot electron effect.

In the conventional EEPROM, when the control gate and the transfer gate are formed by etching and the gate interlayer insulating films on both sides of the control gate and the transfer gate are removed at the time of E, the gate insulating films on both sides of the transfer gate are also removed. Therefore, when the floating gate forming pattern is etched to form the floating gate, the silicon substrates on both sides of the transfer gate are also etched. As a result, grooves are formed in the silicon substrates on both sides of the transfer gate, so that the transfer gate has a so-called trench gate structure. Therefore, punch through is caused between the source and the drain of the transfer transistor. In addition, an offset occurs, and the transconductance gm and the load drive capacity β of the inverter cannot be sufficiently secured. Therefore, malfunctions such as delay in operation timing such as writing or erasing occur.

If the threshold voltage after writing is referred to as VthHigh and the power supply voltage is referred to as Vdd, VthHigh must fall within a range of 0 < VthHigh < Vdd. Since the normal power supply voltage Vdd is 5V, 0 < VthHigh < 5V. Therefore, VthHigh is set in the range of 2V ± 1V in consideration of the error. However, when Vdd is a low voltage of about 3V, VthHigh does not fall within the above limit. For example, if it is intended to fall within the above limit, VthHigh should be set in the range of approximately 1.5V ± 0.5V in consideration of the error.

As described above, when the EEPROM is manufactured by setting VthHigh to a narrow error range, VthHigh often becomes out of specification, which causes a very low yield. For this reason, mass production is low.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object thereof is to provide a nonvolatile memory device having excellent stability in writing and erasing in response to a low voltage power supply.

The present invention has been made to achieve the above object.

In other words, a plurality of nonvolatile memory elements formed by stacking a floating gate and a control gate are connected in series between the output terminal of the data line and the ground terminal through a source / drain region. A channel formation region is formed on the top surface of the control gate through a gate insulating film. Source and drain regions for thin film transistors are formed on both sides of the channel formation region while being connected to the channel formation region and the source and drain regions of the nonvolatile memory device. The gate of the thin film transistor is formed of the control gate.

In the nonvolatile memory device having the above-described structure, the source / drain region of the nonvolatile memory element and the source / drain region of the thin film transistor are formed separately, so that the LDD diffusion layer of the source / drain region of the thin film transistor and the source / drain region of the nonvolatile memory element is formed. Are individually conditioned. For this reason, since the nonvolatile memory element and the thin film transistor are individually controlled, timing shifts between writing and erasing are eliminated. As a result, writing of data or erasing of data can be performed stably without malfunction.

When erasing the write data, the threshold voltage of the nonvolatile memory device becomes a power supply voltage. At this time, the threshold voltage of the thin film transistor is about 0V. Therefore, the characteristics of the thin film transistor become dominant as the characteristics of the nonvolatile memory device. On the other hand, when writing data, the threshold voltage of the nonvolatile memory device becomes a negative power supply voltage. Therefore, the characteristics of the nonvolatile memory device become dominant as the characteristics of the nonvolatile memory device. As a result, the write data is erased when the threshold voltage after the write of the nonvolatile memory element is 0 V or more during erasing.

An embodiment of the present invention will be described according to the schematic sectional drawing of FIG. 1 and the layout of FIG. The schematic configuration sectional drawing is sectional drawing of the B-B line position in a layout diagram. In addition, a part is abbreviate | omitted in schematic sectional drawing and layout view.

In the drawing, as an example of the nonvolatile memory device, a flash type EEPROM 1 in which a plurality of NAND type basic blocks are arranged is shown.

As shown in FIG. 1 and FIG. 2, element isolation is performed on the upper layer of the P-type silicon semiconductor substrate 11 except for the transistor forming regions 2 and 3 forming the basic block. The region 12 is formed.

The gate insulating film 13 is formed in the upper layer of the semiconductor substrate 11 in each transistor formation region 2 and 3, respectively. Each gate insulating film 13 is formed to be 20 nm thick, for example.

A plurality of floating gates 14 (for example, eight) are formed on the top surface of the gate insulating film 13. Each floating gate 14 is made of, for example, polysilicon (hereinafter referred to as poly-si).

The gate interlayer insulating film 15 is formed to cover at least the upper surface of each of the floating gates 14. The gate interlayer insulating film 15 is formed with, for example, 1 nm in thickness.

The word line 16 is formed on the upper surface of the gate interlayer insulating film 15 on each of the floating gates 14 while crossing the transistor forming regions 2 and 3. The word line 16 becomes the control gate 17 on the floating gate 14. Each word line 16 in each of the transistor forming regions 2 and 3 is formed in a connected state.

The first select gate 18 and the second select gate 19 are disposed on both sides of the group of word lines 16. Further, the drain region 20 serving as the output terminal of the data line is disposed on the side opposite to the word line 16 group side with respect to the first selection gate, and is opposite to the word line 16 group side with respect to the second selection gate 19. Again, the source area 21 serving as the ground terminal of the data line is disposed.

In addition, the difference between the first selection gate 18 and the word line 16 (16a) is different from each word line 16 and between the second selection gate 19 and the word line 16 (16b). The source / drain region 22 of the LDD structure is formed.

As the LDD structure, LDD diffusion layers 23 into which N-type impurities are ion-implanted are formed in the upper layer of the semiconductor substrate 11 on both sides of each floating gate 14. The LDD diffusion layer 23 is formed to be thicker than the normal diffusion layer concentration.

In addition, side walls 24 are formed on the side walls of each floating gate 14 and each control gate 17. In addition, sidewalls 25 are formed on sidewalls of the first and second selection gates 18 and 19.

A semiconductor substrate between the sidewall 24 and another sidewall 24 adjacent to the sidewall 24 and between the sidewall 24 and the sidewall 25 adjacent to the sidewall 24. In the upper layer of (11), a source / drain diffusion layer 26 into which an N-type impurity is ion-implanted in a state deeper than that of the LDD diffusion layer 23 is formed. As described above, the source / drain region 22 is formed by the LDD diffusion layer 23 and the source / drain diffusion layer 26.

A gate insulating film 31 made of a silicon oxide film is formed on the upper surface of each control gate 17. The contact hole 32 is provided in the gate insulating film 31 on the source / drain diffusion layer 26. A poly-si film is formed on the entire surface between the first select gate 18 and the second select gate 19 on the gate insulating film 31 side. The channel forming region 33 is formed of a poly-si film on each control gate 17. In addition, a source-drain region 34 of the thin film transistor 5 is formed of a poly-si film on the source-drain region 22. These source and drain regions 33 are formed in a state of being connected to the source and drain diffusion layers 26 through the contact holes 32.

As described above, each of the transistor formation regions 2 and 3 has a gate insulating film 13, a floating gate 14, a gate interlayer insulating film 15, a coat roll gate 17, a source / drain region, respectively. The nonvolatile memory device 4 is composed of a gate transistor 17, a gate insulating film 31, a channel forming region 33, and a source / drain region 34 as a transfer transistor. The acting thin film transistor 5 is constructed.

For example, an interlayer insulating film 35 made of, for example, a silicon oxide film is formed on the entire surface of the thin film transistor 5 side by a chemical vapor deposition method, and the interlayer insulating film 35 on the drain region 20 is formed. The output terminal side contact hole 36 is disposed in the gate insulating film 31, and the ground terminal side contact hole 37 is disposed in the interlayer insulating film 35 and the gate insulating film 31 on the source region 21. The data lines 38 and 39 connected to the drain region 20 and the source region 21 through the contact holes 36 and 37 are formed of a conductor film such as aluminum alloy, for example.

Next, the operation of the EEPROM 1 will be described.

To erase the write data, a voltage higher than that of the drain diffusion layer 21 is applied to the control gate 17, and charge is applied to the floating gate 14 from the drain diffusion layer 20 through the gate insulating film 13 by using a tunnel phenomenon. Injection is performed.

On the other hand, data is written by grounding the control gate 17 and applying a high voltage to the drain diffusion layer 20 to generate a reverse tunnel phenomenon.

In the EEPROM 1 having the above-described configuration, the concentration of the LDD diffusion layer 23 can be set independently, so that the concentration of the LDD diffusion layer 23 can be set higher than that of the normal LDD diffusion layer. Therefore, current easily flows in the channel of the nonvolatile memory device 4, and writing becomes easy.

When the write data is erased, the threshold voltage of the nonvolatile memory element 4 is a power supply voltage, for example, 3V. The threshold voltage of the thin film transistor 5 is approximately 0V. Therefore, as the characteristic of the EEPROM 1, the characteristic of the thin film transistor 5 becomes dominant. On the other hand, when data is written, the threshold voltage of the nonvolatile memory device 4 becomes a negative power supply voltage, for example, -3V. The threshold voltage of the thin film transistor 5 becomes the threshold voltage at the time of erasing. Therefore, as the characteristic of the EEPROM 1, the characteristic of the nonvolatile memory element 4 becomes dominant. As a result, when the threshold voltage VthHigh after the writing of the nonvolatile memory element 4 is set to 0 V or more during erasing, the write data is erased.

Thus, for example, it is possible to use a low voltage power supply of about 3V. Moreover, since the range of VthHigh can be set widely, the product which falls outside the standard of VthHigh can be reduced and a yield can be improved.

Further, by forming the thin film transistor 5 on the nonvolatile memory device 4, the thin film transistor 5 serving as a transfer transistor does not have a so-called trench gate structure. Therefore, no biasing occurs in the channel forming region 33 of the thin film transistor 5. In addition, since the offset is not applied, the transconductance gm and the load driving capacity β of the inverter can be sufficiently secured. Therefore, no malfunction such as delay in operation timing such as writing or erasing occurs.

Next, a manufacturing method of the EEPROM 1 having the above-described configuration will be described according to the manufacturing process diagrams of FIGS. In the description of this manufacturing method, the EEPROM 1 is formed in the transistor formation region 2.

As shown in FIG. 3, the element isolation region 12 is formed on the upper layer of the semiconductor substrate 11 of P-type single crystal silicon except for the transistor formation region 2 by the conventional LOCOS method.

Thereafter, the silicon oxide film (not shown) or silicon nitride film (not shown) formed by the LOCOS method is removed by etching or the like.

Subsequently, a gate insulating film 13 made of a silicon oxide film is formed over the semiconductor substrate 11 in the transistor formation region 2 by, for example, a thermal oxidation method. The gate insulating film 13 is formed to be 20 nm thick, for example.

Then, as shown in FIG. 4, a polysilicon (hereinafter referred to as poly-Si) film is deposited on the entire surface of the device isolation region 12 side by, for example, chemical vapor deposition. Thereafter, a poly-Si pattern 41 for forming a floating gate is formed in a state of covering a part of the gate insulating film 13 by, for example, photolithography technique and etching. However, the poly-Si pattern 41 is not formed in the regions where the selection gates 18 and 19 (see FIG. 2) are formed.

Subsequently, the silicon oxide film 42 is formed to cover at least the poly-Si pattern 41 by, for example, chemical vapor deposition. The silicon oxide film 42 is formed to have a thickness of 1 nm, for example.

Next, as shown in FIG. 5, the poly-Si film 43 for forming the control gate is deposited on the entire surface of the silicon oxide film 42 side by, for example, chemical vapor deposition.

Subsequently, a resist mask 44 for forming the word lines 16 and the first and second selection gates 18 and 19 to be described later is formed by, for example, photolithography. Next, the poly-Si film 43 is etched using the resist mask 44 as an etching mask, and the poly-Si film 43 is crossed in the transistor forming region 2. The word line 16 and the first and second selection gates 18 and 19 are formed.

Further, the silicon oxide film 42 and the poly-Si pattern 41 are etched using the resist mask 44 as an etching mask.

As shown in FIG. 6, the gate interlayer insulating film 15 is formed of the silicon oxide film 42, and the floating gate 14 is formed of the poly-Si pattern 41. As shown in FIG.

The word line 16 on each floating gate 14 acts as a control gate 17.

Subsequently, as shown in FIG. 7, the device isolation region 12 and the resist mask 44 are used as ion implantation masks to form an LDD diffusion layer 23 to be described later, at a dose higher than the normal dose. I-type impurities are implanted into the upper layer of the semiconductor substrate 11. Then, the LDD diffusion layer 23 is formed.

Thereafter, the resist mask 44 is removed by an asher treatment or the like.

As shown in FIG. 8, the silicon oxide film 45 for forming sidewalls is deposited on the entire surface of the pattern forming side by, for example, chemical vapor deposition. Subsequently, the silicon oxide film 45 is anisotropically etched to remove the silicon oxide film 45 in the two-dot chain line portion. The sidewalls 24 are formed on sidewalls of the floating gate 14 and the word line 16 (including the control gate 17). In this case, sidewalls 25 are formed on both sides of the first and second selection gates 18 and 19. The gate insulating film 13 (broken line) and the upper layer portion (broken line) of the element isolation region 12 exposed by etching the silicon oxide film 45 are also removed by this etching.

Subsequently, as shown in FIG. 9, the device isolation region 12, each word line 15 (including the control gate 17), the first and second selection gates 18, 19 ) And the sidewalls 24 and 25 as ion implantation masks, for example, arsenic (As) as N-type impurities in a state deeper than the LDD diffusion layer 23 in the upper layer of the semiconductor substrate 11. Ion implantation.

The drain diffusion layer 20, the source diffusion layer 21, and the source / drain diffusion layer 26 are formed.

As described above, the source / drain diffusion layer 26 and the LDD diffusion layers 23 on both sides form the source / drain region 22.

Again, one gate insulating film 13, a floating gate 14 on the gate insulating film 13, a gate interlayer insulating film 15 on the floating gate 14, and a control gate on the gate interlayer insulating film 15. One nonvolatile memory element 4 is formed by the source 17 and the source / drain regions 22 on the upper side of the semiconductor substrate 11 on both sides of the floating gate 14.

Thereafter, as shown in FIG. 10, the silicon oxide film 46 is formed on the entire surface of the pattern forming side of the control gate 17 or the like by the chemical vapor deposition method. The silicon oxide film 46 on the control gate 17 becomes the gate insulating film 31 of the thin film transistor.

Subsequently, the silicon oxide film 46 (two dashed lines) on the source and drain regions 22 is removed by photolithography and etching to form the contact holes 32 on the source and drain diffusion sides 26. .

Next, as shown in FIG. 11, the poly-Si film 47 is deposited on the whole surface of the pattern formation side, such as the silicon oxide film 46, by the chemical vapor deposition method.

Subsequently, the poly-Si film 47 between the first and second select gates 18 and 19 is left by photolithography technique and etching, and the other poly-Si film (two-dotted line portion) 47 is removed. Remove

Next, as shown in FIG. 12, a resist is applied to the entire surface of the poly-Si film 47 side to form a resist film, and the resist film is subjected to photoresist and development. Then, an ion implantation mask 48 is formed leaving a resist film on the first and second selection gates 18 and 19 and on each control gate 17. Thereafter, arsenic (As) is ion-implanted as an N-type impurity by ion implantation to form a source / drain region 34 in the poly-Si film 47. This source / drain region 34 is connected to the source / drain region 22 of the memory transistor through the contact hole 32. In addition, the poly-Si film 47 on the control gate 17 becomes the channel forming region 33 of the thin film transistor.

As described above, one control gate 17, the gate insulating film 31 on the control gate 17, the channel forming region 33 on the gate insulating film 31, and the channel forming region 33 are formed. One thin film transistor 5 is formed by the source / drain regions 34 on both sides.

Thereafter, the ion implantation mask 48 is removed by an asher treatment or the like.

Subsequently, as shown in FIG. 13, an interlayer insulating film 35 (one dashed line portion) made of silicon oxide (SiO ₂ ) is formed on the entire surface of the pattern forming side by the chemical vapor deposition method, and the drain region 20 is formed. The contact terminal 36 on the output terminal side is disposed in the gate insulating film 31 and the interlayer insulating film 35 on the (). In addition, a ground terminal side contact hole 37 is disposed in the gate insulating film 31 and the interlayer insulating film 35 on the source region 21. Data lines 38 and 39 connected to the drain region 20 and the source region 21 through the respective output terminal side and ground terminal side contact holes 36 and 37 are formed on the upper surface of the interlayer insulating film 34. To form.

As described above, according to the present invention, a source / drain region for connecting to the source / drain region of each nonvolatile memory element is formed on each nonvolatile memory element as a gate. The thin film transistor was excreted. As a result, the LDD diffusion layer of the nonvolatile memory device and the source and drain regions of the thin film transistor can be set independently. Therefore, writing and erasing can be performed stably. In addition, since the threshold voltage does not have to be below the power supply voltage after writing, it is possible to cope with a low voltage power supply.

Further, since the thin film transistors are formed on each nonvolatile memory device, high integration can be achieved.

Claims (1)

A plurality of nonvolatile memory elements formed by forming a plurality of source / drain regions in series between an output terminal of the data line and a ground terminal, and stacking a floating gate and a control gate between each source / drain region; Channel formation regions are formed on the upper surface of the control gate through gate insulating films, and both source and drain regions for thin film transistors connected to both sides of the channel formation regions and the source and drain regions are formed on both sides of the channel formation regions. And a thin film transistor formed in the nonvolatile memory device.