JPH01144673A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To shield an electric field effect from a gate electrode, and to optimize each of the quantity of currents at the time of operation and the quantity of currents at the time of stand-by of a MISFET for load independently by forming the gate electrode for the MISFET for load to the upper section of a MISFET for drive in a memory cell and shaping the gate electrode so as to cover the inside of the memory cell. CONSTITUTION:A memory cell is formed to the main surface section of a p-type well region 2 shaped to the main surface section of an n<-> type semiconductor substrate 1 composed of single crystal silicon. A depletion layer is formed into a gate electrode (a polycrystalline silicon film) 14 by an electric field effect from a gate electrode 7 for a MISFETQd1 or Qd2 for drive, and the electric field effect from the gate electrode 7 is shielded by the gate electrode 14. A flip-flop circuit for the memory cell is changed into a complete CMOS type by shaping a channel forming region 17A, a source region 17C and a drain region 17B in a MISFETQp for load, the ratio of the quantity of currents at the time of operation to the quantity of currents at the time of stand-by of the FETQp can be increased, and power consumption is lowered. The FETQp is arranged to the upper section of the MISFETQd for drive, thus reducing the area of the memory cell, then improving the degree of integration.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a semiconductor integrated circuit device, and in particular, to a semiconductor integrated circuit device.
M (S tatic size anddom access
The present invention relates to a technique that is effective when applied to a semiconductor integrated circuit device having memory.

[Conventional technology]

In SRAM, memory cells are arranged at the intersections of complementary data lines and word lines. The memory cell is composed of a flip-flop circuit and two transfer MISFETs each having one semiconductor region connected to a pair of input/output terminals of the flip-flop circuit.

The flip-flop circuit includes two driving MISFEs.
It is composed of T and two high resistance load elements and is used as an information storage section. The high-resistance load element is made of a polycrystalline silicon film into which impurities that reduce the resistance value are not introduced or are slightly introduced. High resistance load elements are
It is arranged above the gate electrode of the driving MISFET.

The gate electrode of the transfer MISFET of the memory cell is connected to the word line. The other semiconductor region of the transfer MISFET is connected to the complementary data line.

The memory cell configured in this way has a driving MISFE
Since the high resistance load element is placed above the T, the occupied area can be reduced and the SRAM can be highly integrated.

The above-mentioned SRAM is described in Nikkei McGraw-Hill, Inc., Nikkei Elec 1 Heronics, December 30, 1985 issue, pages 117 to 145.

[Problem that the invention seeks to solve]

As a result of studying the above-mentioned high integration of SRAM, the present inventor found that the following problems occur.

When the size of a memory cell is reduced due to the high integration of the SRAM, the size of a high resistance load element is proportionally reduced. Since the high resistance load element is a passive element, a current flows relatively constantly. In other words, SR that aims to reduce power consumption
In AM, in order to reduce standby current (standby current), the size of high resistance load elements is reduced and the resistance value thereof is increased.

However, increasing the resistance of the high resistance load element reduces the amount of current delivered to the storage node of the single flip-flop circuit. The stored charge is gradually lost due to storage node leakage current and MOS tailing current, and if this current is greater than the supply current, the information stored in the memory cell will be reversed, especially at low voltage (retention). Because this is easy to do, SRAM malfunctions occur frequently.

Further, since the high resistance load element is arranged above the gate electrode of the driving MI S FET, the resistance value tends to fluctuate due to the electric field effect from the gate electrode. In other words, it is difficult to optimize the resistance value of the high resistance load element.

Furthermore, as the size of memory cells decreases due to higher integration of SRAMs, the amount of charge stored in the information storage section (storage node of the flip-flop circuit) decreases. Therefore, soft errors in the SRAM occur frequently due to the incidence of α rays.

SUMMARY OF THE INVENTION An object of the present invention is to provide a technology that can achieve higher integration of SRAM and lower power consumption.

Another object of the present invention is to achieve the above object and to
An object of the present invention is to provide a technology that can optimize load elements of AM memory cells.

Another object of the present invention is to achieve the above object and to
The object of the present invention is to provide a technique that can prevent AM rough 1 errors.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means for solving problems]

A brief overview of typical inventions disclosed in this application is as follows.

In an SRAM, a gate electrode of a load MISFET connected to the drain region of the drive MISFET is provided in the second part of the memory cell drive MISFET, and a goo-1 insulating film is interposed over the gate electrode of the load MISFET. Then, a channel forming region, a source region, and a train region of the load MISFET are provided.

Furthermore, the gate electrode of the load MISFET is connected to the drive MISFET.
Provided above the gate electrode of the I S FET.

Further, the gate electrode of the load MISFET is provided so as to cover the inside of the memory cell.

[For production]

According to the dual means, the flip-flop circuit of the memory cell can be completely 0MO3 type, and the ratio between the operating current amount and the standby current amount of the load element can be increased, thereby reducing power consumption. MISFE for driving
Since the load MISFET is arranged above the T, the memory cell area can be reduced and the SRAM can be highly integrated.

In addition, since the electric field effect from the gate electrode of the drive MISFET can be shielded, the load MISFET
It is possible to independently optimize the amount of current during operation and the amount of current during standby.

Furthermore, since the amount of charge stored in the information storage section of the memory cell (storage node of the flip-flop circuit) can be increased, rough 1-errors can be prevented.

Hereinafter, the configuration of the present invention will be explained along with examples.

In addition, in an attempt to explain the embodiments, parts having the same functions are given the same reference numerals, and repeated explanation thereof will be omitted.

[Embodiments of the invention]

(Example I) FIG. 3 (equivalent circuit diagram) shows a memory cell of an SRAM which is Example I of the present invention.

As shown in FIG. 3, the SRAM memory cells are arranged at the intersections of complementary data lines DL, DL and word lines WL. Complementary data lines DL extend in the row direction. The word line WL extends in the column direction.

The memory cell is composed of a flip-flop circuit and two transfer MISFETs Qt and Qt2, each of which has one semiconductor region connected to its pair of input/output terminals.

The transfer M I S F E T Q tz + Q
Each of t2 is constructed of an n-channel type. The other semiconductor region of each of the transfer MISFETs Qt□ and Qt2 is connected to the complementary data line DL. MIS for transfer
FErQt1. Each gate electrode of Qt2 is connected to the word line W
Connected to L.

The flip-flop circuit is configured as an information storage section (having an information storage notebook section). The flip-flop circuit consists of two driving MISFETs Qd□ and Qd2 and 2.
It is composed of two load MISFETs Qp and QP2. Drive MISFETs Qd and Qd2 are n-channel type, and load MISFETs QP+ and QP
? , are constructed of P-channel type. In other words, the flip-flop circuit is made up of a complete CMOS (full CMO8).

The source regions of the driving MISFETs Qd□ and Qdz are connected to a reference voltage SS. Reference voltage Vs
For example, s is the ground potential of the circuit, 0 [V]. The drain region of drive MISFET Qd1 is connected to the load MISFET Qd1.
Drain region of ETQP, transfer MISFET
One semiconductor region of Q tz, driving MISFET Qd
, and the gate electrode of the load MISFET Qp2. The drain region of the drive MISFET Qd2 is the drain region of the load MISFET Q p2, one semiconductor region of the transfer MISFET Qt□, the gate electrode of the drive MISFET Qd, and the load M
It is connected to the gate electrode of ISFETQp. The source regions of the load MISFETs Qp, QP2 are at the power supply voltage V. Connected to C. Power supply voltage ■. 0 is, for example, the operating voltage of the circuit 5 [V].

Next, the structure of a specific memory cell of an SRAM configured in this way will be explained using FIG. 2 (plan view) and FIG. 1 (cross-sectional view taken along the line 1-1 in FIG. 2). Explain briefly.

As shown in FIGS. 1 and 2, the memory cell is provided on the main surface of a P-type well region 2 formed on the main surface of an n-type semiconductor substrate 1 made of single crystal silicon. Although not shown, an n-type well region is provided on the main surface of the semiconductor substrate 1 in a region different from the p-type well region 2. A field insulating film 3 and a p-type channel stopper region 4 are provided on the main surface of the well region 2 between memory cells or between each element constituting the memory cell.

Each of the field insulating film 3 and the channel stopper region 4 is configured to electrically isolate between memory cells or between elements forming the memory cells.

Each of the memory cell transfer MISFETs Qt + Qt is surrounded by a field insulating film 3 and a channel stopper region 4, as shown in FIGS. It is formed on the main surface of the well region 2 in the area where the wafer is formed. That is, the transfer M
Each of I S FETQtl and Q1l-t2 mainly includes a well region 2, a gate insulating film 5,
It is composed of a gate electrode 7, a pair of n-type semi-sensitive regions 9 serving as a source region and a drain region, and a pair of n+-type semiconductor regions 11.

Well region 2 is used as a channel forming region.

The gate insulating film 5 is composed of a silicon oxide film formed by oxidizing the main surface of the well region 2.

The gate electrode 7 is formed on a predetermined upper part of the gate insulating film 5. The gate electrode 7 is composed of a composite film in which a high melting point metal silicide film (W S 12) 7B is laminated on top of a polycrystalline silicon film 7A. The polycrystalline silicon film 7A is C
An n-type impurity (P or As) is introduced which is deposited by VD and reduces the resistance value.

The high melting point metal silicide film 7B is deposited by sputtering or CVD. The gate electrode 7 made of this composite film has a resistivity value that is 10% lower than that of a single layer of polycrystalline silicon film.
It is possible to increase the operating speed. Further, since the upper layer of the gate electrode 7 is composed of the high melting point metal silicide film 7B, the upper layer of the gate electrode 7 is made of polycrystalline silicon film (1
Regardless of the conductivity type of the impurity introduced in 4 and 17B), ohmic connection can be made when connecting to the upper layer polycrystalline silicon film.

Transfer MISFETQt1. ．． Each gate electrode 7 of Qt2 is configured integrally with a word line (WL) 7 extending in the column direction. Word line 7 is provided on field insulating film 3 .

Further, the gate electrode 7 is made of a high melting point metal silicide (MoSi) other than the above-described one on the top of the polycrystalline silicon film 7A.

TaSi2. TiSi, ) film or high melting point metal (Mo,
Ta, Ti.

W) It may be composed of a composite film made of laminated films. Further, the goo 1 electrode 7 may be composed of a single layer of a polycrystalline silicon film, a high melting point metal film, or a high melting point metal silicide film.

The semiconductor region 9 with a low impurity concentration is formed integrally with the semiconductor region 11 with a high impurity concentration, and is provided on the channel formation region side in the main surface portion of the well region 2 . The semiconductor region 9 with a low impurity concentration is used for transfer MISFETs Qt, , Q
Each of t2 is so-called LDD (Fively Dope
d Draj-n) structure. The semiconductor region 9 with a low impurity concentration is configured in self-alignment with the gate electrode 7.

The highly impurity-concentrated semiconductor region 11 is self-aligned with the sidewall spacer 10 formed on the sidewall of the gate I electrode 7 .

Each of the memory cell driving MI 5FETs Qd, . That is, each of the driving MISFETs Qd and Qd2 is connected to the well region 2.
, a gate insulating film 5, a gate electrode 7, a pair of n-type semiconductor regions 9 and a pair of n-type semiconductor regions 11, which are source and drain regions. Drive MI 5F
Each of ETQd, ,Qd, is configured with an LDD structure.

One end of the gate electrode 7 of the driving MISFET Qd1 passes through the connection hole 6, and connects to one semiconductor region 11 of the transfer MISFET Qt□ with an n-type semiconductor region 8 interposed therebetween.
It is connected to the. Similarly, drive MISFETQd2
One extending end of the gate electrode 7 passes through the connection hole 6,
Transfer MISFETQ with n-type semiconductor region 8 interposed
It is connected to one semiconductor region 11 of t2. The connection hole 6 is formed in the gate insulating film 5. Semiconductor region 8 is composed of an n-type impurity diffused from polycrystalline silicon film 7A below gate electrode 7 to the main surface of well region 2 through connection hole 6.

The other end of the gate electrode 7 of the driving MISFET Qd passes through the connection hole 6 and is connected to the semiconductor region 11, which is the drain region of the driving MISFET Qd, with an n'-type semiconductor region 8 interposed therebetween. There is. Drive MISFET
The semiconductor region 11 which is the drain region of Qd□ and the transfer M
It is constructed integrally with one semiconductor region 11 of ISFETQt2.

A data line (DL) 20 is connected to the other semiconductor region 11 of each of the transfer MISFETs Qt□1Qj2 through a connection hole 19 formed in an interlayer insulating film 18. The data line 20 is configured to extend in the row direction above the interlayer insulating film 18. The data line 20 is made of, for example, an aluminum film or an aluminum alloy film added with Cu or Si to prevent migration.

Drive MI 5FETQd1. A reference voltage Vss is applied to the semiconductor region 11 which is the source region of each Qd2. Although not shown, the reference voltage Vss is supplied by a reference voltage wiring formed of the same conductive layer as the gate electrode 7 and the word line 7 and extending in the same column direction. This reference voltage wiring is connected to the drive MISFET Qd1. through the connection hole 6 formed in the gate insulating film 5.
It is connected to the semiconductor region 11 which is the source region of each Qd2.

The memory cell load MISFETQp□ is the driving MIS
It is configured on the top of the FETQd structure. MISF for load
ETQP is configured above the driving MISFETQd2. In other words, the load MISF E T Qp□
rQpz mainly includes the gate electrode 14, the gate insulating film 15, the channel forming region 17A, and the train region 17.
B and a source region 17C.

As shown in detail in FIG. 5 (plan view in a predetermined manufacturing process), gate 1 to electrode 14 of the load MISFET Qp
is configured to cover the upper part of the gate electrode 7 of the driving MISFET Qd1. An interlayer insulating film 12 is provided between the gate electrode 14 and the gate electrode 7. The gate electrode 14 of the load MISFET Qp□ is connected to the driving MISFET through the connection hole 13 formed in the interlayer insulating film 12
High melting point metal silicide 1 of gate electrode 7 of SFETQd1
It is connected to the surface of membrane 7B. Therefore, the gate electrode 14 of the load MISFET QP□ is the gate electrode 7
It is connected to the semiconductor region 11, which is the drain region of the driving MISFET Qd2, with the transistor Qd2 interposed therebetween. Similarly, the gate electrode 14 of the load MISFET QP2 is
It is configured to cover the upper part of the gate electrode 7 of the driving MISFET Qd2. Load MIS
The gate electrode 14 of FET Q p2 is connected to the connection hole 1
3 to the surface of the high melting point metal silicide film 7B of the gate electrode 7 of the driving MISFET Q d2. Therefore, M I S F E T Q for the load
The gate electrode 14 of P2 is a driving MISFET formed integrally with one semiconductor region 11 of the transfer MISFET Qt2.
It is connected to the semiconductor region 11 which is the drain region of SFETQd1.

This gate electrode 14 is composed of a polycrystalline silicon film into which impurities are introduced to reduce the resistance value. An n-type impurity (As or P) is introduced into this polycrystalline silicon film. Since the gate electrode 14 is made of a polycrystalline silicon film doped with n-type impurities, the driving MI 5FET Qd1. Qd2
The ohmic characteristics are not impaired when connecting to the respective gate electrodes 7 or the D'' type semiconductor region 11. That is, the gate electrode 14 made of a polycrystalline silicon film into which n-type impurities are introduced has a characteristic that it is easy to connect.

In addition, when the gate electrode 14 is formed of a polycrystalline silicon film doped with n-type impurities (B), a high melting point metal silicide film 7B is interposed between the semiconductor regions 11 and 11 in order to uniformly insert the parasitic diodes. Alternatively, it is connected to the gate electrode 7. n
The gate electrode 14, which is made of a polycrystalline silicon film into which type impurities have been introduced, is more suitable for loading MIS than in the case of an n-type gate electrode.
The threshold voltage of each of FETQpi, Ql)2 can be lowered. This decrease in threshold voltage is caused by the load MI
Since the amount of impurity introduced into the channel forming region 17A of each of SFETQps and +Qp2 can be reduced, it becomes easier to control the amount of impurity introduced.

Further, as a result of basic research by the present inventor, it has been found that when the gate electrode 14 is formed with a film thickness of about 1,000 mm or more,
The gate electrode 14 (polycrystalline silicon film) is caused by the electric field effect from the gate electrode 7 of the driving MISFET Qd1 or Qd.
It was confirmed that a depletion layer was formed inside the gate electrode 14 and that the electric field effect from the gate electrode 7 could be shielded by the gate electrode 14. Therefore, the gate electrode 7 has the above thickness.

Further, the gate electrode 14 is not limited to a polycrystalline silicon film,
It may be composed of a single layer of a high melting point metal silicide film or a high melting point metal film. In this case, the conductivity type of the conductive layer connected to the gate electrode 14 is irrelevant.

The gate electrode 14 is stretched to cover the inside of the memory cell in order to increase the amount of charge storage in the storage node portion of the flip-flop circuit.

The gate insulating film 15 is composed of a silicon oxide film deposited by CVD.

As shown in detail in FIG. 6 (plan view in a predetermined manufacturing process), the channel forming region 17A is formed by forming the gate insulating film 15.
It is formed at a predetermined upper part of. Channel forming region 17
A is composed of an l-type polycrystalline silicon film into which no impurity to reduce the resistance value is introduced, or into which a small amount of n-type impurity is introduced.

The drain region 17B is formed integrally with one end side of the channel forming region 17A, and is formed of an n-type polycrystalline silicon film doped with an n-type impurity. The train region 17B is connected to the gate insulating film 15 (channel forming region 17A).
It is connected to the gate electrode 14 through a connection hole 16 formed in a portion other than the portion used as an interlayer insulating film.

Since each of the drain region 17B and the gate electrode 14 is made of an n-type polycrystalline silicon film as described above, the drain region 17A and the gate electrode 14 can be ohmically connected.

The source region 17C is formed integrally with the other end side of the channel forming region 17A, and is formed of an n-type polycrystalline silicon film doped with an n-type impurity. Source region 17C is configured integrally with power supply voltage wiring Vcc extending in the column direction.

As described above, each of the load MISFETQP□1QP2 has a drain region 17B and a channel forming region 17B.
The conductivity types of A and the source region 17C are n-1-p structure. Load MIS configured with this structure
Each of FETQPlrQP2 has a characteristic that it is easy to make an ohmic connection between the drain region 17B and the gate electrode 14.

In addition, the load M I S F E T Q P1+ Q
In each of P2, the conductivity type of the drain region 17B, channel forming region 17A, and source region 17G may be configured to have a p-1-p structure. Load MI configured with this structure
Each of the SFE T Q pt and + Q P2 has a feature that makes it easy to establish an ohmic connection between the drain region 17B and the gate electrode 14 when the gate I-electrode 14 is formed of a P-type polycrystalline silicon film.

Load M I S F E T Q Pi l Q P
In each case, the amount of current flowing from the source region 17C to the 1-rain region 17B can be controlled by controlling the voltage applied to the electrode 14. MI for load
S F E T QPl.

Since each QP2 is a complete switch element, the power supply voltage V Q C is applied to the storage node portion of the flip-flop circuit.
The amount of current during supply (during operation) and the power supply voltage V
Ratio to the amount of current when CC is not supplied (standby) (
○N/○FF ratio) can be increased.

In other words, each of the load MISFETs Qp□+QP2 can increase the amount of current during operation, and can significantly reduce the amount of current during standby.

In this way, in the SRAM, the driving MISF E
A load MISFET connected to the drain region (semiconductor region 11) of the drive MISFET Qd on the top of TQd.
Qp gate electrode 14 is provided, and this load MISFET
A channel forming region 17 of the load MISFET QP is formed with a gate insulating film 15 interposed above the gate electrode 14 of the Qp.
A. By providing the source region 17C and drain region 17B, the flip-flop circuit of the memory cell is made into a complete CMO8 type, and the load element (MI 5FETQp for load)
), it is possible to increase the ratio between the operating current landscape and the standby current amount, thereby reducing power consumption.
Since Qp is arranged, the memory cell area can be reduced and high integration can be achieved.

Furthermore, by providing the gate electrode 14 of the load MISFET QP above the gate electrode 7 of the drive MISFET Qd, it is possible to shield the electric field effect from the gate electrode 7 of the drive MISFET Qd.
The operating special current amount and the standby current amount of the SFE4Qp can be independently optimized.

In addition, by configuring the gate electrode 14 of the load MISFET Qp to extend within the memory cell so as to cover the memory cell, the information storage section (flip-flop) of the memory cell is Since the amount of charge stored in the storage node section of the circuit can be increased, errors in the software 1 can be prevented. By preventing errors in the software 1, the memory cell area can be further reduced, so that higher integration of the SRAM can be achieved.

Next, regarding the method for manufacturing the SRAM memory cell,
Figures 7 to 13 (cross-sectional views of main parts shown for each manufacturing process)
Let's briefly explain using.

First, an n-type semiconductor substrate 1 made of single crystal silicon is prepared.

Next, a well region 2 is formed on the main surface of the semiconductor substrate 1 in each of the memory cell formation region and the n-channel MISFET formation region of a peripheral circuit (not shown).

Next, a field insulating film 3 and a p-type channel stopper region 4 are formed on the main surface of the well region 2 between each element of the memory cell.

Next, as shown in FIG. 7, a gate insulating film 5 is formed on the main surface of the well region 2 in each element forming region of the memory cell. Gate insulating film 5 is formed of a silicon oxide film formed by oxidizing the main surface of well region 2 . Gate insulating film 5
is formed to have a thickness of, for example, about 250 to 350 [people].

=24- Next, as shown in FIG. 8, connection holes 6 are formed. The connection hole 6 can be formed by partially removing the gate insulating film 5 at a portion where the gate electrode (7) is directly connected to the main surface of the well region 2.

Next, as shown in FIG. 9, the gate electrode 7, the word line 7
(not shown) and reference voltage wiring (not shown) are formed. The gate electrode 7 is formed of a composite film in which a high melting point metal silicide film 7B is laminated on two parts of the polycrystalline silicon film 7A. The polycrystalline silicon film 7A is deposited by CVD, and P, which is an n-type impurity, is introduced to reduce the resistance value. Polycrystalline silicon film 7A
is formed with a film thickness of, for example, about 2000 to 3000 [A]. The high melting point metal silicide film 7B is deposited by sputtering. For example, the high melting point metal silicide film 7B is 2500 to 3
It is formed with a film thickness of about 500 [people]. Polycrystalline silicon film 7A
The high melting point metal silicide film 7B is patterned by anisotropic etching such as RIE.

Next, as shown in FIG. 10, an n-type semiconductor region 9 to be used as part of the source region and drain region is formed. The semiconductor region 9 has, for example, 1013 [atoms/c
It can be formed by introducing P of about 40 to 60 [K a V] by ion implantation with an energy of about 40 to 60 [K a V]. When introducing this impurity, the gate electrode 7 and field insulating film 3 are mainly used as a mask for impurity introduction. Therefore, the half-quad region 9 can be formed in self-alignment with the gate electrode 7.

Further, as shown in FIG. 10, an n' type semiconductor region 8 is formed on the main surface of the well region 2 to which the gate electrode 7 is connected through the connection hole 6. Semiconductor region 8 can be formed by thermally diffusing n-type impurities introduced into polycrystalline silicon film 7A under gate electrode 7 into the main surface of well region 2. The semiconductor region 8 is formed, for example, by the same heat treatment process used to activate the high melting point metal silicide film 7B on the gate electrode 7.

Next, a sidewall spacer 1 is placed on the sidewall of the gate electrode 7.
form 0. The sidewall spacer 10 can be formed by depositing a silicon oxide film by CVD so as to cover the gate electrode 7, and then subjecting the silicon oxide film to anisotropic etching such as RIE.

Next, as shown in FIG. 11, an n+ type semiconductor region 11 to be used as a source region and a drain region is formed. The semiconductor region 11 is, for example, 1015 to 1016 [ato
ms/cm2 of As at 40-60 [K e V]
It can be formed by ion implantation with a certain amount of energy. When introducing this impurity,
Mainly, the gate electrode 7, field insulating film 3, and sidewall spacer 10 are used as a mask for impurity introduction. Therefore, the semiconductor region 11 can be formed in self-alignment with the sidewall spacer 10. By forming this semiconductor region 11, the transfer MIS
FETQt1. Each of Qt2 and driving MI 5FET
Qd1. , Qd2 are completed.

Although not shown, a p-channel M constituting the peripheral circuit
P+ type semiconductor regions, which are the source and drain regions of the ISFET, are formed after the step of forming the semiconductor region 11.

Next, an interlayer insulating film 12 is formed over the entire surface of the substrate including the upper part of the gate electrode 7. The interlayer insulating film 12 is formed of a silicon oxide film deposited by CVD and having a dense film quality. The interlayer insulating film 12 has a thickness of 300 to 1,500 to alleviate the growth of the step shape and improve the step coverage of the upper conductive layer.
Formed with a film thickness as thin as [a person].

Next, the interlayer insulating film 12 is partially removed at the connection portion between the gate electrode 7 and the gate electrode (14), and the connection hole 1 is removed.
form 3.

Next, as shown in FIG. 12, a load MISFET Q pl is connected to the gate electrode 7 through the connection hole 13.
Each gate electrode 14 of t Q P2 is formed.

The gate electrode 14 is formed of a polycrystalline silicon film deposited by CVD. The gate electrode 14 is formed to have a thin film thickness of, for example, about 1000 to 1500 [people]. The gate electrode 14 is 101
5-101″ [atoms/an2 pieces of P is 20-
It is introduced by ion implantation with an energy of about 40 [K e V].

That is, the gate electrode 14 is formed of an n-type polycrystalline silicon film.

Next, a gate insulating film 15 is formed over the entire surface of the substrate so as to cover the gate electrode 14. The gate insulating film 14 is formed of, for example, a dense silicon oxide film deposited by CVD. The gate insulating film 15 is formed to have a thickness of, for example, about 200 to 400 [people].

Next, as shown in FIG. 13, a load MISFET Q px r Q
A channel forming region 17A, a drain region 17B, and a source region 17C (including power supply voltage wiring) of P2 are sequentially formed. Channel forming region 17A, drain region 1
The source region 7B and the source region 17C are formed of, for example, a polycrystalline silicon film deposited by CVD, and have a thickness of about 650 to 2000 [A]. The channel forming region 17A is formed by forming a B of about 101° [atoms/an2] on a polycrystalline silicon film, for example.
F2 is introduced by ion implantation with an energy of about 50 to 70 [KeV] to form a "" type (slightly P type). The drain region 17B is formed, for example, in a polycrystalline silicon film with a thickness of 101" [at
oms/■ 2 pieces of As 50 to 70 [K e V]
It is introduced by ion implantation with a certain energy to form an n-type. The source region 17C is made of, for example, a polycrystalline silicon film of 10"
'[at.

ms/am2] about 50-70[K e V
] and formed into a p-type.

By forming the channel forming region 17A, drain region 17B, and source region 17C, the load M
I S F E T Qp+ and QP2 are completed.

Next, an interlayer insulating film 18 is formed over the entire surface of the substrate. The interlayer insulating film 18 is formed of, for example, a composite film in which a PSG film deposited by CVD is formed on a silicon oxide film deposited by CVD. After this, a connection hole 19 is formed in the interlayer insulating film 18.

Next, as shown in FIGS. 1 and 2, the connection hole 19
The interlayer insulating film 1 is connected to the other semiconductor region 11 of each of the transfer M5FETQt□1Qt2 through the
A data line 20 is formed in the second part of the 8th part.

By performing these series of manufacturing steps, the SRAM memory cell of this embodiment is completed.

(Example ■) The SRAM memory cell of Example ■ of the present invention was
Shown in figure (plan view).

As shown in FIG. 14, the SRAM memory cell basically has the same structure as the memory cell shown in Example I above. Load MISFET Q Pi + Q
Each gate electrode 14 of P2 is connected to the drive MISFET Qd, , Qd at the shortest distance without being routed around inside the memory cell.
The semiconductor region 11 is the drain region of each of the semiconductor regions 2 and 2. Gate electrode 14 is MISFETQp□ for load
, QP2 are formed only in the channel forming region 17A portion of each. Therefore, the memory cell of Example H has a simple structure.

As above, the invention made by the present inventor has been specifically explained based on the above embodiments, but the present invention is not limited to the above embodiments, and can be modified in various ways without departing from the gist thereof. Of course.

〔Effect of the invention〕

Among the inventions disclosed in this application, the effects that can be obtained by typical ones are as follows.

In the 3RA, it is possible to achieve high integration and low power consumption.

Furthermore, it is possible to optimize the load elements of SRAM memory cells.

Further, rough 1 to SRAM errors can be prevented.

[Brief explanation of the drawing]

FIG. 1 is a sectional view of a main part of a memory cell of an SRAM which is Embodiment I of the present invention, FIG. 2 is a plan view of the memory cell, FIG. 3 is an equivalent circuit diagram of the memory cell, and FIG. 6 to 6 are plan views of the memory cell in predetermined manufacturing steps, FIG. 7 to 13 are sectional views of main parts shown in each manufacturing step of the memory cell, and FIG. 14 is a plan view of the memory cell according to the present invention. FIG. 3 is a plan view of a memory cell of SRA, M which is Example 2; In the figure, 5, 15 - Insulating film, 7, 14... Gate electrode, 8, 9. 11 Semiconductor region, 17A - Channel forming region, 17B... Drain region, 17C Source region, DL, 20... Data line, WL, 7... Word line, Q ji + Q j2... MISFET for transfer
, Qd1. Qd2...Drive MISFET, QP□+
QP2... is a load MISFET.

Claims (1)

[Scope of Claims] 1. A semiconductor integrated circuit device having an SRAM composed of a memory cell composed of a flip-flop circuit composed of a drive MISFET and a load MISFET, and a transfer MISFET, wherein the drive MISFET A gate electrode of the load MISFET connected to the drain region of the drive MISFET is provided on the top of the load MISFET.
A semiconductor integrated circuit device characterized in that a channel forming region, a source region, and a drain region of a load MISFET are provided with a gate insulating film interposed above a gate electrode of the SFET. 2. The gate electrode of the driving MISFET is a single layer of a polycrystalline silicon film, a high melting point metal film, or a high melting point metal silicide film, or a stack of a high melting point metal film or a high melting point metal silicide film on a polycrystalline silicon film. The semiconductor integrated circuit device according to claim 1, wherein the semiconductor integrated circuit device is made of a composite film. 3. The semiconductor according to claim 1 or 2, wherein the gate electrode of the load MISFET is composed of a polycrystalline silicon film, a high melting point metal film, or a high melting point metal silicide film. Integrated circuit device. 4. The gate electrode of the load MISFET is comprised of a polycrystalline silicon film into which an n-type impurity or a p-type impurity is introduced.
Each of the semiconductor integrated circuit devices described in . 5. The semiconductor integrated circuit according to each of claims 1 to 4, wherein the channel forming region, source region, and drain region of the load MISFET are made of a polycrystalline silicon film. circuit device. 6. A p-type impurity is introduced into the polycrystalline silicon film that becomes the source region of the load MISFET, and an n-type impurity or a p-type impurity is introduced into the polycrystalline silicon film that becomes the drain region. A semiconductor integrated circuit device according to claim 5. 7. A semiconductor integrated circuit device having an SRAM configured with a memory cell consisting of a flip-flop circuit consisting of a driving MISFET and a load MISFET, and a transfer MISFET, wherein a providing a gate electrode of the load MISFET connected to a drain region of the drive MISFET;
A semiconductor integrated circuit device characterized in that a channel forming region, a source region, and a drain region of the load MISFET are provided with a gate insulating film interposed above the gate electrode of the load MISFET. 8. A semiconductor integrated circuit device having an SRAM configured with a memory cell consisting of a flip-flop circuit consisting of a driving MISFET and a load MISFET, and a transfer MISFET, in which a memory cell is provided above the driving MISFET. A gate electrode of the load MISFET connected to the drain region of the drive MISFET is provided so as to cover the drive MISFET, and a gate insulating film is interposed over the gate electrode of the load MISFET to form a channel formation region and a source of the load MISFET. A semiconductor integrated circuit device comprising a region and a drain region.