KR960000965B1 - Semiconductor integrated circuit device - Google Patents

Abstract

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Description

Semiconductor integrated circuit device

1 and 2 are a layout view and a cross-sectional view of an essential part of a conventional SRAM memory cell.

3 is a sectional view of an essential part of an SRAM memory cell of the present invention.

4 is a plan view of the memory cell of FIG.

5 is an equivalent circuit diagram of the memory cell of FIG.

6 to 8 are plan views of a predetermined manufacturing process of the memory cell of FIG.

9 to 15 are cross-sectional views of essential parts of each manufacturing model of the memory cell shown in FIG.

16 is a sectional view showing a first modification of the present invention.

17 to 19 show a second modified example of the present invention.

20 and 21 are sectional views showing the manufacturing method of the second modification of the present invention.

22 and 23 are plan and cross-sectional views showing a third modification of the present invention.

24 and 25 are plan and cross-sectional views showing a fourth modification of the present invention.

* Explanation of symbols for main parts of the drawings

25,35 gate insulating film 27,34 gate electrode

28,29,31: semiconductor region 37A: channel region

37B: drain region 37C: small source region

DL, 40: data line WL, 27: word line

Qt ₁ , Qt ₂ : MISFET for transmission Qd ₁ , Qd ₂ : MISFET for head

Qp ₁ , Qp ₂ : Load MISFET

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and more particularly, to a technique effective in application to a semiconductor integrated circuit device having an SRAM composed of CMOS memory cells.

The memory cell of the COMS type SRAM is connected to a flip-flop circuit formed by cross-connecting two n-channel driving MISFETs and an inverter circuit of two p-channel load MISFETs and two storage nodes of the flip-flop circuit. It is composed of n-channel transfer MISFETs, a power supply voltage Vcc and ground potential are supplied to the flip-flop, and a pair of data lines are connected to the drain of each transfer MISFET, and the common gate is a word line. It is. The operation of the memory cell of the SRAM is well known as above. The word line is comforted, and information of "High" or "Low" is stored in the memory node through the transfer MISFET, or the state of the memory node is reversed. The lead acts as a static memory device. In addition, a memory cell of an SRAM having such a CMOS circuit has a feature of lowering power consumption only by the leakage current of the MISFET flowing to the memory cell during standby.

However, since the memory cells of the CMOS SRAMs constitute one memory cell with six MISFETs in total, there is a problem that the chip size becomes large. To solve this problem, a memory cell called "Stacked CMOS" is referred to as "IEEE Transactions on Electron Devices, Vol. ED-32, No. 2, February 1985, p272-277 ”. This memory cell called "Stacked CMOS" is formed of a polysilicon film on an n-channel driving MISFET of a p-channel load MISFET of a flip-flop circuit. 1 and 2, the top and side surfaces of the gate electrode 3b of the n-channel driving MISFET formed in the silicon substrate are covered with at least a thin insulating film 14. A polysilicon film is provided on the upper and side surfaces thereof, and a source 5e, a drain 5b, and a channel portion 5d of the p-channel load MISFET are formed in the polysilicon film.

The gate electrode of the p-channel load MISFET is common to the gate electrode 3b of the n-channel driving MISFET immediately below the channel portion 5d, and the p-channel load MISFET 5d is n. It is formed on the gate electrode 3b of the channel driving MISFET, and the thin insulating film 14 is a gate insulating film of the p-channel MISFET. The MISFET for driving the flip-flop circuit has n-type impurity regions 1e forming a common source, n-type impurity regions 1c, 1d and gate electrodes 3b, 3c forming a drain. It consists of. Each of the gate electrodes 3b and 3c is cross-connected to the impurity regions on the drain side of each other through the connection holes 2b and 2a. In addition, the n-type impurity regions 1c and 1d forming the drain of each driving MISFET constitute a storage node of a flip-flop circuit in common with the source of the n-channel transfer MISFET connected to the flip-flop outside. The transfer MISFET is constituted by the n-type impurity regions 1a and 1b forming the source impurity region, the common gate electrode 3a, and the drain. The n-type impurity regions 1a and 1b are connected to the aluminum electrodes 9a and 9b via the connection holes 8a and 8b. The common gate electrode 3a constitutes a word line in the memory, and the aluminum electrodes 9a and 9b constitute a data line, respectively. Further, on the low resistance polysilicon films 5a and 5b to which the p-type impurity forming the drain of the p-channel load MISFET is added at a high concentration, and on the gate electrodes 3b and 3c of the driving MISFET, respectively. The connection holes 8e and 8f in which the regions are commonly exposed are opened, and the polysilicon film 5a, the gate electrode 3b, and the polysilicon film 5b and the aluminum electrodes 9c and 9d are opened. The gate electrodes 3c are connected to each other. The source of the p-channel load MISFET is a common low-resistance polysilicon film 5e in which high concentrations of p-type impurities are added, and the supply voltage Vcc is supplied to the source of the two-channel load MISFET. It is. The channel portions 5c and 5d of the p-channel MISFET are disposed on the gate electrodes 3c and 3d of the driving MISFET, respectively.

According to the inventor's review, it has been found that the memory cell has the following problems.

First, since the gate electrode of the n-channel driving MISFET formed in the silicon substrate and the gate electrode of the p-channel loading MISFET stacked are shared, the channel portion of the p-channel loading MISFET must be connected to the driving MISFET. It must be placed on the gate electrode. Therefore, since the degree of freedom when arranging the memory cells is small, the problem was that the area of the memory cells cannot be efficiently reduced. In order to form a thin insulating film on the gate electrode of the driving MISFET, the material of the gate electrode may be limited, and the surface of high melting point metals such as tungsten or molybdenum, or those silicides, etc., necessary for speeding up the operation speed of the memory may be used. It was difficult to form a thin insulating film, and there was also a problem that these low resistance materials could not be used in reality. Further, the driving capability of stacked p-channel MISFETs is known to be smaller than that of p-channel MISFETs fabricated in silicon substrates. For example, the mobility of holes in p-channel MISFETs using polysilicon is about 10 cm ² / VS. In the static memory having such a low driving capacity MISFET has the following problems. That is, the 0j * line generated when the uranium (U) or the thrium (Th) contained in a small amount in a material such as resin and wiring material such as aluminum used to seal and block the memory chip is a memory cell. When incident on the memory node in the “high” state, electron-hole pairs are generated depending on the degree of scattering of the * line, and are attracted by the electric field of the depletion layer to change the potential of the memory node. If the value is sufficient for inversion, the information in the memory is destroyed.

This is a phenomenon called soft error, and the mobility of the hole showing the driving capability of the p-channel load MISFET in the memory cell of the conventional full CMOS SRAM in which all the MISFETs are formed in the silicon substrate is 200 cm ² / VS or more. The current could be supplied to the memory node according to the potential change of the node.

However, in the memory cells of the SRAM using the stacked p-channel MISFETs, as described above, the current driving capability is low, and sufficient current cannot be supplied to the storage node until the information is destroyed due to the potential change of the storage node. In addition, some charges are stored in the storage node part by the capacitance and gate capacitance of the pn junction part formed in the drain part of the driving MISFET. If the potential change of the memory node can be recovered by the diffusion of the charges, there is a problem. However, in the highly integrated memory cell, the cell area is small, so the capacity and gate capacity of the pn junction described above are small, and thus the accumulated charge is small, and the current driving capability of the p-channel MISFET is small, thus supplying sufficient charge to the memory node. There is a problem that the information of the memory cell is destroyed because it cannot be done.

An object of the present invention is to provide a semiconductor integrated circuit device having a memory cell structure having a large degree of freedom in arranging memory cells.

Another object of the present invention is to provide a semiconductor integrated circuit device which enables high speed operation.

Another object of the present invention is to provide a semiconductor integrated circuit device having a memory cell resistant to soft errors.

Therefore, a brief description of the representative of the invention disclosed herein is as follows.

That is, the present invention has two inverter circuits in which a load p-channel MISFET and a driving n-channel MISFET are connected in series, and both gate electrodes of one inverter circuit are connected to both drain regions of the other inverter circuit, N-channel for transfer in which a drain or source region is connected to the flip-flop circuit cross-connected and the drain region of each driving MISFET by connecting both gate electrodes of the other inverter circuit to both drain regions of one inverter circuit. A semiconductor integrated circuit device having a plurality of memory cells composed of MISFETs, comprising: a semiconductor substrate having a p-type first semiconductor region on its surface; an n-type source of a driving MISFET located on a main surface of the first semiconductor region; A drain region is disposed between the source and drain regions of the driving MISFET via a first insulating film used as a gate insulating film on a semiconductor substrate. The gate electrode of the molten driving MISFET, the n-type source of the transfer MISFET located on the main surface of the first semiconductor region, the drain region, and the load MISFET provided on the gate electrode of the driving MISFET via a second insulating film. The load MISFET has a gate electrode provided separately from the gate electrode of the driving MISFET, a channel region, a p-type source provided at both ends of the channel region, a drain region, and a gate insulating film provided between the channel region and the gate electrode. The gate electrode of the MISFET is composed of an n-type polycrystalline silicon film, the gate electrode of the load MISFET is composed of an n-type polycrystalline silicon film, and the n-type gate electrode of a load MISFET of one inverter circuit is driven and one inverter circuit is driven. N-type drain region of the MISFET for driving, n-type drain region of the driving MISFET for the other inverter circuit, n-type of transfer MISFET connected to the other inverter circuit A node is formed by electrically connecting a source and a drain region of a node, and a p-type drain region of a load MISFET of the other inverter circuit is connected to the node.

The memory cell of the SRAM according to the first embodiment of the present invention is shown in FIG. 5 (equivalent circuit diagram).

As shown in FIG. 5, the memory cells of the SRAM are arranged at the intersections of the complementarity data lines DL, * and word lines WL. The complementarity data lines DL, * extend in the row direction. The word line WL extends in the column direction.

In the memory cell, each of the two transfer MISFETs Qt ₁ and Qt ₂ , in which one semiconductor region is connected to a flip-flop circuit and a pair of input / output terminals thereof, has an n-channel type. The other semiconductor regions of the transfer MISFETs Qt ₁ and Qt ₂ are connected to the complementarity data lines DL and *. The gate electrodes of the transfer MISFETs Qt ₁ and Qt ₂ are connected to the word line WL.

The flip-flop circuit is comprised as an information accumulating part (having an information accumulating node part). The flip-flop circuit consists of two driving MISFETs Qd ₁ and Qt ₂ and two load MISFETs Qd ₁ and Qt ₂ . The driving MISFETs Qd ₁ and Qt ₂ are of n-channel type, and the load MISEFT Qd ₁ and Qt ₂ are of p-channel type. In other words, the flip-flop circuit is composed of a complete CMOS.

The source regions of the driving MISFETs Qt ₁ and Qt ₂ are connected to the reference voltage Vss. The reference voltage Vss is, for example, 0 V of the ground potential of the circuit. The drain region of the driving MISFET Qt ₁ is connected to the drain region of the load MISFET Qt ₁ , the semiconductor region of one of the transfer MISFET Qt ₁ , the gate electrode of the driving MISFET Qt ₂ , and the gate electrode of the load MISFET Qt ₂ . .

The drain region of the driving MISFET Qt ₂ is connected to the drain region of the load MISFET Qt ₂ , the semiconductor region of one of the transfer MISFET Qt ₂ , the gate electrode of the driving MISFET Qt ₁ , and the gate electrode of the load MISFET Qt ₁ . . The source regions of the load MISFETs Qt ₁ and Qt ₂ are connected to the power supply voltage Vcc. The power supply voltage Vcc is, for example, an operating voltage of 5 V of the circuit.

Next, the structure of the specific memory cell of the SRAM configured as described above will be briefly described with reference to FIGS. 4 (plan view) and 3 (sectional view seen from line III-III of FIG. 4).

The memory cell has a main surface of the p-type well region 22 (first semiconductor region) formed in the main surface portion of the n-type semiconductor substrate 21 made of single crystal silicon, as shown in FIGS. 3 and 4. It is provided in wealth. Although not shown, in the region different from the p-type well region 22, an n-type well region is provided in the main surface portion of the semiconductor substrate 21. Between the memory cells or each element constituting the memory cell, a field insulating film 23 and a p-type channel stopper region 24 are provided on the main surface of the well region 22. Each of the field insulating film 23 and the channel stopper region 24 is configured to electrically separate between memory cells or elements constituting the memory cells.

Each of the MISFETs Qt ₁ and Qt ₂ for transferring the memory cells is shown in FIG. 3, FIG. 4, and FIG. 6 (a plan view in the definition manufacturing process) of the field insulating film 23 and the channel stopper region 24. As shown in FIG. It is comprised in the main surface of the well area 22 in the area | region enclosed by the. That is, each of the transfer MISFETs Qt ₁ and Qt ₂ is mainly a well region 22, a gate insulating film 25 serving as a first insulating film, a gate electrode 27, a source region (second semiconductor region) and a drain region (the first region). A pair of n-type semiconductor regions 29 and a pair of n + type semiconductor regions 31, which are three semiconductor regions.

The well region 22 is used as a channel region.

The gate insulating film 25 is composed of a silicon oxide film formed by oxidizing a main surface of the well region 22.

At the time of transmission, the gate electrodes 27 of the MISFETs Qt ₁ , Qt ₂ and the driving MISFETs Qd ₁ , Qd ₂ are formed in the same layer on a predetermined upper portion of the gate insulating film 25. The gate electrode 27 is composed of a composite film in which a high melting point metal silicide film (WSi ₂ ) 27B is stacked on top of the polycrystalline silicon film 27A. The polycrystalline silicon film 27A is deposited by CVD, and n-type impurities (P or As) for reducing the resistance value are introduced. The high melting point metal silicide film 27B is deposited by sputtering or CVD. The gate electrode 27 composed of the composite film has a lower specific resistance compared to the single layer of the polysilicon film, and thus the operation speed can be increased. When the transfer is formed simultaneously with the gate electrodes of the driving MISFETs Qd ₁ and Qd _2, the gate electrodes of the MISFETs Qt ₁ and Qt ₂ , that is, word lines are formed by using a high melting point metal silicide film having a small resistance value. High speed operation can be realized. In addition, the gate electrode 27 is composed of a high melting point metal silicide film 27B, so that the gate electrode 27 has a conductivity type of impurity introduced into the polycrystalline silicon films 34 and 37 above the gate electrode 27. Irrespective of this, a negative connection can be made at the time of method with an upper polycrystalline silicon film.

The gate electrodes 27 of the transfer MISFETs Qt ₁ and Qt ₂ are integrally formed with word lines WL 27 extending in the column direction. The word line 27 is provided on the field insulating film 23.

The gate electrode 27 is formed by stacking a high melting point metal silicide (MoSi ₂ , TaSi ₂ , TiSi ₂ ) film or a high melting point metal (Mo, Ta, Ti, W) film on top of the polycrystalline silicon film 27A. You may comprise with one composite membrane. The gate electrode 27 may be formed of a single layer of a polycrystalline silicon film, a high melting point metal film, or a high melting point metal silicide film.

The low impurity concentration semiconductor region 29 is formed integrally with the high impurity concentration semiconductor region 31 and is provided on the channel region side at the main surface of the well region 22. In the low impurity concentration semiconductor region 29, each of the transfer MISFETs Qt ₁ and Qt ₂ has a so-called LDD (Lightly Doped Drain) structure. The semiconductor region 29 of low impurity concentration is self-aligned with respect to the gate electrode 27.

The semiconductor region 31 having a high purity concentration is self-aligned with respect to the sidewall spacer 30 formed on the sidewall of the gate electrode 27.

Each of the driving MISFETs Qd ₁ and Qd ₂ of the memory cell has a structure substantially the same as that of each of the transfer MISFETs Qt ₁ and Qt ₂ . That is, each of the driving MISFETs Qd ₁ and Qd ₂ is a pair of n-type semiconductor regions 29 and a pair of well regions 22, a gate insulating film 25, a gate electrode 27, a source region and a drain region. The n + type semiconductor region 31 is formed. Each of the driving MISFETs Qd ₁ and Qd ₂ has an LDD structure.

The other end extending from the gate electrode 27 of the driving MISFET Qd ₂ passes through the connection hole 26 and is a semiconductor region 31 which is a drain region of the driving MISFET Qd ₁ via the n + type semiconductor region 28. Is connected to. One semiconductor region 31 of the driving MISFET Qd ₂ is integrally formed.

The data line DL 40 is connected to the other semiconductor region 31 of the transfer MISFETs Qt ₁ and Qt ₂ through a connection hole 39 formed in the interlayer insulating film 38. The data line 40 is configured to extend in the row direction over the interlayer insulating film 38. The data line 40 is made of, for example, an aluminum film or an aluminum alloy film containing Cu or Si added to prevent migration.

The reference voltage Vss is applied to the semiconductor region 31 which is the source region of each of the driving MISFETs Qd ₁ and Qd ₂ . The supply of the reference voltage Vss is made of a composite film made of the same conductive layer as the gate electrode 27 and the word line 27, that is, the polycrystalline silicon film 27A and the high melting point metal silicide film 27B, and the same. The reference voltage wiring extends in the column direction. This reference voltage wiring is connected to a semiconductor region 31 which is a source region of each of the driving MISFETs Qd ₁ and Qd ₂ through a connection hole 26 formed in the gate insulating film 25.

The load MISFET Qp ₁ of the memory cell is configured on top of the drive MISFET Qd ₂ . The load MISFET Qp ₂ is configured on top of the driving MISFET Qd ₁ . That is, each of the load MISFETs Qp ₁ and Qp ₂ is mainly composed of a gate electrode 34, a gate insulating film 35 as a third insulating film, a channel region 37A, a drain region 37B and a source region 37C. It is.

As shown in detail in FIG. 7 (a plan view in a predetermined manufacturing process), the gate electrode 34 of the load MISFET Qp ₁ is configured to cover it on top of the gate electrode 27 of the drive MISFET Qd ₂ . have. An interlayer insulating film 32 serving as a second insulating film is provided between the gate electrode 34 and the gate electrode 27. The gate electrode 34 of the load MISFET Qp ₁ is connected to the surface of the high melting point metal silicide film 27B of the gate electrode 27 of the driving MISFET Qd ₁ through a connection hole 33 formed in the interlayer insulating film 32. It is. Similarly, the gate electrode 34 of the load MISFET Qp ₂ is configured to cover it on top of the gate electrode 27 of the driving Qd ₁ . The gate electrode 34 of the load MISFET Qp ₂ passes through the connection hole 33 and the gate electrode 34 of the drive MISFET Qd ₂ is driven integrally with one semiconductor region 31 of the transfer MISFET Qt ₁ . MISFET Qd is connected to the semiconductor region 31, a drain region of the _second.

The gate electrode 34 is composed of a polycrystalline silicon film into which impurities having a low resistance value are introduced. The p-type impurity (B) is introduced into this polycrystalline silicon film. The gate electrode 34 is a polycrystalline silicon film into which the p-type impurity (B) is introduced, and constitutes the gate electrode 34. In order to avoid the parasitic diode insertion, the gate electrode 34 is interposed with a high melting point metal silicide film 27B. 31) or the first electrode 27; The gate electrode 34, which is a polycrystalline silicon film into which p-type impurities are introduced, can lower the respective threshold voltages of the load MISFETs Qp ₁ and Qp ₂ as compared with the case of the n-type gate electrode.

The lowering of the threshold voltage can reduce the amount of impurity introduced into the respective channels 37A of the load MISFETs Qp ₁ and Qp ₂ , so that the amount of impurity can be easily controlled.

In addition, when n-type impurities (As or P) are introduced into the gate electrode 34, the gate electrode 34 and the gate electrodes 27 of the driving MISFETs Qd ₁ and Qd ₂ or the n-type vehicle body region, respectively. The ohmic characteristic is not impaired upon connection with (31).

The gate electrodes made of the n-type polycrystalline silicon films of the MISFETs Qp ₁ and Qp ₂ for the load include the drain regions of the n-channel MISFETs Qp ₁ and Qp ₂ for driving, and the n-channel MISFETs Qt ₁ and Qt ₂ for the transfer, Since the nodes are connected to the n-type gate electrodes of the driving MISFETs Qd ₁ and Qd ₂ , and the nodes are composed of n-type semiconductors with each other, the connection becomes a negative connection. Further, as will be described later, since the drain regions of the load MISFETs Qp ₁ and Qp ₂ are formed of a p-type polycrystalline silicon film, there is a possibility that they are connected to the node via a pn junction.

Therefore, there is a concern that the diode D ₂ is connected between the drain region of the diode D ₁ load MISFET Qp ₂ and the node N ₂ between the drain region of the load MISFET Qp ₁ and the node N ₁ . However, since there is no possibility of forming a pn junction between the load MISFET and the node, there is no problem in the operation of the memory cell.

Further, as a result of the basic research of the present inventors, when the gate electrode 34 is formed with a film thickness of about 1000 GPa or more, the gate electrode 34 is caused by the electric field effect at the gate electrode 27 of the driving MISFET Qd ₁ or Qd ₂ . A depletion layer was formed inside the (polycrystalline silicon film) and the effect of shielding the electric field effect at the gate electrode 27 with the gate electrode 34 was confirmed. Therefore, the gate electrode 34 is composed of the above-described film thickness.

The gate electrode 34 is not limited to the polycrystalline silicon film but may be formed of a single layer of a high melting point metal silicide film or a eutectic melting point metal film. In this case, the conductivity type of the conductive layer connected to the gate electrode 34 is irrelevant. The gate electrode 34 may be a composite film of a high melting point metal silicide film or a high melting point metal film on a polycrystalline silicon film.

The capacitor C ₅ having the interlayer insulating film 32 as a dielectric is formed in the gate electrodes 27 of the driving MISFETs Qd ₁ and Qd ₂ and the gate electrode mountains of the load MISFETs Qp ₁ and Qp ₂ . That is, as is clear from Fig. 7, the gate electrode 27 and the gate electrode 34 have a portion which does not overlap with the overlapping portion in the planar pattern, but the capacitor C ₅ is formed at least in the overlapping portion.

This capacity C ₅ has the effect of increasing the capacity of the accumulation node portions n ₁ and n _{2 in} the flop-floor as shown in FIG. 5. The gate insulating film 35 is composed of a silicon oxide film deposited by CVD.

The channel region 37A is formed on a predetermined upper portion of the gate insulating film 35 as shown in detail in FIG. 8 (a plan view in the manufacturing process of the source). The channel region 37A is composed of an i-type polycrystalline silicon film in which impurities which reduce the resistance value are not introduced or in which some p-type impurities are introduced.

The drain region 37B is integrally formed with one end of the channel region 37A, and is composed of a p-type polycrystalline silicon film into which p-type impurities are introduced. The drain region 37B includes a gate insulating film 35 ( It is connected to the gate electrode 27 through a connection hole 36 formed in the channel region 37A except for the portion of the channel region 37A. Since the drain region 37B and the gate electrode 27 are connected via a high melting point metal silicide layer, the drain region 37A and the gate electrode 27 can be ohmicly connected.

The source region 37C is integrally formed with the other end of the channel region 37A, and is composed of a p-type polycrystalline silicon film into which p-type impurities are introduced. The source region 37C is integrally formed with the power supply voltage wiring Vcc extending in the column direction.

As shown in FIG. 3, the gate electrode 34, the source region 37C, and the drain region 37B of the load MISFET Qp ₁ are formed to actively overlap. By overlapping in this manner, the capacitor C ₃ is formed between the gate and the source of the load MISFET Qp ₁ , and the capacitor C ₁ is formed between the gate and the drain. These capacities C ₁ to C ₄ are equivalent when connected to the information storage nodes n ₁ and n ₂ , so that the capacity generated at the information storage nodes can be increased. Therefore, the effect that a software error such as * line or the like rarely occurs is obtained.

As described above, in the SRAM having a CMOS memory cell, the gate electrode 34 of the load MISFET Qp is provided on the gate electrode 27 of the driving MISFET Qd to provide the gate electrode 27 of the driving MISFET Qd. Since the electric field effect can be shielded, the current amount during the operation of the load MISFET Qp and the current amount during the standby can be independently optimized.

In addition, the gate electrodes of the load MISFET and the drive MISFET are made independent of each other so that the direction of connecting the source region and the drain region of the drive MISFET in the planar pattern and the load MISFET as shown in FIG. Since the direction connecting the source area and the drain region of orthogonal to can be arranged to be orthogonal, the degree of freedom of arrangement can be increased.

In addition, since the gate electrode of the transfer MISFET can be formed of a low resistance material having a high melting point silicide layer, information read and write operations can be performed at high speed.

In addition, since the capacitance generated in the information storage node of the memory cell can be increased, the amount of charge accumulation in the information storage unit can be increased, thereby preventing the error.

Next, the manufacturing method of the memory cell of the SRAM will be briefly described with reference to FIGS. 9 to 15 (the main part cross-sectional view to be shown for each manufacturing process).

First, an n-type semiconductor substrate 21 made of single crystal silicon is prepared.

Next, in each of the memory cell formation region and the n-channel MISFET formation region of the peripheral circuit (not shown), the p-type well region 22 is formed in the main surface portion of the semiconductor substrate 21.

Next, the field insulating film 23 and the p-type channel stripper region 24 are formed on the main surface of the well region 22 between the elements of the memory cell.

Next, as shown in FIG. 9, in each element formation region of the memory cell, a gate insulating film 25 is formed on the main surface yarn of the well region 22. The gate insulating film 25 oxidizes the main surface of the well region 22 to form a silicon oxide film. The gate insulating film 25 is formed to have a film thickness of, for example, about 250 to 350 Å.

Next, as shown in FIG. 10, the connection hole 26 is formed. The connection hole 26 can be formed by partially removing the gate insulating film 25 at the portion where the gate electrode 27 is directly connected to the main surface of the well region 22.

Next, as shown in FIG. 11, the gate electrode 27, the word line 27 and the reference voltage wiring are formed. The gate electrode 27 is formed of a composite film in which a high melting point metal silicide film 27B is laminated on the polycrystalline silicon film 27A. The polycrystalline silicon film 27A introduces P, an n-type impurity, which is deposited by CVD to reduce the resistance value. The polycrystalline silicon film 27A is formed to have a film thickness of, for example, about 2000 to 3000 mW. The high melting point metal silicide film 27B is deposited by a sputter. The high melting point metal silicide film 27B is formed to have a film thickness of, for example, about 2500 to 3500 kPa. The polycrystalline silicon film 27A and the high melting point metal silicide film 27B are patterned by anisotropic etching such as RIE.

Next, as shown in FIG. 12, an n + type semiconductor region 28 is formed in the main surface portion of the well region 22 to which the gate electrode 27 is connected through the connection hole 26. As shown in FIG. The semiconductor region 28 can be formed by thermal diffusion of n-type impurities introduced into the polycrystalline silicon film 27A under the gate electrode 27 to the main surface portion of the well region 22. The semiconductor region 28 is formed by the same process as the heat treatment process for activating the high melting point metal silicide film 27B, for example, of the gate electrode 27.

Next, sidewall spacers 30 are formed on the sidewalls of the gate electrodes 27. The sidewall spacer 30 can be formed by depositing a silicon oxide film by CVD so as to cover the gate electrode 27, and anisotropic etching such as RIE on the acid-silicon film.

Next, as shown in FIG. 13, an n + type semiconductor region 31 used as a source region and a drain region is formed. The semiconductor region 31 can be formed by introducing, for example, 10 ¹⁵ to 10 ¹⁶ atoms / cm ² of As by ion implantation of energy of about 40 to 60 KeV. When introducing this impurity, the gate electrode 27, the field lead film 23 and the side wall spacer 30 are mainly used as the impurity introduction mask. Therefore, the semiconductor region 31 may be formed in a self-aligning manner with respect to the sidewall spacer 30. By forming the semiconductor region 31, each of the transfer MISFETs Qt ₁ and Qt ₂ and the drive MISFETs Qd ₁ and Qd ₂ are completed.

Although not shown, a p + type semiconductor region which is a source region and a drain region of the p-channel MISFET constituting the peripheral circuit is formed after the process of forming the semiconductor region 31.

Next, an interlayer insulating film 32 is formed on the front surface of the substrate including the upper portion of the gate electrode 27. The interlayer insulating film 32 is formed of a silicon oxide film having a dense film quality deposited by CVD. The interlayer insulating film 32 is formed to have a thin film thickness of about 300 to 1500 mW so as to alleviate the growth of the step difference formation and improve the step coverage of the upper conductive layer.

Next, at the connection portion between the gate electrode 27 and the gate electrode 34, the interlayer insulating film 32 is partially removed to form the connection hole 33.

Next, as shown in FIG. 14, the gate electrodes 34 of the load MISFETs Qp ₁ and Qp ₂ which are connected to the gate electrodes 27 through the connection holes 33 are formed. The gate electrode 34 is formed of a polycrystalline silicon film deposited by CVD. The gate electrode 34 is formed to have a thin film thickness of, for example, about 1000 to 15000 Å. The gate electrode 34 introduces P of about 10 ¹⁵ to 10 ¹⁶ atoms / cm ² through ion implantation of energy of about 20 to 40 KeV. In other words, the gate electrode 34 is formed of an n-type polycrystalline silicon film.

Next, a gate insulating film 35 is formed on the entire surface of the substrate so as to cover the gate electrode 34. The gate insulating film 35 is formed to have a film thickness of, for example, about 200 to 400 Å.

Next, as shown in FIG. 15, the channel regions 37A, drain regions 37B, and source regions 37C of the load MISFETs Qp ₁ and Qp ₂ are placed on the gate insulating film 35 (power supply voltage). And wiring) are sequentially formed. The channel region 37A, the drain region 37B, and the source region 37C are formed of, for example, a polycrystalline silicon film deposited by CVD, and have a film thickness of about 650 to 2000 GPa. The drain region and the source regions 37B and 37C are formed into a p-type by introducing, for example, 10 ¹⁶ atoms / cm ² of BF ₂ into a polycrystalline silicon film by ion implantation of energy of about 50 to 70 KeV.

By forming the channel region 37A, the drain region 37B and the source region 37C, the load MISFETs Qp ₁ and Qp ₂ are completed.

Next, an interlayer insulating film 38 is formed on the entire surface of the substrate. The interlayer insulating film 38 is formed of a composite film in which, for example, a PSG film deposited by CVD is formed on the silicon oxide film deposited by CVD. Thereafter, a connection hole 39 is formed in the interlayer insulating film 38.

Next, as shown in FIGS. 3 and 4, the interlayer insulating film 38 is connected to the other semiconductor region 31 of the transfer MISFETs Qt ₁ and Qt ₂ through the connection holes 39. FIG. The data line 40 is formed on the upper portion.

By performing these series of manufacturing processes, the memory cell of the SRAM of this embodiment is completed.

FIG. 16 is a polycrystalline sequence of the conductive layers constituting the gate electrodes of the driving MISFETs Qd ₁ and Qd ₂ and the transfer MISFETs Qt ₁ and Qt _{2 in} the lower layer in the structure of the embodiment of the present invention shown in FIG. This is an example of a three-layer structure of a silicon film, TiN, and a high melting point metal silicide layer.

The gate electrodes 37 of the driving MISFETs Qd ₁ and Qd ₂ are n-type, and the gate electrodes 34 and the source and drain regions 37B and 37C of the load MISFETs Qp ₁ and Qp ₂ are p-type, respectively. If directly connected to the dopants, there is a problem that the impurities diffuse to each other. However, as shown in FIG. 16, since the titanium nitride barrier layer is interposed between the p-type drain region and the n-type drain region, mutual diffusion of both impurities is performed. Can be prevented.

In addition, by interposing a TiN barrier layer between the polycrystalline silicon film and the high melting point metal silicide layer, a problem of high melting point metal passing through the polycrystalline silicon film, entering the gate insulating film layer below it, and lowering the breakdown voltage of the gate insulating film is prevented. can do. It goes without saying that the structure of the gate electrode may be applied to another example of the present invention.

FIG. 17 is a cross sectional view taken from XVII-XVII of FIG. 18 as an example of the case where the gate electrodes of the load MISFETs Qp ₁ and Qp ₂ are provided above the source, drain and channel regions. 19 is an equivalent circuit diagram of the memory cell shown in FIG. In addition, in FIG. 17-19, the code | symbol of each part is the same as the example of FIG. The difference between this embodiment and the embodiment shown in FIGS. 3 to 4 is that the gate electrodes of the load MISFETs Qp ₁ and Qp ₂ are provided above the source, drain and channel regions. That is, the source, drain and channel regions of the load MISFETs Qt ₁ and Qt ₂ are formed of the second polycrystalline silicon layer, and the gate electrode is formed of the third polycrystalline silicon layer.

The source and drain regions of the load MISFETs Qp ₁ and Qp ₂ are impurity regions into which boron is introduced. The boron is introduced so that the gate electrode 34 is used as a mask and then annealed so that the gate electrode and the impurity region overlap. The capacitances of the gate electrode, the source, the drain region, and the overlapping are connected as C ₁ to C ₄ in FIG. 19, resulting in the effect of increasing the capacitance added to the information storage node.

20 and 21 illustrate a method of manufacturing a memory cell shown in FIGS. 17 to 19. FIG. As shown in Figs. 9 to 14, the polycrystalline silicon films of the first and second layers are similarly formed. However, the planar pattern of the polycrystalline silicon film of the second layer is different from that of FIG.

As shown in FIG. 20, for example, polycrystalline silicon 37 deposited by CVD is formed to a film thickness of 650 to 2000 microns, and then the gate insulating film 35 is shown as shown in FIG. It is formed to a film thickness of about 200 ~ 400Å. Further, polycrystalline silicon 34 is formed on the gate insulating film 35 by a CVD to a film thickness of 1000 to 1500 Å. This polysilicon 34 is patterned as shown in FIG. Subsequently, ion-implanted BF ₂ of about 10 ¹⁶ atoms / cm ² to the gate electrodes of the load MISFETs Qp ₁ , Qp ₂ , and the source and drain regions with energy of about 50 to 70 KeV, and annealing at 850 to 950 ° C. By overlapping the boron implanted in the polycrystalline silicon 37 in the transverse direction, an overlap capacitance is formed between the source and drain regions and the gate electrode.

By using the gate electrode as an ion implantation mask for forming the source and drain regions in this manner, the source and drain regions can be formed in self-alignment with the gate electrode, and the manufacturing process can be simplified.

22 and 23 are substantially the same as the examples shown in FIGS. 17 to 19, but differ in the planar patterns of the gate electrodes 34 of the load MISFETs Qp ₁ and Qp ₂ . FIG. 22 is a cross sectional view taken along line XXII-XXII in FIG. In this example, the gate electrodes 34 of the load MISFETs Qp ₁ and Qp ₂ have a configuration that overlaps the source and drain regions widely. By overlapping the source and drain regions in this manner, the capacity of C ₁ to C ₄ in FIG. 19 can be increased.

In this case, however, the gate electrode of the load MISFET cannot be used as the ion implantation mask for forming the source and drain regions, as described in FIG. 21, so that the number of manufacturing steps increases.

24 and 25 are examples of the case where the polycrystalline silicon film of the second layer is used as the reference voltage wiring. FIG. 24 is a cross sectional view taken along line XXIV-XXIV of FIG. 25;

On the gate electrodes 27 of the driving MISFETs Qd ₁ and Qd ₂ , a reference voltage wiring 42 formed of the second polycrystalline silicon film is formed as shown in FIG. 25. The reference voltage wiring 42 is disposed between the gate electric 27 of the driving MISFETs Qd ₁ and Qd ₂ and the channel region 37A (i) of the load MISFETs Qp ₁ and Qp ₂ and in a direction parallel to the word line. Extending.

According to this structure, the electric field effect at the gate electrode 27 of the drive MISFETs Qp ₁ and Qp ₂ with respect to the load MISFET can be prevented.

Therefore, it is possible to prevent the gate electrodes of the driving MISFETs Qp ₁ and Qd ₂ from changing the amount of current during the operation and the standby of the load MISFET due to the electric field effect.

In addition, since the reference voltage wiring 42 can be formed with the driving MISFETs Qd ₁ and Qd ₂ , the memory cell area can be made small.

Claims (5)

There are two inverter circuits formed by connecting a load p-channel MISFET and a driving n-channel MISFET in series, and both gate electrodes of one inverter circuit are connected to both drain regions of the other inverter circuit, and the other inverter circuit. A memory cell comprising a flip-flop circuit cross-connected by connecting both gate electrodes of one inverter circuit to both drain regions of one inverter circuit, and an n-channel MISFET for transfer, each having a drain or source region connected to a drain region of the driving MISFET. A semiconductor integrated circuit device having a plurality of semiconductor devices, comprising: (a) a semiconductor substrate having a p-type first semiconductor region on its surface; and (b) an n-type of the driving MISFET located on a main surface of the first semiconductor region. Source and drain regions of (c) a source and a drain of a driving MISFET through a first insulating film used as a gate insulating film on said semiconductor substrate; On the gate electrode of the driving MISFET located between the phosphorus regions, (d) on the n-type source, drain region of the transfer MISFET located on the main surface of the first semiconductor region, and (e) on the gate electrode of the driving MISFET. And a load MISFET provided through a second insulating film, wherein the load MISFET includes a gate electrode provided separately from the gate electrode of the driving MISFET, a channel region, and a p-type source provided at both ends of the channel region; A drain insulating region and a gate insulating film provided between the channel region and the gate electrode, the gate electrode of the driving MISFET is composed of an n-type polycrystalline silicon film, and the gate electrode of the load MISFET is composed of an n-type polycrystalline silicon film. N-type gate electrode of the load MISFET of the one inverter circuit, n-type gate electrode of the driving MISFET of the one inverter circuit, and the other phosphorus A node is formed by electrically connecting the n-type drain region of the drive MISFET of the drive circuit and the n-type source and drain region of the transfer MISFET connected to the other inverter circuit. A semiconductor integrated circuit device formed by connecting a p-type drain region of a load MISFET of an inverter circuit. The method of claim 1, wherein a gate electrode of the load MISFET is formed on the second insulating film, and a channel region of the load MISFET is formed on the load electrode of the load MISFET. And a p-type drain region of the load MISFET is connected to a drain region of the driving MISFET via a gate electrode of the load MISFET. The semiconductor according to claim 2, wherein an n-type gate electrode of the load MISFET and an n-type drain region of the driving MISFET or the transfer MISFET are connected via an n-type gate electrode of the driving MISFET. Integrated circuit device. The method of claim 1, wherein the gate electrode of the driving MISFET is formed on the channel region of the load MISFET via a gate insulating film of the load MISFET, the p-type drain region of the load MISFET And said transfer MISFET or said drive MISFET is connected to an n-type drain region. The semiconductor according to claim 4, wherein a p-type drain region of the load MISFET and an n-type drain region of the transfer MISFET or the driving MISFET are connected via an n-type gate electrode of the driving MISFET. Integrated circuit device.