JPH04226081A - Semiconductor device - Google Patents

Abstract

PURPOSE:To provide a thin film transistor of small leakage current and small source-drain resistance. CONSTITUTION:An insulating layer 11 is overlaid with a silicon thin film 12, and at least a part of the same film is used as the substrate region to provide a gate 14 to form a channel at a corresponding region; further, a silicide film 15 to form a Schottky barrier between the gate and the above-mentioned substrate region, and at least one of the source and drain is constituted of the silicide film.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor integrated circuit device having a thin film transistor (hereinafter referred to as TFT) formed on an insulating layer covering a silicon substrate.

0002

2. Description of the Related Art A TFT has a silicon thin film formed on an insulator as a base region. Source and drain regions of an opposite conductivity type are selectively formed with respect to a base region of one conductivity type, and a gate electrode is formed on the base region between these regions with a gate insulating film interposed therebetween.

[0003]In recent years, integrated circuit devices have been proposed that have a TFT on the same silicon substrate as well as an MIS transistor whose base region is a part of the silicon substrate, such as using a TFT as a load element in a static random access memory (SRAM) cell. , research and development is underway.

0004

In order to integrate TFTs and MIS transistors on a single silicon substrate and obtain desired characteristics, it is necessary to improve the characteristics of TFTs to the same level as MIS transistors. One of the inferior characteristics of TFTs is their large leakage current. As a means of reducing leakage current, it is known to form the substrate region very thin, for example, 500 angstroms or less.

However, forming the base region thinner means that the resistance of the source and drain regions increases. Therefore, it is necessary to supply electricity or provide wiring using a conductive film of low resistance such as metal, which increases the number of manufacturing steps. In particular, when a TFT is used as a load element in an SRAM cell, an additional conductive layer is required to connect the TFT and the MIS transistor, and no improvement in storage capacity can be expected.

[0006] Accordingly, an object of the present invention is to provide a semiconductor device having an improved TFT.

Another object of the present invention is to provide a semiconductor device equipped with a TFT having a small leakage current without increasing the resistance of the source and drain.

Still another object of the present invention is to provide a semiconductor integrated circuit device having a TFT suitable for use as a load element of an MIS transistor.

[0009]

[Means for Solving the Problems] A semiconductor device according to the present invention includes a silicon thin film formed on an insulator, and a gate provided to form a channel in the region using at least a portion of the silicon thin film as a base region. A thin film transistor having an electrode and a metal silicide film forming a Schottky barrier between the silicon thin film, and a junction between at least one of a source and a drain of the transistor and a base region in which the channel is formed. It is characterized by comprising the above-mentioned Schottky barrier.

That is, in the present invention, both the source and the drain are defined by a PN junction, while at least one of them is defined by a Schottky barrier. The metal silicide film used to form the Schottky barrier has good diode characteristics compared to the silicon thin film, and its resistance is sufficiently low, so the film can be used as is as a wiring, and is used to reduce leakage current. Even if the silicon thin film is formed thinly, no additional conductive layer is required.

In a preferred embodiment of the present invention, both the source and drain are formed of silicide films. That is, both the source and drain are separated by a Schottky barrier.

Focusing only on leakage current, it is preferable to make the silicon thin film thinner and to use a PN junction rather than a Schottky barrier. However, a thin silicon film reduces the degree of heterogeneity as described above. Therefore, in another embodiment of the present invention, only one of the source and drain (preferably the source) is formed of a silicide film and separated by a Schottky barrier, and the other of the source and drain (preferably the drain) is formed of a silicon thin film. The PN is composed of an impurity region selectively formed with a conductivity type opposite to that of the same film.
It is divided by a junction, and a silicide layer is further formed in contact with the impurity region. This silicide layer does not form a Schottky barrier between it and the impurity region.

Thus, according to the present invention, a semiconductor device having a TFT with low leakage current and low resistance at the source and drain is provided.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In each embodiment, the same components are designated by the same numbers to avoid duplication of explanation. Furthermore, it goes without saying that the impurity conductivity type, material, etc. in each embodiment can be changed as appropriate.

FIG. 1 is a sectional view showing a first embodiment of the present invention. A field silicon oxide film 11 with a thickness of about 0.5 μm is formed on the surface of a P-type silicon substrate 10. On the surface of the oxide film 11, an N-type polycrystalline silicon film 12, which serves as the base of the TFT, has a film thickness of 400 angstroms and has a thickness of about 1
It is formed with an impurity concentration of about 1015 cm-3. The polycrystalline silicon film 12 is formed by first forming an amorphous silicon film on the oxide film 11 and then polycrystallizing the film through heat treatment. According to the present invention, titanium silicide films 15 and 16 are selectively provided as source and drain regions on polycrystalline silicon film 12 by forming Schottky barriers 18 and 19 therebetween, respectively. The titanium silicide films 15 and 16 are formed by selectively forming a titanium layer on the polycrystalline silicon film 12 and then subjecting it to heat treatment. Thus, source 15 and drain 16 are defined by Schottky barriers 18 and 19, respectively. On the polycrystalline silicon layer 12 between the source 15 and the drain 16, an N-type polycrystalline silicon gate electrode 14 having an impurity concentration of about 1 x 1020 cm-3 is formed via a gate oxide film 13 with a thickness of about 300 angstroms. ing. A titanium silicide film 17 is formed on the gate electrode 14 to provide ohmic contact therewith.

According to this configuration, the silicide film 15,
A TFT is constructed with 16 as a source and a drain, respectively. The Schottky barriers 18 and 19 of the source 15 and drain 16 have good diode characteristics, and the TF
Since the silicon film 14 serving as the base region of T is formed thinly, sufficiently small leakage current characteristics can be obtained. Moreover, the layer resistance of the titanium silicide films 15 and 16 is about 5 Ω/□, which is sufficiently small, so that it can be used as is as wiring for voltage and signal supply.

In addition to titanium for the silicide films 15, 16, and 17, metals that form a Schottky barrier with silicon, such as platinum, tungsten, and molybdenum, can be used.

[0018] The leakage current of the TFT can be further reduced by using a PN junction. That is, FIG. 2 shows the second embodiment of the present invention.
As shown in the embodiment, a P-type region 20 is formed on the drain side, and a PN junction 22 is formed between it and the base region 12. Thus, in this embodiment, the drain is located in the impurity region 2.
It is formed as 0. This area 20 is 1×1013
Since it is formed by ion implantation with a dose of cm2, controllability and workability are much improved compared to high dose implantation. A titanium silicide film 21 is formed on the surface of the drain region 20 and is in ohmic contact with the region 20 .

Reduction of leakage current can also be achieved by reducing the area of the Schottky barrier. That is, as shown in the third embodiment in FIG. 3, titanium silicide films 30 and 31 serving as the source and drain are formed so as to reach the field oxide film 11. Therefore, the base region 12 is only directly under the gate electrode 14,
The areas of the Schottky barriers 35 and 36 are reduced, and leakage current is reduced.

FIGS. 7 and 8 show drain current characteristics and leakage current characteristics of the TFT according to this example. Channel length L and width W are 1.0 μm and 0.8 μm, respectively.
It is. Excellent characteristics were achieved, with the drain current turning on/off in 5 digits and the leakage current being about 10-13 (A).

FIG. 4 shows a fourth embodiment. This embodiment combines the structures for reducing leakage current shown in FIGS. 2 and 3. That is, a P-type region 40 is formed in place of the silicide film 31 in FIG. 3, forming a PN junction with the base region 12. Furthermore, an ohmic contact 43 is formed with the P-type region 40 to connect the titanium silicide film 42.
is formed. In this configuration, the leakage current is even smaller, 5×10−14 (A
) leakage current was achieved.

In the embodiments described above, the gate electrode 14 is formed above the base region 12 as a so-called top gate, but a bottom gate structure can also be realized. That is, as shown in the fifth embodiment in FIG. 5, an N-type polycrystalline silicon gate electrode 60 is selectively formed on a field oxide film 11, and its surface is covered with a gate oxide film 61. A base region 12 made of an N-type polycrystalline silicon film is formed on a gate oxide film 61, and a titanium silicide film 65 as a source and a titanium silicide film 66 as a drain are formed with Schottky barriers 67 and 68, respectively. In this example as well, almost the same characteristics as in FIGS. 7 and 8 were obtained.

FIG. 6 shows a sixth embodiment, in which the configuration of the embodiment of FIG. 4 is applied to a bottom gate. That is,
A P-type region 70 is formed by forming a PN junction 71 with the base region 12. Titanium silicide layer 72 forms ohmic contact 73 with P-type region 70 . This further reduces leakage current.

Referring to FIG. 9, an N-channel MIS
An inverter using a transistor QM1 and a P-channel TFT QT1 is shown as a seventh embodiment. Since the TFT used in this embodiment is the same as that in the first embodiment shown in FIG. 1, its explanation will be omitted. However, the polycrystalline silicon layer 12 as the base region of the TFT is replaced by the field oxide film 1.
1 and is in contact with the drain region 90 of the transistor QM1. Further, a titanium silicide layer 16 as a drain is also formed to extend and form a Schottky barrier with the silicon layer 12, and is in contact with the drain region 90. Since drain region 90 is highly doped, silicide layer 16 forms an ohmic contact. The titanium silicide layer 16 is further used as the output wiring of this inverter.
It is formed to extend so as to be connected to another logic gate (not shown). Although the silicide layer 15 serving as the source of the TFTQT1 is supplied with power through the aluminum wiring 97 in this embodiment, it is preferable to connect the silicide layer 15 directly to the power supply line.

A drain region 90 and a source region 91 of the transistor QM1 are selectively formed on the silicon substrate 10, and an N-type polycrystalline silicon gate electrode 93 is formed on the substrate between them with a gate oxide film 92 interposed therebetween. ing. A titanium silicide layer 94 is in ohmic contact thereon. A titanium silicide layer 95 is also formed on the surface of the source region 95 in ohmic contact, and a ground potential is applied to it by an aluminum wiring. Note that 98 is BPSG as an interlayer insulating layer.

The gate electrode 14 of the TFT QT1 and the gate electrode 93 of the transistor QM1 are commonly connected and supplied with an input signal to be inverted. Thus, the present inverter operates equivalently to a normal CMOS inverter, both formed as MIS transistors.

In addition to the TFT shown in FIG. 1, any of the TFTs shown in FIGS. 2 to 6 can be used as the TFT Q1. As an example, an inverter using the TFT shown in FIG. 5 is shown in FIG. 10 as an eighth embodiment. That is, T in FIG.
The drain silicide film 66 of the FTQT2 is formed by extending the field oxide film 11 and is connected to the drain region 101 of the MIS transistor QM2 with ohmic contact. The silicide film 66 is further led out as an output wiring of the inverter. An N-type polycrystalline silicon gate electrode 104 is formed on the substrate 10 between the drain region 101 and the source region 102 of the transistor QM2 with a gate oxide film 105 interposed therebetween.
are commonly connected to the gate electrodes 60 of and receive the signal to be inverted. In this embodiment, the ground wiring 96 is connected to the source region 102.
Although it is directly connected to, a silicide layer may be interposed.

In this way, in the inverters shown in FIGS. 9 and 10, the silicide layer 16 is used as the drain of the TFT, and because of its low layer resistance, it is also used as a wiring to the drain of the MIS transistor, resulting in low leakage. A complementary inverter with current characteristics and a very small footprint is provided.

By the way, the SRAM cell is shown in FIG.
As shown in , two inverters (QT11, QM11), each consisting of P and N channel transistors, (
QT12, QM12) and two transfer gate transistors QM13, QM14. Therefore, using the inverters shown in FIGS. 9 and 10, SRAM
cells can be configured. However, in these configurations, since the TFT and the MIS transistor are formed separated from each other in a plane, there is room for improvement in reducing the cell area.

Therefore, an SRA with a smaller cell area
FIG. 11 shows an M cell as a ninth embodiment. In addition, Figure 11
(B) is a plan view of the cell, and (C) is an I-I diagram of (B).
FIG.

In this SRAM cell, P-channel transistors QT11 and QT12 are composed of TFTs, and N-channel transistors QM11-QM14 are composed of MIS transistors. Furthermore, by using the bottom gate type TFT shown in FIG.
The gate of T12 is connected to transistors QM11 and QM, respectively.
It also serves as 12 gates. That is, as can be seen from FIG. 11C, the transistor QM12 has a gate electrode 126 on the substrate 10 between the source region 122 and the drain region 121 with the gate oxide film 123 interposed therebetween. Gate electrode 126 has an N-type polycrystalline silicon layer 124 and a tungsten silicide layer 125 formed thereon. A base region 127 of the TFTQT 12 is formed on the gate electrode 126 via a silicon oxide film 130, and a shock barrier is formed between this region and a titanium silicide film 128 for the source and a titanium silicide film 129 for the drain are provided. It is being The silicide film 128 receives power as the power line 115 and also serves as the TFTQ
It is formed to extend so as to also serve as the source of T11. Drain silicide 129 is connected to a gate electrode 133 of transistor QM11 (made of polycrystalline silicon 131 and tungsten silicide 132, like gate electrode 126 of QM12), and gate electrode 133 is connected to drain region 121 of transistor QM12. Gate electrode 133 is further connected to transfer gate transistor QM14 (see FIG. 11B). The source region 122 of the transistor QM12 is connected to the titanium silicide layer 116 for ground wiring, and the source region 138 of the transistor QM11 is also connected to the silicide layer 1.
16. Transistor QM11, TFT
The structure of QT11 is the same as that shown in FIG. 11(C), so its description will be omitted.

As described above, the SRAM cell according to this embodiment has a small leakage current and good data retention characteristics even though TFT is used as a load element, and also has a very small cell area and a high storage capacity. An SRAM is provided.

[0033]

As described above, according to the present invention, a TF with low leakage current and low resistance at the source and drain can be obtained.
Since the TFT is provided with a small element area, the characteristics of an integrated circuit device using the TFT can be improved, and the integration density can also be improved.

[Brief explanation of the drawing]

FIG. 1 is a sectional view showing a first embodiment of the present invention.

FIG. 2 is a sectional view showing a second embodiment of the invention.

FIG. 3 is a sectional view showing a third embodiment of the present invention.

FIG. 4 is a sectional view showing a fourth embodiment of the present invention.

FIG. 5 is a sectional view showing a fifth embodiment of the present invention.

FIG. 6 is a sectional view showing a sixth embodiment of the present invention.

FIG. 7 is a graph of drain current characteristics of TFTs according to third and fifth embodiments.

FIG. 8 is a graph of leakage current characteristics of TFTs according to third and fifth embodiments.

FIG. 9 is a sectional view showing a seventh embodiment of the present invention.

FIG. 10 is a sectional view showing an eighth embodiment of the present invention.

FIG. 11 is an SRAM cell showing a ninth embodiment of the present invention, in which (A) is an equivalent circuit diagram thereof, (B) is a plan view, and (C) is a view taken along line I-I' in (B). FIG.

Claims (9)

[Claims] 1. A shot is formed between a silicon thin film formed on an insulating layer, a gate provided to form a channel in the base region using at least a part of the silicon thin film as a base region, and the silicon thin film. 1. A semiconductor device comprising a thin film transistor having a silicide film forming a key barrier, wherein a junction between at least one of a source and a drain of the thin film transistor and the base region is formed by the Schottky barrier. 2. The semiconductor device according to claim 1,
A semiconductor device, wherein the source and the drain both form the Schottky barrier with the base region. 3. The semiconductor device according to claim 1,
It further includes an impurity region forming a PN junction with the base region and another silicide film in ohmic contact with the impurity region, and one of the source and drain has the Schottky barrier between it and the base region. form,
A semiconductor device, wherein the other of the source and drain includes the impurity region to form the PN junction with the base region. 4. The semiconductor device according to claim 2,
A semiconductor device, wherein the Schottky barrier reaches the insulating layer. 5. The semiconductor device according to claim 3,
A semiconductor device, wherein both the Schottky barrier and the PN junction reach the insulating layer. 6. A thin film transistor and an insulated gate transistor formed on the same semiconductor substrate, the thin film transistor comprising a silicon thin film formed on an insulating layer covering the semiconductor substrate, and at least a portion of the silicon thin film. a gate formed as a base region to form a channel in the base region; a source made of a first silicide film forming a Schottky barrier between the base region; and a drain having a second silicide film. The insulated gate transistor includes a source and a drain formed of impurity regions selectively formed on the semiconductor substrate, and a gate formed on the substrate between the source and drain with a gate insulating film interposed therebetween. , said second
A semiconductor device characterized in that the silicide film is formed in an extended manner and is in ohmic contact with the impurity region of the insulated gate transistor. 7. The semiconductor device according to claim 6,
A semiconductor device, wherein the second silicide film forms a Schottky barrier between the second silicide film and the base region. 8. The semiconductor device according to claim 6,
The semiconductor device further includes a semiconductor region forming a PN junction between the drain of the thin film transistor and the base region, and the second silicide film is in ohmic contact with the semiconductor region. 9. An insulated gate transistor and a thin film transistor formed on the same semiconductor substrate, wherein the insulated gate transistor has source and drain regions selectively formed in the semiconductor substrate and a thin film transistor formed on the substrate between them. and a gate electrode formed on the gate electrode via a first gate insulating film, and the thin film transistor includes a silicon thin film formed on the gate electrode via a second gate insulating film and controlled by the gate electrode to form a channel. and a source made of a first silicide film forming a Schottky barrier between the thin film and the thin film, and a drain having a second silicide film, the second silicide film being formed in an extended manner to form a Schottky barrier between the source and the thin film. A semiconductor device, characterized in that it is in ohmic contact with the drain region of a gate transistor.