JP2663953B2 - Semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a static random access memory (CMOS) having a complete CMOS structure using a melt-recrystallized semiconductor technology and a silicon-on-insulation (SOI) technology. (SRAM) cell.

In recent years, with the demand for lower power consumption and higher integration of semiconductor devices, SRAM cells (SRAM
Memory cells) are also configured with a complete CMOS and using a three-dimensional structure based on SOI technology has been proposed. And such an SRAM
Of the one conductivity type formed in the lower layer in the memory cell of
OS transistor and MO of opposite conductivity type formed in upper layer
There is a demand for a reliable connection to an S transistor.

[0003]

2. Description of the Related Art FIG. 6 is a circuit diagram showing an example of a conventional semiconductor device, FIG. 7 is a diagram showing a lower layer element in an example of a conventional semiconductor device, and FIG. It is a figure showing an upper layer side element in an example. Conventionally, SRAM (memory cell) consisting only of CMOS transistors
For example, as shown in the circuit diagram of FIG. 6, two CMOS inverters 55 and 56 composed of PMOS transistors 51 and 52 and NMOS transistors 53 and 54 and switching elements 57 and 58 composed of two NMOS transistors are provided. ing. The output terminal of one CMOS inverter 55 is connected to the input terminal of the other CMOS inverter 56, and the input terminal of one CMOS inverter 55 is connected to the output terminal of the other CMOS inverter 56. I have. Further, the respective drains of the respective switching elements 57 and 58 have respective CMOS inverters 56 and 5 connected thereto.
5 input terminals are connected, and the bit lines BL, B
L _B (where, BL _B is inverted level of the bit line BL) is mounted, and the word line WL to the gate electrode
Is connected.

When this circuit is formed as a semiconductor device, as shown in FIGS. 7 to 9, for example, a three-dimensional structure using SOI technology is used to increase the degree of integration of elements.
An OS transistor having two layers is used. That is, as shown in FIG. 7A, a first interlayer insulating film 67 as shown in FIG. 9 is formed on the NMOS transistors 53, 54, 57, 58 formed in the bulk layer, and , FIG.
(a) and a molten recrystallized silicon film (upper layer UL) 73, 74 as shown in FIG. 9 is grown, and PMOS transistors 51, 52
To form Each MOS transistor is connected by a bulk wiring or an aluminum electrode wiring.

By the way, the upper PMOS transistors 51, 52
And the lower NMOS transistors 53 and 5
When connecting to the circuit formed by 4,57,58,
A contact hole is provided in the interlayer insulating film 67 and aluminum wiring is used. For example, as shown in the side sectional view of FIG. 9 cut along the line AA in FIG. 7A and the line BB in FIG. 8A, the gate is connected to the word line WL. The drain region 57a of the NMOS transistor 57 and another NM
Gate electrode 61 of OS transistor 54 and PMOS transistor
When the gate electrode 62 is connected to the gate electrode 62 of the NMOS transistor 57, a first contact hole 68 is provided in a thermal oxide film formed on each of the NMOS transistors 54 and 57 so that the drain region 57a of the NMOS transistor 57 and another The gate electrode 61 of the NMOS transistor 54 is connected. Further, of the second interlayer insulating film 71 formed on the PMOS transistor 52,
A second contact hole 69 is provided above the gate electrode of the PMOS transistor, and the first contact hole
A third contact hole 70 is provided at a position corresponding to 68. Then, an aluminum electrode 72 is laminated on the second interlayer insulating film 71 to form first to third contact holes 68 to 70.
By filling the inside with an aluminum electrode 72, the drain region 57a of the NMOS transistor 57, the gate electrode 61 of another NMOS transistor 54, and the gate electrode 62 of the PMOS transistor 51 are connected.

The source region 57 of the NMOS transistor 57
A contact hole is provided above b, and the contact hole is filled with an aluminum layer 78 (bit line BL). In FIG. 7, reference numeral 74a
Is a contact hole for connecting the gate electrode 63 of the PMOS transistor 51 and the gate electrode 60 of the NMOS transistor 53, and 75 is a conductivity type diffusion layer of the PMOS transistor 52 and another PM.
In order to connect with the gate electrode of the OS transistor 51, a contact hole formed in the insulating film on the molten recrystallized silicon film 73, and 76 indicates an aluminum electrode continuously formed in these contact holes 74a and 75. I have. In FIG. 9, reference numeral 50 denotes a semiconductor substrate (lower layer LL), and 77 denotes an insulating film.

[0007]

However, according to the structure described with reference to FIGS.
Since it is formed in and around the first and third contact holes 68, 70 provided in the two interlayer insulating films 67, 71, the aspect ratio is increased in this portion, and the coverage of the aluminum layer 72 is poor. This causes problems such as disconnection.

Therefore, as shown in FIG. 10, a first contact hole 68 is filled with a molten recrystallized silicon film 72 ', on which a gate electrode 62' of a PMOS transistor 54 is laminated to form an upper PMOS transistor 52 '. And lower NMOS transistor 57
It is also possible to connect However, the inside of the first contact hole 68 is heated by the laser beam irradiated when forming the molten recrystallized silicon film 72 ', and
The N-type impurity in the drain region 57a of the NMOS transistor 57 diffuses into the molten recrystallized silicon film 72 '. As a result, the P-type impurity implanted into the molten recrystallized silicon film 72 'is in a compensated state, and the resistance at the portion of the first contact hole 68 becomes extremely high, so that the inconvenience such that the conduction does not occur occurs. Become.

SUMMARY OF THE INVENTION In view of the above-mentioned problems of the conventional semiconductor device, the present invention can connect a MOS transistor of one conductivity type formed in a lower layer and a MOS transistor of an opposite conductivity type formed in an upper layer without disconnection. It is an object of the present invention to provide a semiconductor device which can be used.

[0010]

According to the present invention, a lower layer LL is provided.
One-type MIS transistor 2; 3, an interlayer insulating film 24 laminated on the one-type MIS transistor 2; 3, and the one-type MIS transistor
A contact hole 12; 19 provided on the conductive type region layer 2a; 3a of the transistor 2; 3, and a connection to the conductive type region layer 2a; 3a of the one conductivity type MIS transistor 2; 3 through the contact hole 12; 19. Opposite conductivity type polycrystalline silicon film 3
1; 34 and a part of the opposite conductivity type polycrystalline silicon film 31; 34 as a gate electrode, and the semiconductor film 2 on the interlayer insulating film 24 is formed.
7; 28, an upper conductivity type MIS transistor 33; 36 on the side of the upper layer UL;
And the conductive type region layer 2a; 3a of the one conductive type MIS transistor 2; 3 and the opposite conductive type polycrystalline silicon film 31; 3
4 has a connection pad 42a of one conductivity type between the semiconductor device and the semiconductor device.

[0011]

According to the semiconductor device of the present invention, the gate electrodes of the opposite conductive type MIS transistors 33 and 36 on the upper UL side are formed by the opposite conductive type polycrystalline semiconductor films 31 and 34, and the opposite conductive type polycrystalline semiconductor films 31 and 34 are formed. Film 31; 34 into contact hole 12;
19 and is connected to the one conductivity type transistor 2; 3 below the contact hole 12; 19. Thus, it is not necessary to connect the upper element and the lower element through the contact hole formed in the upper interlayer insulating film, and the contact hole 12 is formed in the interlayer insulating film 24 for separating the upper and lower elements. 19, the upper and lower elements can be connected from here, the aspect ratio can be reduced, the coverage can be improved, and the occurrence of disconnection can be prevented.

In the contact holes 12 and 19,
Conductivity region layer 2a; 3a of one conductivity type MIS transistor 2; 3
By providing a connection pad 42a of one conductivity type between the polysilicon film 31 and the opposite conductivity type, the aspect ratio can be further reduced. This one-conductivity-type connection pad is provided between the other conductivity-type region layer 2b; 3b of the one-conductivity-type MIS transistor and the metal wiring layer 41 in the other contact hole 11; 14 (connection pad 42b). ,
The aspect ratio of the contact holes 11 and 14 can be reduced. Further, the silicide layers 15 and 18 constituting the gates of the other one conductivity type MIS transistors 4 and 5 formed in the lower layer LL are connected to the one conductivity type connection pads 42a.
By connecting to the conductivity type region layers 2a; 3a of the one conductivity type MIS transistor 2; 3 through the, the electrical connection can be improved.

[0013]

Embodiments of the present invention will be described below with reference to the accompanying drawings. FIG. 1 is a diagram showing an element on a lower layer side in an embodiment of a semiconductor device according to the present invention.
(a) is a plan view showing a lower element, and (b) is a circuit diagram showing a lower element.

In FIG. 1A, reference numeral 1 denotes a P-type semiconductor substrate (lower layer LL) made of silicon or the like, and four element formation regions 2 to 5 are defined on the surface of the semiconductor substrate 1. Of these, the second, diagonally opposed,
The third element formation region is continuous via an N-type element connection region layer 6, and these element formation regions 2 to 5 and the element connection region layer 6 are formed by an oxide film 7 formed by a selective oxidation method. being surrounded. Further, the element formation region 2
The upper surface of 5 is covered with a thermal oxide film 8 (see FIG. 3) formed by a thermal oxidation method.

Reference numeral 9 denotes a first gate electrode formed through a thermal oxide film 8 at a position orthogonal to the first element formation region 2 and the second element formation region 3. Are configured to be connected to the word line WL. In the first element formation region 2, N-type conductive layers (N-type impurity diffusion regions) 2 a and 2 b are formed on both sides of the gate electrode 9, and a part thereof is provided on the thermal oxide film 8. The first contact hole 11 and the second contact hole 12 are configured to be exposed. Similarly,
In the second element formation region 3, N-type conductive layers (N-type impurity diffusion regions) 3a and 3b are formed at both ends of the gate electrode 9,
One of the regions 3b is the third region provided on the thermal oxide film 8.
Exposed from the contact hole 14 and the other region 3a
Is configured to be connected to one end of the element connection region layer 6.

Reference numeral 15 denotes a second gate electrode formed on the third element formation region 4 via the thermal oxide film 8. The gate electrode 15 has an element connection region layer 6 on its side. One end is connected to the N-type conductive layer of the first element formation region 2 through the second contact hole 12, and the other end is provided on the thermal oxide film 8. It is connected to the N-type conductive layer 5 a at one end of the fourth element formation region 5 through the fourth contact hole 17. In the third element formation region 4, N-type conductive layers 4a and 4b are formed on both sides of the gate electrode 15. Reference 18
Is a third gate electrode formed on the fourth element formation region 5 with the thermal oxide film 8 interposed therebetween.
Are connected to the element connection region layer 6 through a fifth contact hole 19 provided in the substrate, and N-type conductive layers (N-type impurity diffusion regions) 5a and 5b are formed in the element formation regions 5 at both ends thereof. One of the regions 5a is exposed from the fourth contact hole 17 and is electrically connected to the second gate electrode 15, and the other region 5b is exposed from the sixth contact hole 21 provided in the thermal oxide film 8. And is connected to the V _ss voltage electrode 22.

In FIG. 1A, reference numeral 40 denotes
An eleventh contact hole provided in the thermal oxide film 8 is used to connect the V _ss voltage electrode with the layer 4b of the N-type conductive layers 4a and 4b on both sides of the second gate electrode, which is opposite to the element connection region layer 6. Are conducted. With this configuration, the first to fourth NMOS transistors are formed in the first to fourth element formation regions 2 to 5, respectively, and the first to fourth NMOS transistors are formed as shown in FIG. The drain region of the NMOS transistor 2 is the fourth
The source region of the NMOS transistor 5 and the gate electrode 15 of the third NMOS transistor 4 are electrically connected to each other.
The drain region of the transistor 3 is connected to the source region of the third NMOS transistor 4 and the gate electrode 18 of the fourth NMOS transistor 5.

FIGS. 2A and 2B are views showing an upper element in one embodiment of the semiconductor device of the present invention. FIG. 2A is a plan view showing a lower element, and FIG. FIG. In FIG. 2A, reference numeral 24 denotes an interlayer insulating film provided above the semiconductor substrate 1 on which the first to fourth NMOS transistors 2 to 5 are formed. Eighth and ninth contact holes 25 and 26 are formed in regions above the fifth contact holes 12 and 19. An L-shaped P is formed on the interlayer insulating film 24.
Mold melting recrystallized silicon films (upper layer UL) 27 and 28 are formed at two places, and oxide films 29 and 30 by thermal oxidation are formed thereon.

Reference numeral 31 denotes a CVD (Chemical Vapor Deposit).
position) is a fourth gate electrode made of polycrystalline silicon (polysilicon) formed by the method or the like.
Are formed at positions orthogonal to each other, and one end of the second N
Extending into a seventh contact hole 32 provided in the oxide film 30 on the mold-melted recrystallized silicon film 28, and the other end extending to an eighth contact hole 25 in the interlayer insulating film 24; The second gate electrode 15 in the second contact hole 12 shown in FIG. 1A is in contact with the drain region (N-type conductive layer) 2a of the first NMOS transistor 2. Further, P-type impurities are implanted into the first N-type molten recrystallized silicon film 27 on both sides of the electrode 31 to form P-type conductive layers 27a and 27b, thereby forming the first PMOS transistor 33. It is configured.

Reference numeral 34 denotes a fifth gate electrode made of polycrystalline silicon formed by a CVD method or the like. This gate electrode 34 has an oxide film 30 formed on a second P-type recrystallized silicon film 28. One end of which is connected to the P-type conductive layer 27b through a tenth contact hole 35 provided in the oxide film 29 on the first N-type molten recrystallized silicon film 27, The film 24 extends to the ninth contact hole 26, and is configured to contact the third gate electrode 18 and the element connection region layer 6 shown in FIG.
Further, a P-type impurity is implanted into the second N-type molten recrystallized silicon film 28 on both sides of the electrode 34 so that the P-type conductive layers 28a,
28b, thereby forming the second PMOS transistor 36b.
Is configured.

A circuit having such a structure is shown in FIG.
With shorting two mutually the gate and the drain of the PMOS transistor 33 and 36 as shown in, as shown in FIG. 5, the third NMOS transistor drain of the first PMOS transistor 33 via the diode D ₁ 4 connected to the drain also configured to connect the drain of the second PMOS transistor 36 to the drain of the fourth NMOS transistor 5 via the diode D _2.

In FIG. 2, reference numeral 37 denotes V _CC connected to the drains 27a and 28b of the PMOS transistors 33 and 36.
In FIG. 5, reference numeral 38 denotes a first CMOS inverter constituted by a first PMOS transistor 33 and a third NMOS transistor 4, and 39 denotes a second PM.
A second CMOS inverter including an OS transistor 36 and a fourth NMOS transistor 5 is shown.

In the embodiment described above, C- in FIG.
As shown in the side sectional view of FIG. 3 taken along the line C and the line DD in FIG. 2A, the gate electrode 31 of the first PMOS transistor 33 made of a polycrystalline silicon film is formed by a CVD method. The second contact hole 12 is formed so as to extend to the second contact hole 12, and the second contact hole 12 is formed in one interlayer insulating film 24, so that the aspect ratio is small and the coverage is improved. The occurrence of disconnection is prevented. Similarly, a second PM made of a polycrystalline silicon film
The gate electrode 34 of the OS transistor 36 is formed so as to extend to the fifth contact hole 19 by a CVD method or the like, and the fifth contact hole 19 is formed in one interlayer insulating film 24. In addition, the aspect ratio is small, the coverage is improved, and the occurrence of disconnection is prevented. Here, in FIG. 3, reference numeral 41 denotes a bit line BL (BL _B: BL _B is a bit line of an inversion level of BL)
And 43 denotes an insulating film.

As described above, according to the present embodiment, the gate electrode of the PMOS transistor 33 (36) on the upper layer UL is formed of the P-type polycrystalline semiconductor film 31 (34). 34) is extended to the contact hole 12 (19) and connected to the drain region 2a (3a) of the NMOS transistor 2 (3) below the contact hole 12 (19). Accordingly, there is no need to connect the upper element and the lower element through the contact hole formed in the upper interlayer insulating film, and the contact provided in the interlayer insulating film 24 for separating the upper and lower elements is not required. The upper and lower elements can be connected from the hole 12 (19). As a result, it is possible to reduce the aspect ratio of the contact hole, improve the coverage, and prevent the occurrence of disconnection.

FIG. 4 is a side sectional view showing a main part of another embodiment of the semiconductor device of the present invention. The semiconductor device shown in FIG.
Connection pad in the contact hole
42a and 42b are provided. That is, in response to demands for higher integration of semiconductor devices, SRAM memory cells are also miniaturized. In such miniaturized memory cells, each contact hole is also miniaturized, and the aspect ratio is reduced. With the increase, improvements in electrical connection will be required. Specifically, for example, in the second contact hole 12 of the semiconductor device of FIG. 3, the connection between the drain region 2a of the NMOS transistor 2 and the gate electrode 15 of the NMOS transistor 4 is made by a PMOS transistor formed of P-type polysilicon. 33 gate electrode 31 and N
Type silicide (eg, tungsten polycide: WSi
₂ / poly-Si 2000/1000 Å) Since the diffusion of impurities becomes remarkable at the interface with the gate electrode 15 of the NMOS transistor 4 formed by the method of FIG. Drain region
If the contact area between 2a and the gate electrode 15 of the NMOS transistor 4 cannot be sufficiently ensured, there is a problem that the electrical connection is insufficient, and the aspect ratio becomes large. The embodiment shown in FIG. 4 addresses such a problem, and further improves the aspect ratio and electrical connection of the contact hole.

As shown in FIG. 4, in the second contact hole 12 (fifth contact hole 19), the NMOS
An N-type transistor is provided between the drain region 2a (3a) of the transistor 2 (3) and the gate electrode 31 (34) of the PMOS transistor 33 (36) and the gate electrode 15 (18) of the NMOS transistor 4 (5). A polysilicon pad 42a is provided, and a first contact hole 11 (third contact hole 14) is provided between the source region 2b (3b) of the NMOS transistor 2 (3) and the aluminum wiring layer 41. , N-type polysilicon pads 42b are provided.

Thus, for example, in the second contact hole 12, the gate electrode 31 of the PMOS transistor 33 formed of P-type polysilicon is connected to the N-type silicide (for example, tungsten) through the N-type polysilicon pad 42a. Since polycide is connected to the gate electrode 15 of the NMOS transistor 4 formed of WSi ₂ / poly-Si 2000/1000 Å), contact failure due to diffusion of impurities does not occur, and the NMOS transistor 4 Gate electrode 15 and
Electrical connection with the drain region 2a of the NMOS transistor 2 (the gate electrode 31 of the PMOS transistor 33) is ensured. Further, by forming the polysilicon pad 42a on the drain region 2a of the NMOS transistor 2 in the second contact hole 12, the aspect ratio of the contact hole 12 can be reduced. Further, for example, also in the first contact hole 11, since the polysilicon pad 42b is formed on the source region 2b of the NMOS transistor 2, the aspect ratio of the contact hole 11 can be reduced. Here, with respect to the fifth contact hole 19, the electrical connection and the aspect ratio can be improved in the same manner as with the second contact hole 12, and the third contact hole 14) can be improved. As in the case of the first contact hole 11, the aspect ratio can be improved. Also, the polysilicon pad 42a in the second contact hole 12 and the polysilicon pad 42b in the first contact hole 11 can be formed in the same step.

FIG. 5 is a circuit diagram of a semiconductor device according to an embodiment of the present invention. Next, the operation of this embodiment will be briefly described with reference to FIG. First, in order to write a memory, a high-level signal “H” is applied to the bit line BL,
When a low-level signal “L” is applied to the bit line BL _B and a high-level signal “H” is input to the word line WL, the first CM
Since the input terminal t ₂ of the NMOS transistor 4 of the OS inverter 38 is at a high level “H”, the NMOS transistor 4 is turned on, and the input terminal t ₃ of the PMOS transistor 36 of the second CMOS inverter 39 and the input of the NMOS transistor 5 The end t ₁ becomes low level “L”, the NMOS transistor 5 is turned off, and the PMOS transistor 5 is turned off.
The transistor 36 is turned on, and t ₄ becomes high level “H”.

Here, since a voltage is applied to the diodes D ₁ and D ₂ connected in the CMOS inverters 38 and 39 in the positive direction, the current does not flow. Further, the state of the cell does not change even if the signal of the word line WL is set to the low level “L”.

Next, when reading the memory, a high-level "H" signal is applied to the word line WL so that the bit line BL
High level "H", and the bit line BL _B goes low "L". Then, by reading this, the state of the memory is determined. Here, the bit line BL
And if the signal applied to the other bit line BL _B Conversely, also reversed the read signal.

In the above embodiment, the lower element is
The semiconductor device in which the upper element is a PMOS transistor without the NMOS transistor has been described.
It is also possible to use a PMOS transistor and an NMOS transistor on the upper side. However, in this case, it is necessary to make the current flow from the conductivity type region layer of the PMOS transistor to the conductivity type region layer of the NMOS transistor.

[0032]

As described above, according to the semiconductor device of the present invention, it is not necessary to connect the upper element and the lower element through the contact hole formed in the upper interlayer insulating film. A contact hole is provided in the interlayer insulating film for isolating the lower element, from which the upper and lower elements can be connected, the aspect ratio can be reduced, the coverage can be improved, and the occurrence of disconnection can be prevented. Will be possible. In the contact hole, one conductivity type MIS
Polycrystalline silicon with conductivity type opposite to that of transistor conductivity region
By providing a connection pad of one conductivity type between
As a result, the aspect ratio can be further reduced.

[Brief description of the drawings]

FIG. 1 is a view showing a lower element in an embodiment of a semiconductor device according to the present invention.

FIG. 2 is a diagram showing an upper layer side element in one embodiment of the semiconductor device of the present invention.

FIG. 3 is a side sectional view showing a main part of one embodiment of the semiconductor device of the present invention.

FIG. 4 is a side sectional view showing a main part of another embodiment of the semiconductor device of the present invention.

FIG. 5 is a circuit diagram showing a semiconductor device according to an embodiment of the present invention.

FIG. 6 is a circuit diagram formed by an example of a conventional semiconductor device.

FIG. 7 is a diagram showing a lower layer element in an example of a conventional semiconductor device.

FIG. 8 is a diagram illustrating an upper element in an example of a conventional semiconductor device.

FIG. 9 is a side sectional view showing a main part of an example of a conventional semiconductor device.

FIG. 10 is a side sectional view showing a main part of another example of a conventional semiconductor device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Semiconductor substrate 2-5 ... Element formation area (NMOS transistor) 7 ... Oxide film 8 ... Thermal oxide film 9 ... Gate electrode 11 ... 1st contact hole 12 ... 2nd contact hole 24 ... Interlayer insulating film 27 ... Melting Recrystallized silicon film 30 Thermal oxide film 31 Fourth gate electrode 33 First PMOS transistor 36 Second PMOS transistor

Claims (6)

(57) [Claims] 1. A one conductivity type MIS Trang formed below
And register, the interlayer insulation laminated on the said one conductivity type MIS transistor
An edge film , a contact hole provided on the conductive type region layer of the one-conductivity type MIS transistor in the interlayer insulating film, and connected to the conductive type region layer of the one-conductivity type MIS transistor through the contact hole Opposite conductivity type polycrystalline silicon
And silicon film, a portion of the reflected Taishirube conductivity type polycrystalline silicon film in the gate electrode, comprising a opposite conductivity type MIS transistor on the upper layer side formed on the semiconductor film on the interlayer insulating film, the Conta
In the hole, the one-conductivity type MIS transistor
Between the conductive type region layer and the opposite conductive type polycrystalline silicon film.
A semiconductor device having a connection pad of one conductivity type between them . 2. The semiconductor device further includes another one-conductivity-type MIS transistor formed in a lower layer, and a silicide layer forming a gate of the other one-conductivity-type MIS transistor.
Is Oite the contact hole, the one conductivity type of which the semiconductor device according to claim 1, adapted to be connected to the conductive type region layer of the one conductivity type MIS transistor via connection pads. Wherein the semiconductor device, 4 is formed in the lower layer
One of the N-type MIS transistor and two P-type MIS transistor formed in the upper layer is <br/> in static random access memory having a plurality of memory cells composed of the semiconductor device according to claim 1. 4. A plurality of one conductivity type MISs formed in a lower layer.
A transistor, an interlayer insulation laminated on the said one conductivity type MIS transistor
An edge film; and a first one-conductivity-type MIS transistor of the interlayer insulating film.
A first contact provided on one conductivity type region layer of data
A hole , a metal wiring layer connected to one conductivity type region layer of the first one conductivity type MIS transistor through the first contact hole, and the first one conductivity type MIS of the interlayer insulating film. second con provided on the other conductivity type region layer of the transistor
And contact holes, and the opposite conductivity type polycrystalline silicon film is connected through the second contact hole to the other conductivity type region layer of said first conductivity type MIS transistors, one the reflected Taishirube conductivity type polycrystalline silicon film A MIS transistor on an upper layer side formed in a semiconductor film on the interlayer insulating film, with the first portion serving as a gate electrode ;
In the contact hole, the first one conductivity type MIS
One conductive type region layer of the transistor and the metal wiring layer;
A first connection pad of one conductivity type between
In the second contact hole, the first one conductivity type
The other conductivity type region layer of the MIS transistor and the opposite conduction
A second connection path of one conductivity type between
Wherein a has a head. 5. The semiconductor device according to claim 4 , wherein said first connection pad and said second connection pad are made of polysilicon formed in the same step. Wherein said semiconductor device comprises a second conductivity type MIS transistor formed in the lower layer to form a gate of the one conductivity type MIS transistor of the second Shirisai
De layer is adapted to be connected the Oite to the second contact hole, the one conductivity type region layer of said second of said first through connection pads of one conductivity type having one conductivity type MIS transistor 5. The semiconductor device according to claim 4 , wherein: