JPH07153854A - Perfect cmos type sram device - Google Patents

Abstract

PURPOSE:To reduce the cell area, i.e., increase the integration degree and speed up the signal processing. CONSTITUTION:A p-type impurity diffused layer 4a of a p-type transistor and n-type impurity diffused layer 4b of an n-type transistor which are components of an SRAM cell are formed in a semiconductor film layer of the same pattern so as to form a direct p-n junction (diode connection). Parts of gate electrodes 6a and 6a' formed on the upper part of the semiconductor film layer are connected through contact holes 8a and 8b to the impurity diffused layer 4b or/and 4a near the p-n junction.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a complete CMOS type SRAM device having memory cells formed on an SOI substrate.

[0002]

2. Description of the Related Art A P-channel thin film transistor (TF) is used as a memory cell of an SRAM for 4 Mb or 16 Mb.
A memory cell for SRAM using T) as a load transistor has been developed. The TFT load type SRAM memory cell consumes less power during standby and is excellent in stability as compared with the high resistance load type SRAM memory cell. Further, the load transistor is excellent in high integration as compared with a bulk CMOS memory cell for a complete SRAM in which a load transistor is formed on a semiconductor substrate.

However, the TFT load type SRAM memory cell has a problem that its manufacturing process is complicated. Therefore, the bulk CMOS complete SRA
The M memory cell is being reviewed. Bulk structure complete C
The MOS type SRAM memory has a simpler manufacturing process as compared with the TFT load type SRAM memory, can obtain a high current during operation, and is excellent in memory stability.

1993 VLSI technology (Te
ch. ) In pages 65 to 66 of the literature, a bulk structure complete CMOS SRA in which two word lines are arranged for each memory cell.
M devices have been developed. In the conventional bulk structure complete CMOS type SRAM device including those described in this document, in the memory cell, the N type impurity diffusion layer in the N type MOS transistor region and the P type MOS transistor region in the P type MOS transistor region are formed.
The type impurity diffusion layer is formed separately.

[0005]

However, it is difficult to electrically separate the N-type impurity diffusion layer and the P-type impurity diffusion layer formed on the silicon substrate from each other, and it is necessary to perform sufficient electric separation. When trying to do so, it was necessary to increase the separation width. Therefore, the area of the memory cell is increased, which may cause an increase in chip area and signal delay.

The present invention has been made in view of the above situation, and is a complete CMO capable of reducing the cell area, that is, increasing the degree of integration, and speeding up signal processing.
It is an object to provide an S-type SRAM device.

[0007]

To achieve the above object, a first complete CMOS type SRAM device according to the present invention comprises a P type impurity diffusion layer and an N type impurity diffusion layer of a P type transistor which are constituent elements of an SRAM cell. The N-type impurity diffusion layer of the transistor is formed so as to directly make a PN junction in the semiconductor thin film layer of the same pattern, and the N-type impurity diffusion layer near the PN junction is formed.
A part of the gate electrode formed on the semiconductor thin film layer is connected to the type impurity diffusion layer or the P type impurity diffusion layer through a contact hole.

To achieve the above object, a second complete CMOS type SRAM device according to the present invention comprises a P-type impurity diffusion layer of a P-type transistor and an N-type impurity diffusion of an N-type transistor which are constituent elements of an SRAM cell. Layer is formed so as to directly form a PN junction in the semiconductor thin film layer having the same pattern, and the upper portion of the semiconductor thin film layer is formed with respect to both the N-type impurity diffusion layer and the P-type impurity diffusion layer in the PN junction portion. A part of the gate electrode formed in is connected through a single contact hole.

In order to achieve the above object, a third complete CMOS type SRAM device according to the present invention is a P-type impurity diffusion layer of a P-type transistor and an N-type impurity diffusion of an N-type transistor which are constituent elements of an SRAM cell. Layers are formed so as to directly form a PN junction in the semiconductor thin film layer having the same pattern, and the word line for each SRAM cell is divided into two and arranged so as to be orthogonal to the bit line. .

[0010]

In the first complete CMOS type SRAM device according to the present invention, the element isolation can be designed with the minimum design by forming the SRAM cell on the SOI substrate.
In addition, a complete CMOS with a bulk structure on a normal semiconductor substrate
Since it is not necessary to form a well as compared with the case of forming a type SRAM device, the P-type impurity diffusion layer of the P-type transistor and the N-type impurity diffusion layer of the N-type transistor are formed in the semiconductor thin film layer of the same pattern. Can be formed so as to be directly PN-junctioned with.

With this PN junction, a diode is formed in the storage node portion extending from the load transistor side to the drive transistor side. However, in the SRAM memory cell, a forward bias is applied from the load transistor side to the drive transistor side. , It does not matter on the memory cell. In the first complete CMOS SRAM device according to the present invention, P
Since no insulating region is formed between the n-type impurity diffusion layer and the n-type impurity diffusion layer, the cell area can be reduced, that is, high integration can be achieved, and the signal processing speed can be increased.

A second complete CMOS SRA according to the present invention
In the M device, element isolation can be designed with a minimum design by forming the SRAM cell on the SOI substrate. In addition, a complete CM with a bulk structure on a normal semiconductor substrate
Since it is not necessary to form a well as compared with the case of forming the OS type SRAM device, the P type impurity diffusion layer of the P type transistor and the N type impurity diffusion layer of the N type transistor are formed into a semiconductor thin film layer of the same pattern. It can be formed so as to have a direct PN junction therein.

Moreover, a part of the gate electrode formed on the semiconductor thin film layer is connected to both the N-type impurity diffusion layer and the P-type impurity diffusion layer at the PN junction through a single contact hole. can do. Therefore, the influence of the diode formed by the PN junction can be almost ignored.

Second complete CMOS SRA according to the present invention
In the M device, since the insulating region is not formed between the P-type impurity diffusion layer and the N-type impurity diffusion layer, the cell area can be reduced, that is, the integration can be increased, and the signal processing speed can be increased. . In the third complete CMOS type SRAM device according to the present invention, the element isolation can be designed with the minimum design by forming the SRAM cell on the SOI substrate. Further, as compared with the case of forming a complete CMOS type SRAM device having a bulk structure on a normal semiconductor substrate, it is not necessary to form a well, so that the P of the P type transistor is formed.
The type impurity diffusion layer and the N type impurity diffusion layer of the N type transistor can be formed so as to be directly PN junctioned in the semiconductor thin film layer having the same pattern. Moreover, the word line for each SRAM cell is divided into two and arranged so as to be orthogonal to the bit line.

Generally, it is difficult to make the electrical characteristics of a transistor formed on an SOI substrate uniform as compared with a transistor formed on a normal semiconductor substrate.
By combining the word line division type cell adopted this time with the SOI structure, the geometrical symmetry of the cell is enhanced, the operational stability of the cell is improved, and the characteristic variation between the transistors is easily absorbed.

A third complete CMOS SRA according to the present invention
Since the M device does not form an insulating region between the P-type impurity diffusion layer and the N-type impurity diffusion layer and has a suitable word line pattern, the cell area can be reduced, the integration can be increased, and the signal processing can be performed. It is possible to increase the speed.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Complete CMOS type SRAM according to the present invention will be described below.
The device will be explained in more detail on the basis of an embodiment shown in the drawing.
FIG. 1 is a full CMOS SRAM according to an embodiment of the present invention.
2 is a plan view of a main part of a memory cell of the device, FIG. 2 is an equivalent circuit diagram of an SRAM memory cell according to the embodiment, and FIG. 3 is shown in FIG.
Sectional views taken along the line III-III, FIGS. 4A and 4B are sectional views of the essential parts showing the manufacturing process of the memory cell shown in FIG. 3, and FIGS. 5 to 9 are memory cells shown in FIGS. FIG. 10 is a plan view of the essential parts showing the manufacturing process of the same, and FIG. 10 is a complete CM according to another embodiment of the present invention.
FIG. 11 is a plan view of a main part of a memory cell of the OS type SRAM device.
12 is a cross-sectional view of an essential part of a memory cell of a complete CMOS type SRAM device according to still another embodiment of the present invention, FIG.
11A and 11B are cross-sectional views of the essential part showing the manufacturing process of the memory cell shown in FIG. 11, and FIG. 13 is an equivalent circuit diagram of the memory cell shown in FIG.

First, the complete C according to the embodiment shown in FIGS.
The MOS type SRAM device will be described. As shown in FIG. 1, the memory cell MC of the complete CMOS type SRAM device according to this embodiment is formed on an SOI substrate in which a semiconductor thin film layer having a predetermined pattern is formed on the insulating layer 2.

The SOI substrate is formed by, for example, a method combining a bonding method and a selective polishing method, or an O ₂ ion implantation method. In the method that combines the bonding method and the selective polishing method, after forming a step for element isolation on a semiconductor substrate such as a silicon wafer, an insulating layer is deposited on the surface, and a polysilicon layer or the like is formed on the surface of the insulating layer. A planarization layer is deposited and its surface is planarized. Then, a supporting substrate such as a silicon wafer is attached to the flattened surface. After that, selective polishing is performed from the back surface of the semiconductor substrate until the element isolation step is exposed to leave a semiconductor thin film layer having a predetermined pattern on the insulating layer.

As shown in FIG. 1, the semiconductor thin film layer contains P
The type impurity diffusion layer 4a and the N type impurity diffusion layer 4b are formed so as to be in contact with each other at the boundary portion 5. On the semiconductor thin film layer, gate electrodes 6a, 6a ', and
6b and 6b 'are laminated.

The gate electrodes 6b and 6b 'are the word lines W
It also serves as 1 and W2, and two memory cells are formed for each memory cell MC and arranged so as to be orthogonal to a bit line described later. The gate electrode 6 which becomes the word lines W1 and W2
b and 6b 'serve as gate electrodes of the selection transistors WQ3 and WQ4. The gate electrodes 6a and 6a 'have a substantially L-shape and are arranged between the word lines 6b and 6b' so as to be point-symmetrical to each other. The gate electrodes 6a and 6a 'intersect with the substantially T-shaped semiconductor thin film layers (impurity diffusion layers 4a and 4b) arranged at point-symmetrical positions in the memory cell MC, and drive transistors DQ1 and DQ2 and a load transistor LQ.
5 and LQ6.

The load transistors LQ5 and LQ6 are formed on the P-type impurity diffusion layer 4a, and the drive transistors DQ1 and DQ2 and the selection transistors SQ3 and SQ are formed.
4 is formed on the N-type impurity diffusion layer 4b. These transistors have contact holes 8a, 8b, 10a, and 10a in order to form the SRAM memory cell shown in FIG.
10b, 12a, 12b, 14a and 14b are connected to the upper wiring layer.

As shown in FIG. 2, the SRAM memory cell includes a pair of drive transistors DQ1 and DQ2 forming a flip-flop circuit, selection transistors SQ3 and SQ4 for selecting the memory cell, and a load transistor LQ5,
With LQ6. Select transistors SQ3, SQ4
Turns on the transistors according to the gate voltage generated on the word line W, and drives the transistors DQ1 and DQ2.
The information stored in the flip-flop circuit constituted by is transmitted to the bit line b and the inverted bit line b '.

Since the memory cell of this embodiment employs the structure described later, the load transistors LQ5,
A diode D is provided at each storage node portion which is a connection point from LQ6 to the drive transistors DQ1 and DQ2.
1, D2 is formed. These diodes D1 and D2 are
There is no problem in the circuit of the SRAM cell provided that it is connected in the forward direction. In the embodiment shown in FIG. 2, the diodes D1 and D2 are the load transistors LQ5 and LQ of the storage node.
Although connected to the Q6 side, drive transistors DQ1 and DQ
The same applies when formed on the Q2 side.

Next, the reason why such diodes D1 and D2 are formed will be described. In this embodiment, as shown in FIGS. 1 and 3, a P-type impurity diffusion layer 4a and an N-type impurity diffusion layer 4b are formed in a semiconductor thin film layer having the same pattern so as to form a PN junction at a boundary portion 5. To be done. Therefore, the forward bias diode D1 or D2 is formed at the boundary portion 5. As shown in FIGS. 1 to 3, the gate electrodes 6a and 6a 'of the drive transistors DQ1 and DQ2 and the load transistors LQ5 and LQ6 are
It is necessary to connect to the other storage node of the pair through the contact holes 8a and 8b. Gate electrodes 6a, 6
Since a'is generally composed of a polysilicon layer containing N-type impurities, the impurity diffusion layer of the storage node connected through the contact holes 8a and 8b is shown in FIG. 3 for impurity diffusion from the polysilicon layer. As shown, the N-type impurity diffusion layer 4b is formed.

[0026] In FIG. 3, reference numeral 16a denotes a channel portion of the load transistor LQ5, N ^- is an impurity diffusion region. Further, reference numeral 16b denotes a channel region of the select transistor SQ3, P ^- which is an impurity diffusion region. Further, reference numeral 18 is a gate insulating layer, which is composed of a silicon oxide layer or the like.

Next, a method of manufacturing a complete CMOS type SRAM device utilizing the SOI structure shown in FIGS. First, as shown in FIGS. 4A and 5, an SOI substrate in which the semiconductor thin film layer 16 is formed in a predetermined pattern on the insulating layer 2 is manufactured. The SOI substrate is manufactured by, for example, a method combining a bonding method and a selective polishing method. The gate insulating layer 1 is formed on the semiconductor thin film layer 16.
8 is formed. Gate insulating layer 18 is formed of, for example, a silicon oxide layer formed by a thermal oxidation method.

Further, impurities for adjusting the threshold voltage of the transistor are introduced into the semiconductor thin film layer 16 to form a P-type MOS.
An N ⁻ type impurity region 16a is formed in a region where a transistor will be formed, and a P ⁻ type impurity region 16b is formed in a region where an N type MOS transistor will be formed.

Next, after forming a contact hole 8a in the gate insulating layer 18 at a position corresponding to the storage node contact portion, as shown in FIG. 4 (B), the gate insulating layer 1 is formed.
A polysilicon layer 6 to be a gate electrode is deposited on the gate electrode 8. Before forming the contact hole 8a, an oxide film protective layer made of a polysilicon layer or the like may be formed on the surface of the gate insulating layer 18.

Next, the polysilicon layer 6 to be the gate electrode
As shown in FIG. 6, patterning is performed to drive the drive transistors DQ1 and DQ2 and the load transistors LQ5 and LQ.
The gate electrodes 6a and 6a 'of Q6 and the selection transistor S
Gate electrodes 6b and 6b '(word lines W1 and W2) to be Q3 and SQ4 are formed. At that time, the gate electrodes 6a,
6a 'is connected to the impurity diffusion layers of the paired storage nodes through the contact holes 8a and 8b.

Next, as shown in FIG. 6, selective ion implantation is performed on the semiconductor thin film layer from above the gate electrode to form the source / drain region P of each transistor.
A type impurity diffusion layer 4a and an N type impurity diffusion layer 4b are formed. After the ion implantation, heat treatment is performed to diffuse the impurities. By the heat treatment, the N-type impurities contained in the polysilicon layers forming the gate electrodes 6a and 6a ′ are diffused to the surface of the semiconductor thin film layer through the contact holes 8a and 8b, and the conductivity type of the semiconductor thin film layer at the contact portion is diffused. Becomes N-type continuous with the N-type impurity diffusion layer 4b, as shown in FIG. Further, as shown in FIG. 3, a diode D1 is formed at the boundary between the P-type impurity diffusion layer 4a and the N-type impurity diffusion layer 4b. Although not shown, the diode D2 is similarly formed. In addition, in FIG.
Although the width of the gate electrode is the same as the width of the contact holes 8a and 8b in the figure, it is preferable to design so that the gate electrode overlaps the contact hole.

Next, as shown in FIG. 7, after depositing a first interlayer insulating layer on the gate electrode, the contact hole 1 is formed.
0a, 10b, 12a, 12b, 14a, 14b are formed. Examples of the first interlayer insulating layer include a silicon oxide layer, a silicon nitride layer, a PSG layer and a BPSG layer. The contact holes 10a and 10b are holes for bit line contact, and the contact hole 1
Reference numerals 2a and 12b are holes for the power supply line Vdd contact, and contact holes 14a and 14b are holes for the reference potential line Vss contact.

Next, a first aluminum layer is formed on the first interlayer insulating layer, as shown in FIG. The first aluminum layer is formed of the patterns 20a, 20b, 22, 24a, 24 shown in FIG.
Etching is performed in b. In the first aluminum layer, the patterns 20a and 20b show the pattern of the power supply line Vdd.
The pattern 22 is a pad layer pattern for lifting to the reference potential line Vss composed of the second layer aluminum. The patterns 24a and 24b are patterns of pad layers for shifting the contact positions with the bit lines b and b'composed of the second layer aluminum.

Next, as shown in FIG. 9, a second interlayer insulating layer is formed on the first aluminum layer, and contact holes 26, 28a, 28b are formed in the second interlayer insulating layer. The second interlayer insulating layer is not particularly limited, but is, for example, a silicon oxide layer, a silicon nitride layer, a PSG layer, a BPSG.
It is composed of layers. The contact hole 26 is a hole for contacting the reference potential line Vss, and the contact holes 28a, 28b are holes for the bit lines b, b '.

Next, a second aluminum layer is deposited on the second interlayer insulating layer, and the second aluminum layer is formed into a pattern 30 shown in FIG.
Etching is performed with 32a and 32b to obtain the reference potential line Vss and the bit lines b and b '. After that, an overcoat layer, a pad layer, etc. are formed to complete the CMOS type SRA.
Manufacture M device. Note that the memory cells MC are laid out in a line object in the vertical direction and the horizontal direction and are formed in large numbers. Further, peripheral circuits such as a data writing circuit and a data reading circuit for the cells are formed around the memory cell group.

In the complete CMOS type SRAM device according to this embodiment, the element isolation can be designed with the minimum design by forming the SRAM cell on the SOI substrate.
In addition, a complete CMOS with a bulk structure on a normal semiconductor substrate
Since it is not necessary to form a well as compared with the case of forming a type SRAM device, the P-type impurity diffusion layer of the P-type transistor and the N-type impurity diffusion layer of the N-type transistor are formed in the semiconductor thin film layer of the same pattern. Can be formed so as to be directly PN-junctioned with.

With this PN junction, the load transistor L
The diodes D1 and D2 are formed in the storage node portion extending from the Q5 and LQ6 sides toward the drive transistors DQ1 and DQ2 side. However, in the SRAM memory cell, the load transistor side to the drive transistor side are forward biased. There is no problem in memory cells.

That is, in the complete CMOS SRAM device according to this embodiment, since no insulating region is formed between the P-type impurity diffusion layer 4a and the N-type impurity diffusion layer 4b, the cell area is reduced, that is, the degree of integration is increased. It is possible to achieve high speed of signal processing. Further, by arranging two word lines W1 and W2 for each cell to form a word line division type cell, and combining this word line division type cell with the SOI structure, the geometric symmetry of the cell is increased, Operational stability is improved, and variations in characteristics between transistors are easily absorbed.

The present invention is not limited to the above-mentioned embodiments, but can be variously modified within the scope of the present invention. For example, as shown in FIG. 10, as compared with the embodiment shown in FIG. 1, the driving transistors DQ1 and DQ2 are
A memory cell MC 'having a layout in which the positions of the load transistors LQ5 and LQ6 are reversed is also conceivable. In the case of this embodiment, the positional relationship between the contact holes 14a, 14b for the reference potential line Vss and the contact holes 12a, 12b for the power supply line Vdd is also reversed, but other than that, it is the same as the above-mentioned embodiment. It has various effects.

Next, the embodiment shown in FIGS. 11 to 13 will be described. FIG. 11 is a sectional view corresponding to the sectional view shown in FIG. 3 of the above embodiment. In this embodiment, the gate electrode 3
6a and 36b have a multi-layer structure of a lower layer side gate electrode 30 and an upper layer side gate electrode 32. Further, at the contact hole 8a portion of the storage node, the gate electrodes 36a, 36
The upper gate electrode 32 forming a part of b contacts the surface of the semiconductor thin film layer, and this contacts the P-type impurity diffusion layer 4
It is connected to both a and the N-type impurity diffusion layer 4b. The lower gate electrode 30 also serves as a protective layer for protecting the oxide film forming the gate insulating layer 18, and is made of a polysilicon layer or the like. In addition, the upper gate electrode 3
2 is made of a refractory metal such as titanium or tungsten.

At least the contact portion that enters the contact hole 8a for the storage node is made of a conductive material containing no impurities, so that impurities are prevented from diffusing into the semiconductor thin film layer through the contact hole 8a. Portions can contact both the P-type impurity diffusion layer 4a and the N-type impurity diffusion layer 4b through the same contact hole 8a.

If such a contact can be realized, unlike the above embodiment, the influence of the diode formed at the boundary portion 5 between the P-type impurity diffusion layer 4a and the N-type impurity diffusion layer 4b can be almost ignored, and FIG. As shown, a complete CMOS SRAM cell in which no diode is formed can be realized.

In order to realize such contact, first, as shown in FIG. 12A, an SOI substrate in which the semiconductor thin film layer 16 is formed in a predetermined pattern on the insulating layer 2 is manufactured. The SOI substrate is manufactured by, for example, a method combining a bonding method and a selective polishing method. A gate insulating layer 18 is formed on the semiconductor thin film layer 16. Gate insulating layer 18 is formed of, for example, a silicon oxide layer formed by a thermal oxidation method.

Further, impurities for adjusting the threshold voltage of the transistor are introduced into the semiconductor thin film layer 16 to form a P-type MOS.
An N ⁻ type impurity region 16a is formed in a region where a transistor will be formed, and a P ⁻ type impurity region 16b is formed in a region where an N type MOS transistor will be formed.

Next, the lower gate electrode 3 also serving as a protective layer
A polysilicon layer to be 0 is deposited with a film thickness of about 30 nm, for example. After that, a contact hole 8a is formed in the storage node portion. Thereafter, as shown in FIG. 12B, a non-doped conductive layer (for example, a refractory metal) forming upper gate electrode 32 is deposited, and the contact is buried in hole 8a. In the subsequent steps, except that the upper gate electrode 32 is simultaneously connected to the bipolar impurity diffusion layers 16a and 16b at the contact hole 8a,
This is similar to the above embodiment.

In addition to the operation and effect of the above-mentioned embodiment, this embodiment further has the operation and effect that the influence of the diode formed by the PN junction can be almost ignored. In this embodiment, the gate electrode is not necessarily multi-layered but may be composed of a single layer of refractory metal containing no impurities. Further, only the contact portion for the storage node may be made of a refractory metal different from the material forming the gate electrode.

[0047]

As described above, in the first complete CMOS type SRAM device according to the present invention, the element isolation can be designed with the minimum design by forming the SRAM cell on the SOI substrate. In addition, it is not necessary to form a well as compared with the case of forming a complete CMOS type SRAM device having a bulk structure on a normal semiconductor substrate.
The P-type impurity diffusion layer of the P-type transistor and the N-type impurity diffusion layer of the N-type transistor can be formed so as to make a direct PN junction in the semiconductor thin film layer of the same pattern.

With this PN junction, a diode is formed in the storage node portion extending from the load transistor side to the drive transistor side. However, in the SRAM memory cell, a forward bias is applied from the load transistor side to the drive transistor side. , It does not matter on the memory cell. In the first complete CMOS SRAM device according to the present invention, P
Since no insulating region is formed between the n-type impurity diffusion layer and the n-type impurity diffusion layer, the cell area can be reduced, that is, high integration can be achieved, and the signal processing speed can be increased.

Second complete CMOS SRA according to the present invention
In the M device, element isolation can be designed with a minimum design by forming the SRAM cell on the SOI substrate. In addition, a complete CM with a bulk structure on a normal semiconductor substrate
Since it is not necessary to form a well as compared with the case of forming the OS type SRAM device, the P type impurity diffusion layer of the P type transistor and the N type impurity diffusion layer of the N type transistor are formed into a semiconductor thin film layer of the same pattern. It can be formed so as to have a direct PN junction therein.

Moreover, a part of the gate electrode formed on the semiconductor thin film layer is connected to both the N-type impurity diffusion layer and the P-type impurity diffusion layer at the PN junction through a single contact hole. can do. Therefore, the influence of the diode formed by the PN junction can be almost ignored.

Second complete CMOS type SRA according to the present invention
In the M device, since the insulating region is not formed between the P-type impurity diffusion layer and the N-type impurity diffusion layer, the cell area can be reduced, that is, the integration can be increased, and the signal processing speed can be increased. . In the third complete CMOS type SRAM device according to the present invention, the element isolation can be designed with the minimum design by forming the SRAM cell on the SOI substrate. Further, as compared with the case of forming a complete CMOS type SRAM device having a bulk structure on a normal semiconductor substrate, it is not necessary to form a well, so that the P of the P type transistor is formed.
The type impurity diffusion layer and the N type impurity diffusion layer of the N type transistor can be formed so as to be directly PN junctioned in the semiconductor thin film layer having the same pattern. Moreover, the word line for each SRAM cell is divided into two and arranged so as to be orthogonal to the bit line.

Generally, it is difficult to make the electrical characteristics of a transistor formed on an SOI substrate uniform as compared with a transistor formed on a normal semiconductor substrate.
By combining the word line division type cell adopted this time with the SOI structure, the geometrical symmetry of the cell is enhanced, the operational stability of the cell is improved, and the characteristic variation between the transistors is easily absorbed.

Third Complete CMOS Type SRA According to the Present Invention
Since the M device does not form an insulating region between the P-type impurity diffusion layer and the N-type impurity diffusion layer and has a suitable word line pattern, the cell area can be reduced, the integration can be increased, and the signal processing can be performed. It is possible to increase the speed.

The complete CMOS type SRAM device according to the present invention can be suitably used as a memory for ASIC.

[Brief description of drawings]

FIG. 1 is a plan view of a main part of a memory cell of a complete CMOS SRAM device according to an embodiment of the present invention.

FIG. 2 is an equivalent circuit diagram of the SRAM memory cell according to the embodiment.

FIG. 3 is a cross-sectional view of essential parts taken along the line III-III shown in FIG.

4A and 4B are cross-sectional views of a main part showing a manufacturing process of the memory cell shown in FIG.

FIG. 5 is a plan view of relevant parts showing a manufacturing process of the memory cell shown in FIGS.

6 is a plan view of relevant parts showing a step subsequent to that shown in FIG. 5;

7 is a plan view of relevant parts showing a step subsequent to that shown in FIG. 6;

8 is a plan view of relevant parts showing a step subsequent to that shown in FIG. 7. FIG.

9 is a plan view of relevant parts showing a step subsequent to that shown in FIG. 8;

FIG. 10 is a complete CM according to another embodiment of the present invention.
FIG. 3 is a plan view of a main part of a memory cell of an OS type SRAM device.

FIG. 11 is a cross-sectional view of essential parts of a memory cell of a complete CMOS SRAM device according to still another embodiment of the present invention.

12A and 12B are cross-sectional views of the essential part showing the manufacturing process of the memory cell shown in FIG. 11.

FIG. 13 is an equivalent circuit diagram of the memory cell shown in FIG. 11.

[Explanation of symbols]

2 ... Insulating layer 4a ... P-type impurity diffusion layer 4b ... N-type impurity diffusion layer 5 ... Border part 6a, 6a ', 6b, 6b' ... Gate electrode 8a, 8b ... Contact hole 10a, 10b, 12a for storage node , 12b, 14a, 14b ...
Contact hole 16 ... Semiconductor thin film layer 18 ... Gate insulating layer MC ... Memory cell DQ1, DQ2 ... Drive transistor SQ3, SQ4 ... Select transistor LQ5, LQ6 ... Load transistor b ... Bit line b '... Inverted bit line W, W1, W2 ... Word line MC, MC '... Memory cell

Claims (4)

[Claims] 1. A complete CMOS type SR is formed on an SOI substrate in which a semiconductor thin film layer having a predetermined pattern is formed on an insulating layer.
A complete CMOS type SRAM device in which an AM cell is formed, wherein a P-type impurity diffusion layer of a P-type transistor and a N-type impurity diffusion layer of an N-type transistor, which are constituent elements of the SRAM cell, have the same pattern. Part of the gate electrode formed above the semiconductor thin film layer with respect to the N-type impurity diffusion layer or the P-type impurity diffusion layer near the PN junction portion, which is formed so as to directly make a PN junction in the layer. , A complete CMOS SRAM device connected through contact holes. 2. A complete CMOS type SR is formed on an SOI substrate in which a semiconductor thin film layer having a predetermined pattern is formed on an insulating layer.
A complete CMOS type SRAM device in which an AM cell is formed, wherein a P-type impurity diffusion layer of a P-type transistor and a N-type impurity diffusion layer of an N-type transistor, which are constituent elements of the SRAM cell, have the same pattern. Part of the gate electrode formed on the semiconductor thin film layer for both the N-type impurity diffusion layer and the P-type impurity diffusion layer of the PN junction portion formed directly in the layer. , A full CMOS SRAM device connected through a single contact hole. 3. A complete CMOS type SR on an SOI substrate in which a semiconductor thin film layer having a predetermined pattern is formed on an insulating layer.
A complete CMOS type SRAM device in which an AM cell is formed, wherein a P-type impurity diffusion layer of a P-type transistor and a N-type impurity diffusion layer of an N-type transistor, which are constituent elements of the SRAM cell, have the same pattern. A complete CMOS type SR is formed so that the PN junction is directly formed in the layer, and the word line for each SRAM cell is divided into two and arranged so as to be orthogonal to the bit line.
AM device. 4. The complete CMOS type SRAM device according to claim 1, wherein the word line for each SRAM cell is divided into two and arranged so as to be orthogonal to the bit line.