JP3070099B2 - Static RAM - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a static RAM,
In particular, a new static RAM that can reduce the cell area
About.

[0002]

2. Description of the Related Art In a static RAM, a driver transistor and a switching transistor are generally formed in a bulk (semiconductor substrate), and their gate electrodes are usually formed on the same surface of the semiconductor substrate at the same time.

FIG. 10 is a plan view of a conventional example of a static RAM cell, and FIG. 11 is a circuit diagram of the static RAM cell (regardless of the conventional example and the present invention). The lower left corner of FIG. 10 is an arrangement diagram showing the arrangement of each cell by F, and the lower right cell of the four cells in this arrangement diagram is shown in FIG.

In FIG. 10 (and FIG. 2 to be described later), a hatched portion descending to the left is a wiring layer made of, for example, polycide, and includes gate electrodes (word lines) of switching transistors Q1 and Q2 and a driver transistor Q3. , Q4. The satin pattern portion is a field region, and the white portions other than the field region are diffusion regions forming a source and a drain. The hatched portions going down to the right are the contacts of Vss and bit lines, the rectangles and the diagonal portions thereof are the contact portions between the gate electrode and the semiconductor substrate, and conventionally at least 3 contacts per memory cell. Needed. In the figure, a, b, c, and d indicate nodes.
Incidentally, for example, high resistance loads R1, R
2, is formed so as to overlap the gate electrodes of the driver transistors Q3 and Q4 and does not affect the cell size, and is not shown.

[0005]

Although the demand for improvement in the degree of integration of static RAMs is increasing, it is becoming difficult to meet the demands. This is mainly due to the fact that the gate electrodes of the driver transistor and the switching transistor are formed as the same layer in the conventional static RAM, so that the arrangement of the driver transistor and the switching transistor is strongly restricted. And it is the first
Secondly, a sufficient gap is required between the gate electrodes of the driver transistor and the switching transistor, which hinders the degree of integration. Second, the number of contacts between the gate electrode and the substrate must be as high as three per cell. As a result, the three contact portions e, f, and g occupy an area that cannot be ignored.

The first contact portion e makes contact between the drain d of the driver transistor Q4 and the gate electrode of the driver transistor Q3, and the second contact portion f makes the drain c of the driver transistor Q3 and the gate of the driver transistor Q4. The third contact part g makes contact with the electrode, and the driver transistor Q3
And the source region of the switching transistor Q2 on the side opposite to the bit line is contacted. In the conventional static RAM, three contact portions e, f, and g were necessarily required for each cell.

SUMMARY OF THE INVENTION The present invention has been made to solve such a problem.
An object of the present invention is to increase the storage capacity and the density of an AM.

[0008]

SUMMARY OF THE INVENTION The present invention provides a static RA.
M forms a switching transistor and a driver transistor in the SOI layer, and connects these gate electrodes to the SOI layer.
The layers are formed on opposite sides of each other.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The static RAM according to the present invention will be described below in detail with reference to the illustrated embodiments. FIG. 1 is a sectional view showing one embodiment of the static RAM of the present invention, and FIG. 2 is a plan view showing a layout example. In the figure, 1 is a silicon semiconductor substrate, 2 is a bonding polysilicon layer, 3 is an insulating film, 4 is a high resistance load element made of polysilicon, 5 is an insulating film, 6 is a switching transistor Q1 or Q2.
6a is a polysilicon layer, 6b is, for example, a tungsten silicide layer,
The gate electrode 6 is shown by a thick solid line in FIG.
Reference numeral 7 denotes a gate insulating film of the switching transistor formed on the back surface of the SOI layer 8. 9 is an element isolation insulating film formed by embedding, and 10 is
Source formed by doping the type impurity /
This is a drain region. In the SOI layer 8, switching transistors Q1, Q2 and driver transistors Q3, Q4
Are formed.
Reference numeral 11 denotes a gate insulating film of the driver transistor formed on the surface of the SOI layer 8. The gate insulating film 11 is made thinner than the gate insulating film 7 although a difference is not clearly shown in the drawing. This is because it is desirable for the switching transistors Q1 and Q2 to form the gate insulating film 7 slightly thicker in order to stabilize the switching operation, whereas the driver transistor Q
This is because, for Q3, it is desirable to form the gate insulating film 11 thinner in order to ensure high-speed operation and the like. 1
Reference numeral 2 denotes a gate electrode formed of polycide of the driver transistor formed on the surface of the gate insulating film 11, 12a denotes a polysilicon film, and 12b denotes a tungsten silicide film.

As described above, in the present static RAM, a switching transistor and a driver transistor are formed on the SOI layer 8 formed by wafer bonding.
Since the gate electrode 6 of the switching transistor is formed on the back surface of the SOI layer 8 and the gate electrode 12 of the driver transistor is formed on the front surface of the SOI layer 8, the arrangement of the driver transistors Q3, Q4 and the switching transistors Q1, Q2 is inevitable. Of the driver transistors Q3 and Q3 as shown in FIG.
4 and the switching transistors Q1, Q
The distance between the second gate electrode (word line) 6 and the gate electrode 6 when viewed from above can be made extremely small. Moreover, the contact part of the gate electrode to the SOI layer 8 includes a contact g connecting the gate electrode of the driver transistor Q3 to the switching transistor Q2 and the source / drain region of the driver transistor Q4, and a contact g connecting the driver transistor Q4 and the gate electrode to the switching transistor Q1. , Driver transistor Q3
Since only two contacts f are required to be connected to the source / drain regions, the occupied area of the contact portion is reduced. From the above, the cell area is actually 20 to 30% higher than the conventional one.
It became possible to make it narrow.

The gate electrodes 6 of the driver transistors Q3, Q4 and the switching transistors Q1, Q2
Is formed on the opposite surface of the SOI layer 8,
The driver transistor and the switching transistor have completely different gate insulating films 7 and 11. Therefore,
By setting the thicknesses of the gate insulating films 7 and 11 individually, the gate insulating film 11 having an optimum thickness for the driver transistors Q3 and Q4, and the optimum thickness for the switching transistors Q1 and Q2. The gate insulating film 7 can be formed, and the performance of the static RAM can be further improved.

FIGS. 3 to 10 are sectional views showing a method of manufacturing the static RAM shown in FIG. 1 in the order of steps. (1) A semiconductor substrate 13 to be an SOI layer is formed, its surface is selectively etched, and an insulating film is buried in the etched portion to form an element isolation insulating film as shown in FIG. (2) Next, a gate insulating film 7 is formed by thermal oxidation,
Gate electrode 6 (6a, 6b) of the switching transistor
), And then, as shown in FIG.
To cover the semiconductor substrate 13. (3) Next, a contact hole 5a is formed in the insulating film 5, and then a high resistance load film 4 made of polysilicon is formed as shown in FIG. (4) Next, the surface on the high resistance load film 4 side is covered with the insulating film 3, a polysilicon layer 2 for wafer bonding is further formed, and the semiconductor substrate 13 is separated from the surface of the polysilicon layer 2 by another semiconductor. It is bonded to the surface of the substrate 1. FIG. 6 shows a state after wafer bonding with the semiconductor substrate 13 facing upward.

(5) Next, the back surface of the semiconductor substrate 13 is polished to form the SOI layer 8 as shown in FIG. The polished surface is defined as the surface of the SOI layer 8, and the opposite surface is defined as S
The back surface of the OI layer 8. (6) Next, as shown in FIG. 8, the gate insulating film 11 and the gate electrode 1 of the driver transistor are formed on the surface of the SOI layer 8.
Form 2 (7) Then, as shown in FIG. 9, the source / drain regions 10, 10,... Are formed by ion-implanting an n-type impurity with a portion serving as a channel of the switching transistor being masked by the resist film. Then, when the resist film 14 is removed, a static RAM as shown in FIG. 1 is completed. Thereafter, formation of an interlayer insulating film, formation of a contact hole, and formation of an electrode are performed by a normal static RAM manufacturing method.

In this embodiment, a high resistance load film made of polysilicon is formed on the back side of the SOI layer 8 as a load element, but this is not always necessary.
It may be formed on the surface side of the SOI layer 8. However, when formed on the back side of the SOI layer 8, the resistance length can be increased, and the layout becomes easy.

[0015]

According to the static RAM of the present invention, at least a switching transistor and a driver transistor are formed in an SOI layer formed by wafer bonding, and a gate electrode of the switching transistor and a gate electrode of the driver transistor are mutually connected to each other in the SOI layer. It is characterized by being formed on the opposite surface. Therefore, according to the present static RAM, the constraint on the positional relationship between the driver transistor and the switching transistor and the gate electrode thereof is weakened, the layout becomes easy, and the distance between the gate electrode of the driver transistor and the switching transistor as viewed from above is reduced. It becomes possible.
Further, the number of contacts per cell between the SOI layer and the gate electrode of the driver transistor can be reduced. Therefore, the cell area can be reduced, and the static RA
The capacity and integration of M can be increased. And
Since the gate insulating film is formed separately for the driver transistor and the switching transistor, the threshold voltage and the like can be made different between the driver transistor and the switching transistor, so that the driver transistor and the switching transistor can have unique characteristics. Can improve the performance of the static RAM.

[Brief description of the drawings]

FIG. 1 is a sectional view showing one embodiment of a static RAM of the present invention.

FIG. 2 is a plan view showing one layout example of a static RAM as shown in FIG.

FIG. 3 shows a first example of the manufacture of the static RAM shown in FIG. 1;
It is sectional drawing which shows the process of FIG.

FIG. 4 shows a second example of the manufacture of the static RAM shown in FIG.
It is sectional drawing which shows the process of FIG.

FIG. 5 shows a third example of the manufacture of the static RAM shown in FIG. 1;
It is sectional drawing which shows the process of FIG.

FIG. 6 shows a fourth example of the manufacture of the static RAM shown in FIG. 1;
It is sectional drawing which shows the process of FIG.

FIG. 7 shows a fifth example of the manufacture of the static RAM shown in FIG. 1;
It is sectional drawing which shows the process of FIG.

FIG. 8 shows a sixth example of the manufacture of the static RAM shown in FIG. 1;
It is sectional drawing which shows the process of FIG.

FIG. 9 is a seventh view of the manufacture of the static RAM shown in FIG. 1;
It is sectional drawing which shows the process of FIG.

FIG. 10 is a sectional view showing a conventional example of a static RAM.

FIG. 11 is a circuit diagram of a cell of a static RAM (common to the present invention and a conventional example).

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Wafer 6 Gate electrode of switching transistor 7 Gate insulating film of switching transistor 8 SOI layer 11 Gate insulating film of driver transistor 12 Gate electrode of driver transistor

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 21/8244 H01L 21/336 H01L 27/11 H01L 27/12

Claims (1)

(57) [Claims] 1. An S layer formed by wafer bonding.
A static RAM, wherein at least a switching transistor and a driver transistor are formed in the OI layer, and a gate electrode of the switching transistor and a gate electrode of the driver transistor are formed on opposite sides of the SOI layer.