JPH04215473A - Static ram - Google Patents

Abstract

PURPOSE:To provide a large-capacity and high-density static RAM by forming driver transistors and switching transistors in an SOI layer, on opposite sides of which the gate electrodes of the respective transistors are formed. CONSTITUTION:Driver transistors Q3 and Q4 have their gate electrodes 6 on one side of an SOI layer 8, while switching transistors Q1 and Q2 have their gate electrodes on the other side of the SOI layer. The driver transistors and the switching transistors include different gate insulator films 7 and 11. These insulator films can have different thicknesses that are optimal for the respective transistors. This improves the performance of a static RAM. Further, since the restriction on gate position can be relaxed, layout becomes easy, and the spacing between transistors is decreased.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] The present invention relates to static RAM,
New static RAM that can especially reduce cell area
Regarding.

0002

2. Description of the Related Art In a static RAM, a driver transistor and a switching transistor are generally formed in a bulk (semiconductor substrate), and gate electrodes of these transistors are generally formed simultaneously on the same surface of the semiconductor substrate.

FIG. 10 is a plan view of a conventional example of a static RAM cell, and FIG. 11 is a circuit diagram of a static RAM cell (
Regardless of the conventional example or the present invention). The lower left corner of FIG. 10 is a layout diagram showing the arrangement with each cell represented by F, and FIG. 10 shows the lower right cell among the four cells in this layout diagram.

In FIG. 10 (and FIG. 2, which will be described later), the hatched portions that descend toward the left are wiring layers made of polycide, for example, and include gate electrodes (word lines) of switching transistors Q1 and Q2, and driver transistor Q3. , and form the gate electrode of Q4. The satin-patterned portion is the field region, and the white portion other than the field region is the diffusion region forming the source and drain. The hatched area that descends toward the right is the Vss and bit line contact, and the rectangle and its diagonal line are the contact area between the gate electrode and the semiconductor substrate. It was necessary in some places. In the figure, a, b, c, and d indicate nodes. In addition, for example, high resistance loads R1 and R made of polycrystalline silicon
2 is formed to overlap the gate electrodes of the driver transistors Q3 and Q4, and is not shown because it does not affect the cell size.

[0005]

By the way, although there is an ever-increasing demand for an improvement in the degree of integration of static RAMs, it is becoming increasingly difficult to meet this demand. The main reason for this is that in the conventional static RAM, the gate electrodes of the driver transistor and the switching transistor are formed in the same layer, so the arrangement of the driver transistor and the switching transistor is strongly restricted. Firstly, it requires a sufficient gap between the gate electrodes of the driver transistor and the switching transistor, which impedes the degree of integration, and secondly, the number of contacts between the gate electrode and the substrate is 3 per cell. is also required, and these 3
This leads to the contact portions e, f, and g occupying a non-negligible area.

Incidentally, the first contact part e makes contact between the drain d of the driver transistor Q4 and the gate electrode of the driver transistor Q3, and the second contact part f makes contact between the drain c of the driver transistor Q3 and the gate of the driver transistor Q4. The third contact part g is in contact with the electrode, and the third contact part g is the driver transistor Q3.
A contact is made between the gate electrode of the switching transistor Q2 and the source region of the switching transistor Q2 on the side opposite to the bit line. In a conventional static RAM, three contact portions e, f, and g are required for each cell.

[0007] The present invention has been made to solve these problems, and it is possible to reduce the static radius by narrowing the cell area.
The purpose is to increase the memory capacity and density of AM.

[0008]

[Means for solving the problems] Static RA of the present invention
M forms a switching transistor and a driver transistor in the SOI layer, and connects their gate electrodes to the SOI layer.
It is characterized by being formed on opposite sides of the layers.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The static RAM of the present invention will be explained in detail below according to the illustrated embodiments. FIG. 1 is a sectional view showing one embodiment of the static RAM of the present invention, and FIG. 2 is a plan view showing an example of the layout. In the figure, 1 is a silicon semiconductor substrate, 2 is a polysilicon layer for bonding, 3 is an insulating film, 4 is a high resistance load element made of polysilicon, 5 is an insulating film, and 6 is a polycide of switching transistor Q1 or Q2. In the gate electrode, 6a is a polysilicon layer, and 6b is, for example, a tungsten silicide layer, and the gate electrode 6 is shown by a very thick solid line in FIG. 7 is a gate insulating film of a switching transistor formed on the back surface of the SOI layer 8. 9 is an element isolation insulating film formed by embedding, and 10 is an n-type film in the SOI layer 8.
The source/source formed by doping type impurities
This is the drain region. The SOI layer 8 includes switching transistors Q1 and Q2 and driver transistors Q3 and Q4.
Both source/drain regions 10 are formed. 11 is a gate insulating film of the driver transistor formed on the surface of the SOI layer 8. This gate insulating film 11 is thinner than the gate insulating film 7, although the difference is not clearly shown in the drawings. This is because while it is desirable for the switching transistors Q1 and Q2 to form the gate insulating film 7 slightly thicker in order to stabilize the switching operation, the driver transistor Q
3. This is because for Q4, it is desirable to form the gate insulating film 11 thinly in order to ensure high speed performance. 1
2 is a gate electrode made of polycide of the driver transistor formed on the surface of the gate insulating film 11, 12a is a polysilicon film, and 12b is a tungsten silicide film.

In this way, the present static RAM has switching transistors and driver transistors formed on the SOI layer 8 formed by wafer bonding,
Since the gate electrode 6 of the switching transistor is formed on the back surface of the SOI layer 8, and the gate electrode 12 of the driver transistor is formed on the surface of the SOI layer 8, the arrangement of the driver transistors Q3, Q4 and the switching transistors Q1, Q2 is inevitably required. As shown in FIG. 2, the constraint on driver transistors Q3 and Q
4 gate electrode and switching transistors Q1, Q
The distance from the second gate electrode (word line) 6 when viewed from above can be made extremely narrow. Moreover, the contact portion of the gate electrode to the SOI layer 8 includes a contact g that connects the gate electrode of the driver transistor Q3 to the source/drain regions of the switching transistor Q2 and the driver transistor Q4, and a contact g that connects the gate electrode of the driver transistor Q4 and the gate electrode to the switching transistor Q1. , driver transistor Q3
Since only two contacts f are required to connect to the source/drain regions of , the area occupied by the contact portion becomes narrow. From the above, the cell area is actually 20 to 30% more than the conventional one.
It is possible to narrow it down.

Furthermore, the gate electrodes 6 of the driver transistors Q3 and Q4 and the switching transistors Q1 and Q2
a gate electrode 12 is formed on the opposite side of the SOI layer 8,
The driver transistor and the switching transistor have completely different gate insulating films 7 and 11. Therefore,
By setting the film thicknesses of the gate insulating films 7 and 11 separately, the gate insulating films 11 have the optimum thickness for the driver transistors Q3 and Q4, and the optimum film thickness for the switching transistors Q1 and Q2. The gate insulating film 7 can be formed, and the performance of the static RAM can be further improved.

FIGS. 3 to 10 are cross-sectional views showing the method of manufacturing the static RAM shown in FIG. 1 in the order of steps. (1) A semiconductor substrate 13 to be an SOI layer is formed, its surface portion is selectively etched, and an insulating film is buried in the etched portion to form an element isolation insulating film as shown in FIG. (2) Next, a gate insulating film 7 is formed by thermal oxidation,
Gate electrodes 6 (6a, 6b) of switching transistors
) is formed, and then an insulating film 5 is formed as shown in FIG.
to cover the semiconductor substrate 13. (3) Next, a contact hole 5a is formed in the insulating film 5, and then a high resistance load film 4 made of polysilicon is formed as shown in FIG. (4) Next, the surface on the high resistance load film 4 side is covered with an insulating film 3, a polysilicon layer 2 for wafer bonding is further formed, and a semiconductor substrate 13 is attached to another semiconductor on the surface of the polysilicon layer 2. It is attached to the surface of the substrate 1. FIG. 6 shows the state after wafer bonding with the semiconductor substrate 13 facing upward.

(5) Next, the back surface of the semiconductor substrate 13 is polished to form an SOI layer 8 as shown in FIG. The polished surface is the surface of the SOI layer 8, and the opposite surface is the surface of the SOI layer 8.
This is the back surface of the OI layer 8. (6) Next, as shown in FIG.
form 2. (7) Thereafter, as shown in FIG. 9, source/drain regions 10, 10, . . . are formed by ion-implanting n-type impurities while masking the portion that will become the channel of the switching transistor with a resist film 14. Then, when the resist film 14 is removed, a static RAM as shown in FIG. 1 is completed. Thereafter, an interlayer insulating film, contact holes, and electrodes are formed using a normal static RAM manufacturing method.

In this embodiment, a high-resistance load film made of polysilicon is formed as a load element on the back side of the SOI layer 8, but it is not necessary to do so.
It may also be formed on the surface side of the SOI layer 8. However, if it is formed on the back side of the SOI layer 8, the resistance length can be increased and the layout becomes easier.

[0015]

Effects of the Invention In the static RAM of the present invention, at least a switching transistor and a driver transistor are formed on an SOI layer formed by wafer bonding, and the gate electrode of the switching transistor and the gate electrode of the driver transistor are connected to each other in the SOI layer. It is characterized by being formed on the opposite side. Therefore, according to the present static RAM, constraints on the positional relationship between the driver transistor, the switching transistor, and their gate electrodes are weakened, making layout easier, and the distance between the gate electrodes of the driver transistor and the switching transistor viewed from above can be narrowed. becomes possible. Furthermore, the number of contact portions between the SOI layer and the gate electrode of the driver transistor per cell can be reduced. Therefore, the cell area can be reduced and static RA
It is possible to increase the capacity and high integration of M. and,
Since gate insulating films are formed separately for the driver transistor and the switching transistor, the driver transistor and the switching transistor can have different threshold voltages, etc., and can have unique characteristics. can improve the performance of static RAM.

[Brief explanation of the drawing]

FIG. 1 is a sectional view showing one embodiment of a static RAM of the present invention.

FIG. 2 is a plan view showing an example layout of a static RAM as shown in FIG. 1;

[Figure 3] First stage of manufacturing the static RAM shown in Figure 1
It is a sectional view showing the process.

FIG. 4: Second stage of manufacturing the static RAM shown in FIG.
It is a sectional view showing the process.

FIG. 5: Third stage of manufacturing the static RAM shown in FIG.
It is a sectional view showing the process.

FIG. 6: Fourth stage of manufacturing the static RAM shown in FIG.
It is a sectional view showing the process.

FIG. 7: Fifth step of manufacturing the static RAM shown in FIG.
It is a sectional view showing the process.

FIG. 8: Sixth step of manufacturing the static RAM shown in FIG.
It is a sectional view showing the process.

FIG. 9: Seventh step of manufacturing the static RAM shown in FIG.
It is a sectional view showing the process.

FIG. 10 is a sectional view showing a conventional example of a static RAM.

FIG. 11 is a circuit diagram of a static RAM cell (common to the present invention and the conventional example).

[Explanation of symbols]

1 Wafer 6 Gate electrode of switching transistor 7 Gate insulating film of switching transistor 8 SOI layer

Claims (1)

[Claims] 1. At least a switching transistor and a driver transistor are formed in an SOI layer formed by wafer bonding, and a gate electrode of the switching transistor and a gate electrode of the driver transistor are formed on opposite sides of the SOI layer. Static RAM characterized by