KR20020034313A - Method of manufacturing sram cell - Google Patents

Method of manufacturing sram cell Download PDF

Info

Publication number
KR20020034313A
KR20020034313A KR1020000064437A KR20000064437A KR20020034313A KR 20020034313 A KR20020034313 A KR 20020034313A KR 1020000064437 A KR1020000064437 A KR 1020000064437A KR 20000064437 A KR20000064437 A KR 20000064437A KR 20020034313 A KR20020034313 A KR 20020034313A
Authority
KR
South Korea
Prior art keywords
wiring layer
wiring
raemsel
formed
interconnection layer
Prior art date
Application number
KR1020000064437A
Other languages
Korean (ko)
Inventor
김장근
Original Assignee
박종섭
주식회사 하이닉스반도체
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 박종섭, 주식회사 하이닉스반도체 filed Critical 박종섭
Priority to KR1020000064437A priority Critical patent/KR20020034313A/en
Publication of KR20020034313A publication Critical patent/KR20020034313A/en

Links

Images

Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing, power reduction
    • G11C11/417Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing, power reduction for memory cells of the field-effect type
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76895Local interconnects; Local pads, as exemplified by patent document EP0896365
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
    • H01L27/11Static random access memory structures
    • H01L27/1104Static random access memory structures the load element being a MOSFET transistor
    • H01L27/1108Static random access memory structures the load element being a MOSFET transistor the load element being a thin film transistor

Abstract

PURPOSE: A method for fabricating a static random access memory(SRAM) cell is provided to reduce resistance of a cell node contact, by using a gate line of a drive transistor as a pad so that a contact having a low aspect ratio is formed. CONSTITUTION: An active region(21a) having a diagonal symmetrical structure is formed in a semiconductor substrate(21). The first interconnection layer is formed on the active region, disposed lengthwise and having a diagonal symmetrical structure. The second interconnection layer is formed on the first interconnection layer, disposed widthwise and coupling a predetermined portion of the first interconnection layer to the active region. The third interconnection layer using the second interconnection layer as a lower gate is formed on the second interconnection layer. The fourth interconnection layer is formed on the third interconnection layer, disposed widthwise and connected to the active region under the first interconnection layer. The fifth interconnection layer is formed on the fourth interconnection layer, disposed in a direction crossing the fourth interconnection layer.

Description

에스램셀의 제조 방법{METHOD OF MANUFACTURING SRAM CELL} S. raemsel method {METHOD OF MANUFACTURING SRAM CELL} of

본 발명은 반도체소자의 제조 방법에 관한 것으로, 특히 5층 배선(3P-2M)구조의 TFT SRAM(Thin Film Transistor Static Random Access Memory) 셀의 레이아웃 (Layout) 및 그의 제조 방법에 관한 것이다. The present invention relates to that, in particular, five-layer wiring (3P-2M) the structure of the TFT SRAM layout (Layout), and a method of producing a (Thin Film Transistor Static Random Access Memory) cell, a method of manufacturing a semiconductor device.

일반적으로, SRAM의 단위셀은 6개의 트랜지스터(6T)로 구성되는데, 구동트랜지스터(Drive transistor), 엑세스트랜지스터(Access transistor), 부하소자(Load element)로 구성된다. In general, the unit cell of the SRAM is composed of six transistor (6T), it consists of a driving transistor (transistor Drive), the access transistor (Access transistor), a load element (Load element).

여기서, 상기 구동트랜지스터 및 엑세스트랜지스터는 NMOS를 이용하며, 상기 부하소자는 저항, PMOS, FCMOS(Full CMOS), 폴리실리콘부하소자(Polysilicon load) 또는 TFT(Thin Film Transistor)를 이용한다. Here, the driving transistor and the access transistor uses an NMOS, the load element is used in a resistance, PMOS, FCMOS (Full CMOS), polysilicon load devices (Polysilicon load) or TFT (Thin Film Transistor).

최근에는 저전력, 대용량 메모리소자를 구현하기 위해 TFT를 부하소자로 적용하고 있다. Recently, to apply the TFT to the load device in order to implement a low-power, large-capacity memory device.

상기와 같이 구성되는 SRAM의 단위셀에 있어서, 각 트랜지스터의 배치 및 형태는 소자마다 다르며, 특히, 부하소자인 TFT를 배치하기 위한 방법은 게이트의 위치에 따라 하부게이트(Bottom gate) TFT, 탑게이트(Top gate) TFT, 더블게이트 (Double gate) TFT로 다양하게 구분된다. In the unit cell of the SRAM is configured as described above, the arrangement and shape of the respective transistors is different for each element, in particular, the load element is a method for placing the TFT is a bottom gate (Bottom gate) TFT according to the gate position, the top-gate (Top gate) TFT, is separated by a variety of double-gate (double gate) TFT. 또한, 워드라인(Wordline; WL), 정비트라인(BL), 부비트라인(/BL), V CC 라인, V SS 라인을 구성하는 방법에 있어서도 다양한 형태의 셀 형태가 있다. Further, the word lines; a cell in the form of various types even in configuring (Wordline WL), maintenance of Triton (BL), sub bit line (/ BL), V CC line, V SS line.

도 1은 일반적인 TFT SRAM 셀의 등가회로도로서, 부하소자로서 P형 TFT(T1, T2)를 연결하고, 각각 게이트에 워드라인(WL)이 연결되고 드레인에 정비트라인(BL) 또는 부비트라인(/BL)이 연결된 엑세스트랜지스터(Q1, Q2), 상기 TFT(T1, T2)의 일측과 상기 엑세스트랜지스터(Q1, Q2)의 소스단이 공통으로 연결된 정셀노드 및 부셀노드(N1, N2)에 드레인단이 연결되고 상기 드레인단이 게이트에 서로 교차연결된 구동트랜지스터(Q3, Q4)로 구성된다. 1 is an equivalent circuit diagram of a typical TFT SRAM cells, as a load element connecting the type P TFT (T1, T2), each of the word line (WL) connected to the gate is maintained in the drain Tra of (BL) or a sub bit line a (/ BL) are access transistors (Q1, Q2) connected to the TFT (T1, T2) jeongsel node and bushel nodes (N1, N2) connected to one side and the common source terminal of the access transistor (Q1, Q2) of consists of the drain stage is connected to the driving transistor (Q3, Q4) connected to cross each other on the drain stage gate. 그리고, 상기 TFT(T1, T2)의 타측은 전원전압(V CC )이 인가되고, 상기 구동트랜지스터(Q3, Q4)의 소스단에는 접지전원 (V SS )이 인가된다. Then, the other side of the TFT (T1, T2) is applied to the power supply voltage (V CC), a source terminal of the drive transistor (Q3, Q4) is applied to the lower supply voltage (V SS).

도 2는 종래기술에 따른 TFT SRAM의 레이아웃도로서, 종래기술에 따른 TFT SRAM은 셀의 상하부, 좌우 대칭구조를 갖는다. Figure 2 is a TFT SRAM according to a drawing layout of TFT SRAM according to the prior art, the prior art has a top and bottom, left and right symmetric structure of the cell.

도 2a에 도시된 바와 같이, 반도체기판(11)에 소자분리마스크를 이용하여 필드산화막(12)을 형성하여 활성영역(11a)을 정의한 후, 상기 반도체기판(11)상에 제 1 폴리실리콘을 증착하고, 상기 제 1 폴리실리콘을 선택적으로 식각하여 다수의 게이트라인(13)을 형성한다. As shown in Figure 2a, by using the element isolation mask on the semiconductor substrate 11 to form a field oxide film (12), define an active region (11a), a first polysilicon on the semiconductor substrate 11, depositing and selectively etching the first polysilicon to form a plurality of gate lines (13). 이 때, 상기 게이트라인(13)은 엑세스트랜지스터 및 구동트랜지스터의 게이트전극이며, 상기 엑세스트랜지스터의 게이트라인은 워드라인으로 이용된다. Here, the gate line 13 is the gate electrode of the access transistor and driver transistor, the gate line of the access transistor is used as a word line. 계속해서, 상기 게이트라인(13)을 마스크로 이용한 불순물 이온주입으로 소스/드레인(도시 생략)을 형성한다. Subsequently, to form a source / drain (not shown), the gate line 13 in the impurity ion implantation using as a mask.

이어서, 상기 게이트라인(13)을 포함한 전면에 제 1 층간절연막을 형성한 후, 상기 게이트라인(13)과 활성영역(11a)이 동시에 노출되는 정셀노드/부셀노드 콘택홀을 형성한다. Then, a first after forming the interlayer insulating film, jeongsel node / bushel node contact hole and the gate line 13 and the active region (11a) is exposed at the same time in the front, including the gate line 13. 이상 버팅콘택(Butting)이라 한다. Or more is referred to as inverting the contact (Butting).

이어서, 상기 정셀노드/부셀노드 콘택홀을 포함한 전면에 제 2 폴리실리콘을 증착한 후, 상기 제 2 폴리실리콘을 선택적으로 패터닝하여 엑세스트랜지스터와 구동트랜지스터의 접합부분에 접속되어 상기 엑세스트랜지스터의 드레인에 접속된 비트라인으로부터 전송된 전하를 저장하는 정셀노드콘택/부셀노드콘택(14)을 형성한다. Then is connected to the junction portion of the jeongsel node / bushel depositing a second polysilicon on the front, including the node contact holes, the access is selectively patterned in the second polysilicon transistor and a driving transistor to the drain of the access transistor storing the charge transferred from the bit line connected to the contact node jeongsel / bushel to form a node contact (14).

이어서, 상기 정셀노드콘택/부셀노드콘택(14)을 포함한 전면에 제 2 층간절연막(도시 생략)을 형성한 후, 상기 제 2 층간절연막을 선택적으로 패터닝하여 V SS 라인을 형성하기 위한 콘택홀을 형성하고, 상기 콘택홀상에 제 3 폴리실리콘을 형성한다. Then, the second after the formation of an interlayer insulating film (not shown), wherein the contact hole for forming the V SS line and selectively patterning the second interlayer insulating film on the front, including the jeongsel node contacts / bushel node contact (14) formed, and forming a third polysilicon on the contact holsang. 계속해서 상기 제 3 폴리실리콘을 선택적으로 패터닝하여 상기 활성영역(11a)에 접속되는 V SS 콘택(15a) 및 V SS 라인(15b)을 형성한다. Subsequently it is selectively patterned in the third polysilicon to form a V SS contact (15a) and the V SS line (15b) connected to the active region (11a).

계속해서, TFT의 게이트전극에 접속되는 콘택홀을 형성하고, 상기 콘택홀을 포함한 전면에 제 4 폴리실리콘을 형성한 후, 상기 제 4 폴리실리콘을 선택적으로 패터닝하여 TFT의 게이트전극(16)을 형성한 후, 상기 TFT의 게이트전극(16)상에 제3 층간절연막, 즉, TFT의 게이트산화막을 형성한다. Subsequently, after forming a contact hole connected to the gate electrode of the TFT, and to form a fourth polysilicon in the front, including the contact hole, the gate electrode 16 of the TFT it is selectively patterned in the fourth polysilicon after the formation, to form a third gate oxide film of the interlayer insulating film, that is, on the TFT gate electrode 16 of the TFT.

도 2b에 도시된 바와 같이, 상기 TFT의 게이트산화막상에 TFT의 활성층을 위한 제 5 폴리실리콘을 증착한 후, 상기 제 5 폴리실리콘을 선택적으로 패터닝하여 TFT의 채널 및 소스/드레인(17)을 형성한다. As shown in Figure 2b, the fifth depositing a poly-silicon for the active layer of the TFT to the gate oxide film of the TFT, a channel and a source / drain 17 of the TFT is selectively patterned in the fifth polysilicon forms. 상기 TFT의 소스/드레인(17) 형성시, V CC 라인(18)이 동시에 형성된다. , V CC line 18, a source / drain 17 is formed in the TFT is formed at the same time.

도 2c에 도시된 바와 같이, 상기 활성영역(11a)을 노출시키는 콘택홀을 형성한 후, 상기 콘택홀에 접속되는 정비트라인(19a) 및 부비트라인(19b)을 형성한다. As it is shown in Figure 2c, after forming a contact hole exposing the active region (11a), to form a maintenance Tra of (19a) and the sub-bit line (19b) connected to the contact holes.

그러나, 상기한 종래기술에서는 6개의 배선층(5P-1M)이며, 마스크 공정의 오정렬로 인해 셀이 비대칭으로 형성되는 문제점이 있다. However, in the prior art and six wiring (5P-1M), there is a problem in that due to the misalignment of the mask process cells are formed asymmetrically. 그리고, V SS 콘택 및 V SS 라인으로서 폴리실리콘을 이용하므로 V SS 콘택저항이 높고 비트라인 콘택저항이 높음에 따라 저 V CC 특성 및 SER(Soft Error Rate) 특성이 저하되는 문제점이 있고, 또한 셀 구성을 위한 공정이 복잡하여 생산성 및 원가절감에 불리한 단점이 있다. Then, using the polysilicon as the V SS contact and the V SS line, so there is a problem that the low V CC characteristics and SER (Soft Error Rate) characteristic in accordance with the V SS contact resistance is high bit line contact resistance is high degradation, and cell the process is complex, there is a disadvantage for the construction disadvantages in productivity and cost savings.

본 발명은 상기 종래기술의 문제점을 해결하기 위해 안출한 것으로서, 마스크공정의 오정렬에 의한 셀의 비대칭효과(Asymmetry effect)를 방지하고 데이터의 저장부인 셀노드의 콘택저항을 감소시키는데 적합한 SRAM 셀의 제조 방법을 제공함에 그 목적이 있다. The present invention is made in the right SRAM cell sikineunde as one made in view to solve the problems of the prior art, it prevents asymmetric effect (Asymmetry effect) of the cell according to the misalignment of the mask process, and reduce the contact resistance of the storage deny cell node data to provide a method it is an object.

도 1은 일반적인 SRAM 셀의 등가회로도, 1 is an equivalent circuit diagram of a typical SRAM cell,

도 2a 내지 도 2c는 종래기술에 따른 SRAM 셀의 제조 방법을 도시한 레이아웃도, Figure 2a to 2c are a layout showing a method of manufacturing the SRAM cell according to the prior art,

도 3a 내지 도 3f는 본 발명의 실시예에 따른 SRAM 셀의 제조 방법을 도시한 레이아웃도, A layout showing a method of manufacturing the SRAM cell according to an embodiment of the present invention, Figures 3a-3f,

도 4는 도 3f의 A-A'선에 따른 SRAM 셀의 구조 단면도, 4 is a structural cross-sectional view of the SRAM cell according to the line A-A 'in Fig. 3f,

도 5는 도 3f의 B-B'선에 따른 SRAM 셀의 구조 단면도. 5 is a structural cross-sectional view of the SRAM cell according to the line B-B 'of FIG 3f.

*도면의 주요 부분에 대한 부호의 설명 * Description of the Related Art

21a : 활성영역 21b : 필드영역 21a: active area 21b: field region

22a, 22b, 22c, 22d : 게이트라인 23a : 정셀노드콘택 22a, 22b, 22c, 22d: Gate line 23a: jeongsel node contact

23b : 부셀노드콘택 24a : TFT의 채널 23b: the channel of the TFT: bushel node contact 24a

24b : TFT의 소스/드레인 24c : V CC 라인 24b: the source of the TFT / drain 24c: V CC line

25a : V SS 콘택 25b : V SS 라인 25a: V SS contact 25b: V SS line

26a : 정비트라인 26b : 부비트라인 26a: maintenance of Tra 26b: sub bit line

100 : 제 1 배선층 200 : 제 2 배선층 100: first wiring layer 200: second wiring layer

300 : 제 3 배선층 400 : 제 4 배선층 300: third wiring layer 400: fourth wiring

500 : 제 5 배선층 500: a fifth wiring layer

상기의 목적을 달성하기 위한 본 발명의 SRAM 셀의 제조 방법은 엑세스 트랜지스터, 구동 트랜지스터 및 하부게이트구조의 박막트랜지스터를 구비하는 에스램셀의 제조 방법에 있어서, 반도체기판에 대각선 대칭구조를 갖는 활성영역을 형성하는 단계; Production process of the SRAM cell of the present invention for achieving the above object is the method of manufacturing a S. raemsel having an access transistor, a drive transistor, and a bottom gate structure thin film transistor of a semiconductor substrate an active region having a diagonal line symmetry forming; 상기 활성영역상에 횡방향으로 배선되며 대각선 대칭구조를 갖는 제 1 배선층을 형성하는 단계; And the step of the wiring on the active region in the lateral direction to form a first wiring layer having a diagonal symmetry; 상기 제 1 배선층상에 종방향으로 배선되며 상기 제 1 배선층의 소정부분과 상기 활성영역을 교차결합시키는 제 2 배선층을 형성하는 단계; And the step of the wiring in the longitudinal direction of the first wiring layer, forming a second wiring layer to cross-link the predetermined section and the active region of the first wiring layer; 상기 제 2 배선층상에 상기 제 2 배선층을 하부게이트로 이용하는 제 3 배선층을 형성하는 단계; Forming a third wiring layer using the second wiring layer in the second wiring layer, a bottom gate; 상기 제 3 배선층상에 횡방향으로 배선되며 상기 제 1 배선층 하부의 상기 활성영역에 접속되는 제 4 배선층을 형성하는 단계; Wherein said third wiring is in the horizontal direction to the wiring layer to form a fourth wiring layer is connected to the active region of the first wiring layer bottom; 및 상기 제 4 배선층상에 상기 제 4 배선층과 교차하는 방향으로 배선되는 제 5 배선층을 형성하는 단계를 포함하여 이루어짐을 특징으로 한다. And characterized by yirueojim including the step of forming the fifth wiring layer to be wired in a direction crossing the fourth wiring in the fourth wiring layer.

이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부 도면을 참조하여 설명하기로 한다. Hereinafter to be described in detail enough to easily carry out self technical features of the present invention one of ordinary skill in the art, with reference to the accompanying drawings, the preferred embodiment of the present invention will be described .

본 발명의 실시예에서 SRAM의 단위셀은 통상과 동일하게 도 1에 도시된 등가회로로 구성되는데, NMOS의 구동트랜지스터(Q1,Q4) 및 엑세스트랜지스터(Q2, Q3), 하부게이트구조의 P형 TFT의 부하트랜지스터로 구성된 6T(6 Transistor) 구조를 갖는다. There is a unit cell of the SRAM in the embodiment of the present invention is composed of the equivalent circuit shown in Figure 1 generally in the same, the NMOS driver transistor (Q1, Q4) and the access transistors (Q2, Q3), P type bottom gate structure It has a 6T (6 transistor) structure composed of a TFT load transistors.

도 3a 내지 도 3f는 본 발명의 실시예에 따른 SRAM 셀의 제조 방법을 도시한레이아웃도로서, 단위셀을 구성하는 구동트랜지스터, 엑세스트랜지스터, 풀업트랜지스터인 TFT의 레이아웃 형태 및 각각의 배선층을 연결시키기 위한 콘택 레이아웃을 도시하고 있다. Figures 3a to 3f are to connect the layout type and each of the wiring layer of the driving transistor, the access transistor, the pull-up transistor TFT constituting a unit cell as a layout showing a method of manufacturing the SRAM cell according to an embodiment of the present invention It shows the layout for the contact.

도 3a에 도시된 바와 같이, 소자분리마스크를 이용하여 단위셀이 형성될 반도체기판(21)상에서 전기적으로 활성화되어야 할 활성영역(21a)과 비활성화되는 필드영역(21b)을 형성한다. As it is shown in Figure 3a, by using a device isolation mask to form an active region (21a) and which disable field region (21b) to be electrically activated on the semiconductor substrate 21 is formed in the unit cell. 이 때, SRAM 단위셀의 활성영역(21a)은 대각선 방향의 대칭 구조이고, 중심부에 후속 V SS 콘택이 형성될 영역(21c)을 포함하며 단위셀의 상단과 하단에 각각 1/2개씩의 정비트라인패드 및 부비트라인패드가 형성될 영역을 포함한다. At this time, the active region (21a) of the SRAM unit cell is symmetrical in a diagonal direction, and includes a region (21c) become V SS subsequent contact formation in the heart and maintenance of the respective half each on the top and bottom of the unit cell It includes Tra pads and sub bit line region to be the pad is formed. 아울러, 후속 셀노드콘택이 형성될 영역도 포함한다. In addition, also it comprises a zone a subsequent node cell contact formation.

이어서, 상기 활성영역(21a)상에 폴리실리콘(P1), 실리콘, 살리사이드 또는 메탈 중 어느 하나를 형성한 후, 선택적으로 패터닝하여 상기 반도체기판(21)의 활성영역(21a)을 가로지르는 방향 즉, 횡방향으로 엑세스트랜지스터의 게이트라인 (22a, 22b)과 구동트랜지스터의 게이트라인(22c, 22d)을 형성한다. Then, after forming any one of the over the active region (21a) of polysilicon (P1), silicon, salicide or metal, a direction that runs by selectively patterned to cross the active region (21a) of the semiconductor substrate 21, That is, a gate line of access transistor in a transverse direction (22a, 22b) and a gate line of the driving transistor (22c, 22d). 이 때, 상기 구동트랜지스터의 게이트라인(22c, 22d)은 후속 V SS 콘택이 형성될 영역(21c)을 중심으로 상하부에 횡방향으로 대칭구조를 갖고 인접셀(도시 생략)과 서로 고립되어 배치되며, 후속 셀노드콘택을 형성하기 위한 패드 역할을 한다. At this time, the gate lines (22c, 22d) of the driving transistor is arranged subsequent V SS contacts are isolated from each other and adjacent has a symmetrical structure in the horizontal direction in upper and lower portions around the region (21c) is formed in the cell (not shown) and the pads act to form a subsequent cell node contacts. 이처럼 구동트랜지스터의 게이트라인(22c, 22d)을 후속 셀노드콘택 형성을 위한 패드로 이용하는 이유는 게이트라인과 소스/드레인이 동시에 오픈되는 버팅콘택(Butting contact)을 사용하지 않기 때문이다. The reason of using the pad for subsequent cell node contact forming the gate line of the driving transistor (22c, 22d) is that they do not use the gate lines and the source / drain contact inverting (Butting contact) which is open at the same time. 이처럼, 버팅콘택을 이용하지 않으면 종횡비(Aspect ratio)가 작은 콘택을 형성할 수 있다. Thus, if you are not using the butting contact aspect ratio (Aspect ratio) that can form a small contact.

그리고, 상기 엑세스트랜지스터의 게이트라인(22a, 22b)은 상기 구동트랜지스터의 게이트라인(22c, 22d)에 소정간격 이격되어 서로 대칭구조를 갖고 측방으로 인접하는 셀의 엑세스트랜지스터의 게이트라인과 연결되며 워드라인으로 이용된다. And, the access gate line of the transistor (22a, 22b) is connected to the gate line of access transistor of the cell adjacent to the side has been a predetermined distance spaced apart symmetrically with each other in the gate line (22c, 22d) of the driving transistor word It is used as a line.

여기서, 상기 구동트랜지스터의 게이트라인(22c, 22d)과 엑세스트랜지스터의 게이트라인(22a, 22b)은 제 1 폴리실리콘 레벨(Polysilicon level; P1)로서 제 1 배선층(100)이라 하며, 단위셀의 대각선방향으로 서로 대칭된다. Here, the gate line of the driving transistor (22c, 22d) and a gate line of access transistor (22a, 22b) includes a first polysilicon level (Polysilicon level; P1) as referred to as a first wiring layer 100, a diagonal of the unit cell It is symmetrical with each other in the direction.

도면에 도시되지 않았지만, 후속 공정으로 상기 제 1 배선층(100)을 마스크로 이용한 불순물 이온주입으로 상기 활성영역(21a)에 각 트랜지스터의 소스/드레인을 형성한다. Although not shown in the figure, the first wiring layer 100 in a subsequent step by impurity ion implantation using as a mask to form a source / drain of each transistor in the active region (21a).

도 3b에 도시된 바와 같이, 상기 게이트라인(22a, 22b, 22c, 22d)을 포함한 전면에 제 1 층간절연막(도시 생략)을 형성한 후, 상기 제 1 층간절연막을 선택적으로 패터닝하여 후속 정셀노드콘택(NC) 및 부셀노드콘택(/NC)을 위한 콘택홀을 형성하는데, 이 때, 상기 콘택홀 형성으로 인해 구동트랜지스터의 게이트라인(22c, 22d)과 활성영역(21a)의 소정부분이 노출된다. A, the gate lines (22a, 22b, 22c, 22d) after the front formation of the first interlayer insulating film (not shown), and subsequently selectively patterned in the first interlayer insulating film jeongsel including as a node shown in Figure 3b contact (NC) and bushels node contact (/ NC) for, in forming a contact hole for this time, the gate lines (22c, 22d) and the exposed predetermined portion of the active region (21a) of the driving transistor due to the formation of the contact hole do. 또한, 상기 활성영역(21a)의 정비트라인패드 및 부비트라인패드가 형성될 부분도 식각하여 콘택홀을 형성한다. In addition, the maintenance is also etched trad the pad portion and the portion to be the bit line pad is formed in the active region (21a) to form a contact hole.

이어서, 상기 콘택홀을 포함한 전면에 폴리실리콘을 형성한 후, 상기 폴리실리콘을 선택적으로 패터닝하여, 상기 구동트랜지스터의 게이트라인(22c, 22d)과 활성영역(21a)을 교차접속시키는 정셀노드콘택(23a) 및 부셀노드콘택(23b)을 형성하고 동시에 상기 활성영역(21a)에 접속되는 정비트라인패드(23c), 부비트라인패드(23d)를 형성한다. Then, after forming the polysilicon on the front, including the contact holes, contact jeongsel node which is selectively patterned in the polysilicon, cross-connecting the gate lines (22c, 22d) and the active region (21a) of the driving transistor ( 23a) and bushels form a node contact (23b) and at the same time forms a maintenance trad pads (23c), sub bit line pad (23d) which is connected to the active region (21a).

상기와 같은 정셀노드콘택(23a), 부셀노드콘택(23b), 정비트라인패드(23c) 및 부비트라인패드(23d)를 포함하여 제 2 배선층(200)이라 하며, 상기 제 2 배선층(200)은 후속 부하트랜지스터인 P형 TFT의 게이트로 이용되고 제 2 폴리실리콘 레벨(P2)이다. Said second wiring layer (200 as jeongsel node contact (23a), bushel node contact (23b), maintenance trad the pad (23c) and the sub-bit line pad (23d), the second wiring layer 200, including as described above, and ) it is used as a gate of a P-type TFT subsequent load transistor and the second polysilicon level (P2).

도 3c에 도시된 바와 같이, 상기 제 2 배선층(200)을 포함한 전면에 제 2 층간절연막을 형성한 후, 선택적으로 패터닝하여 하부의 구동트랜지스터의 게이트라인(22c, 22d)에 접속된 정셀노드콘택(23a)과 부셀노드콘택(23b)을 노출시키는 콘택홀을 형성하고, 상기 콘택홀을 포함한 전면에 폴리실리콘을 형성한 후, 선택적으로 패터닝하여 상기 콘택홀을 통해 상기 정셀노드콘택(23a)과 부셀노드콘택(23b)에 접속되는 제 3 배선층(300)을 형성한다. As shown in Figure 3c, wherein after forming the second interlayer insulating film on the front containing the second wiring layer 200, the selective patterning to the jeongsel node contact connected to the gate line of the lower driver transistors (22c, 22d) to (23a) and bushels node contact (23b) contacts after the formation of the hole, forming a polysilicon on the front, including the contact holes, and optionally the jeongsel node contact (23a) via the contact holes and patterned to expose the and to form a third wiring layer 300 connected to the node bushel contact (23b). 여기서, 도면부호 24d는 제 2 배선층(200)과 제 3 배선층(300)을 연결시키는 콘택을 나타낸다. Here, reference numeral 24d denotes a contact for connecting the second wiring layer 200 and the third wiring layer 300.

이 때, 상기 제 3 배선층(300)은 제 3 폴리실리콘 레벨(P3)로서, 상기 제 2 배선층(200)을 하부 게이트로 하는 TFT의 채널(24a) 및 소스/드레인(24b)을 포함하고, 상기 TFT에 전원을 공급하며 횡방향으로 인접셀과 접속되는 V CC 라인(24c)을 포함한다. At this time, the third wiring layer 300 and a third polysilicon level as (P3), the channel (24a) and source / drain (24b) of the TFT to the second wiring layer 200 to the bottom gate, supplying power to the TFT and includes a V CC line (24c) to be connected to neighboring cells in the horizontal direction.

상기와 같은 제 3 배선층(300)은 V CC 라인(24c)에서 TFT의 채널(24a)을 거쳐 구동트랜지스터의 게이트라인(22c, 22d)에 접속된 정셀노드콘택(23a) 및 부셀노드콘택(23b) 즉, TFT의 게이트전극으로 연결되며, 또한 채널(24a)에서 90°꺽이면서LDO(Lightly Drain Offset) 영역 또는 소스/드레인영역(24b)으로 이어지므로 채널길이(Channel length)를 최대화시킬 수 있다. Wherein the third wiring layer 300, a gate line of the driving transistor through the channel (24a) of the TFT at the V CC line (24c) (22c, 22d) of jeongsel node contact (23a) and a bushel node contact (23b connected to the same ), that is, is connected to the gate electrode of the TFT, also while 90 ° bent at the channel (24a) so followed by LDO (Lightly drain Offset) region or source / drain region (24b) it is possible to maximize the channel length (channel length) . 즉, 소자의 스링크(Shrink)시 셀크기 감소와 TFT 크기 감소로 인해 발생할 수 있는 TFT의 특성 퇴화를 방지하기 위해 TFT의 채널(24a)과 소스/드레인영역(24b)을 연결하는 형태를 굴곡시키므로서 채널길이를 크게 한다. That is, the switch link (Shrink) when bent in the form of connection channels (24a) and the source / drain regions (24b) of the TFT to prevent the characteristics of the TFT degradation that may be caused by the cell size decreases and the TFT size reduction of the device standing largely because the channel length.

도 3d에 도시된 바와 같이, 상기 제 3 배선층(300)을 포함한 전면에 제 3 층간절연막을 형성한 후, 상기 제 1, 2, 3 층간절연막을 동시에 식각하여 활성영역 (21a)의 V SS 콘택이 형성될 부분(21c)을 노출시키는 콘택홀을 형성한다. As shown in Figure 3d, wherein after forming the third interlayer insulating film on the front, including the third wiring layer 300, wherein the 1, 2, 3 V SS contact of the interlayer insulating film and at the same time, etching the active region (21a) a portion (21c) is to be formed to form a contact hole for exposing. 이어서, 상기 콘택홀을 포함한 전면에 금속을 증착한 후, 선택적으로 패터닝하여 V SS 콘택(25a) 및 V SS 라인(25b)을 포함하는 제 4 배선층(400)을 형성한다. Then, to form a fourth wiring layer 400 including a depositing a metal on the front, including the contact hole, is selectively patterned with a V SS contact (25a) and the V SS line (25b). 이 때, 상기 제 4 배선층(400)은 제 1 메탈 레벨(Metal level; M1)이라 하며, V SS 콘택(25a)에 오버랩되고 단위셀의 횡방향으로 배선되어 측방의 인접셀의 V SS 콘택과 연결된다. At this time, the fourth wiring 400, a first metal level (Metal level; M1) referred to, and, V SS contact overlap in (25a) are wired in the horizontal direction of the unit cells V SS contact of the side neighboring cell and It is connected.

여기서, 제 4 배선층(400)의 배치공간은 충분하여 여분의 배선라인(25b,25c)을 추가할 수 있는데 이들 라인 중 하나(25b)는 제 1 배선층(100)의 워드라인 즉, 구동트랜지스터의 게이트라인(22c, 22d)을 스트랩핑(Stapping)하는 역할을 하고 나머지 하나(25c)는 글로발 워드라인(Global wordline)으로 사용할 수 있다. Here, the setting space of the fourth wiring layer 400 may be sufficient to add the redundant wiring line (25b, 25c) there of the word line that is, the drive transistor of one of these lines (25b) has a first wiring layer (100) serves to ping the gate lines (22c, 22d) strap (Stapping) and the other (25c) may be used in the Global word lines (Global wordline).

그리고, 상기 제 4 배선층(400)은 텅스텐 와이어링(W wiring) 공정 또는 텅스텐 플러깅(W pluging) 공정을 사용할 수 있는데 공정수를 감소시키기 위해서는 텅스텐 와이어링 공정을 사용함이 바람직하다. In addition, the fourth wiring 400, it is preferred to use a tungsten wiring process in order to reduce the number of steps may be used tungsten wiring (wiring W) or tungsten plugging process (W pluging) process.

도 3e에 도시된 바와 같이, 상기 제 4 배선층(400)을 포함한 전면에 제 4 층간절연막을 형성한 후, 상기 제 2,3,4 층간절연막을 선택적으로 동시에 식각하여 활성영역(21a)에 접속된 제 2 배선층(200)의 정비트라인패드(23c) 및 부비트라인패드(23d)를 노출시키는 콘택홀을 형성한다. Connected to a, the fourth wiring 400, the fourth front after forming the interlayer insulating film, an active region (21a) at the same time by selectively etching the interlayer insulating film on the first 2, 3, 4, including, as shown in Figure 3e the first to form a contact hole for exposing the maintenance trad the pad (23c) and the sub-bit line pad (23d) of the second wiring layer (200).

이어서, 상기 콘택홀을 포함한 전면에 금속을 형성한 후, 상기 금속을 선택적으로 패터닝하여 상기 정비트라인패드(23c) 및 부비트라인패드(23d)에 접속되며 소정간격 거리를 갖는 정비트라인(26a) 및 부비트라인(26b)을 포함하는 제 5 배선층(500)을 형성하는데, 이 때, 상기 제 5 배선층(500)은 상기 단위셀의 종방향으로 배선된다. Which then, after forming the metal on the front, including the contact hole, is selectively patterned in the metal it is connected to the pad (23c) and the sub-bit line pad (23d) the maintenance trad maintenance trad with a predetermined gap distance ( 26a) and a portion for forming the fifth wiring layer 500 including a bit line (26b), at this time, the fifth wiring 500 is wired in a longitudinal direction of the unit cells. 여기서, 상기 제 5 배선층(500)은 제 2 메탈레벨(M2)이라 한다. Here, the fifth wiring 500 is referred to as a second metal level (M2).

도 3f에 도시된 바와 같이, 본 발명의 실시예에서는 5층의 배선구조 즉, 3 폴리실리콘(P3)-2 메탈(M2)의 배선층 구조를 이용하므로써 셀구성 요소를 포함하면서 최소의 배선층을 사용하여 셀 및 전체 다이를 구성하도록 한다. As it is shown in Figure 3f, the wiring structure of the fifth floor in the exemplary embodiment of the present invention That is, the three polysilicon (P3) using a minimum of wiring layers and a cell component By using the wiring layer structure -2-metal (M2) It will be to configure the cell and the entire die. 즉, 5층의 배선구조 중 제 1,2,3 배선층(100, 200, 300)은 폴리실리콘레벨(P1, P2, P3)이고, 제 4, 5 배선층(400, 500)은 금속레벨(M1, M2)이며, V SS 콘택(25a) 및 V SS 라인(25b)을 포함하는 제 4 배선층(400)을 통상과 달리 금속레벨로 한다. That is, the first, second and third wiring layers 100, 200 and 300 of the wiring structure of the five-layer polysilicon level (P1, P2, P3), and the fourth and fifth wiring layers 400 and 500 are metal level (M1 , M2), and to the fourth wiring layer 400 including the V SS contact (25a) and the V SS line (25b) of a metal level, unlike the conventional.

도 4는 도 3f의 A-A'선에 따른 에스램셀의 단면도로서, 반도체기판(21)에 소자분리공정을 이용하여 필드영역(21b)이 형성되고, 필드영역상(21)상에 제 1 배선층(100)의 게이트라인(22d)이 형성되며, 게이트라인(22d)상에 제 2 배선층(200)으로서 셀노드콘택(23a)/부셀노드콘택(23b)이 형성된다. Figure 4 is a cross-sectional view of S. raemsel along the line A-A 'of 3f, using a device separation process, a semiconductor substrate 21, field region (21b) is formed, the first on the field region the 21 a gate line (22d) of the wiring layer 100 is formed, a gate line (22d) to the cell node contact (23a) / bushel node contact (23b) into a second wiring layer 200 a is formed. 그리고, 셀노드콘택(23a)/부셀노드콘택(23b)상에 제 3 배선층(300)으로서 TFT의 채널을 포함하는 소스/드레인영역(24d)이 형성되며, 반도체기판(21)의 소스/드레인(도시 생략)에 제 4 배선층(400)으로서 V SS 콘택(25a) 및 V SS 라인(25b)이 접속된다. Then, the cell node contact (23a) / bushel node contact (23b) to the third wiring layer 300, a source / drain region (24d) comprising a channel of a TFT is formed in the source / drain of the semiconductor substrate 21, V SS is a contact (25a) and the V SS line (25b) is connected to a fourth wiring layer 400 (not shown).

마지막으로, V SS 라인(25b)상부에 소정간격을 두고 제 5 배선층(500)으로서 정비트라인(26a)/부비트라인(26b)이 형성된다. Finally, V SS line (25b) the maintenance of Triton (26a) / sub bit line (26b) at a predetermined interval in the upper portion as a fifth wiring layer 500 is formed.

여기서, 미설명 도면부호 27a 내지 27d는 층간절연막을 나타낸다. Here, non-described reference numerals 27a to 27d denotes an interlayer insulating film.

도 5는 도 3f의 B-B'선에 따른 에스램셀의 구조 단면도로서, 필드영역(21b)이 형성된 반도체기판(21)상에 제 1 배선층(100)으로서 구동트랜지스터 및 엑세스트랜지스터의 게이트라인(22a,22b,22c,22d)이 형성되며, 상기 제 1 배선층(100)상에 제 2 배선층(200)으로서 구동트랜지스터의 게이트라인(22b)과 활성영역(21a)을 교차접속시키는 부셀노드콘택(23b)이 형성된다. 5 is a structural cross-sectional view of S. raemsel according to line B-B 'of FIG 3f, the field region (21b) is formed in the semiconductor substrate 21, a first gate line of the driving transistor and an access transistor as the wiring layer 100 on the ( 22a, 22b, 22c, 22d) is formed, bushel node contact of the second wiring layer 200 is cross connected to a gate line (22b) and an active region (21a) of the driving transistor as on the first wiring layer 100 ( this 23b) is formed. 그리고, 활성영역(21a)의 일측에 부비트라인패드(23c)이 접속되며, 부셀노드콘택(23b)상에 제 3 배선층(300)으로서 TFT의 소스/드레인(24a) 및 채널(24b), V CC 라인(24c)이 형성된다. And, and part at one side of the active region (21a), a bit line pad (23c) is connected to the source / drain (24a) and the channel of the TFT as a third wiring layer 300 on the bushel node contact (23b), (24b), the V CC line (24c) is formed.

그리고, 제 3 배선층(300)상에 제 4 배선층(400)으로서 V SS 라인(25b), 글로발 워드라인과 워드라인 스트랩핑으로 이용되는 여분의 라인(25c, 25d)이 형성되며 제 4 배선층(400)상에 제 5 배선층(500)으로서 부비트라인(26b)이 부비트라인패드 (23c)에 접속된다. Then, the third wiring layer 300, a fourth wiring 400 to the V SS line (25b), an extra line is used as a ping Global word lines and word line straps (25c, 25d) is formed the fourth wiring layer ( 400) sub bit line (26b as the fifth wiring 500 to the top) is connected to the sub bit line pad (23c).

본 발명의 기술 사상은 상기 바람직한 실시예에 따라 구체적으로 기술되었으나, 상기한 실시예는 그 설명을 위한 것이며 그 제한을 위한 것이 아님을 주의하여야 한다. Although the teachings of the present invention is specifically described in accordance with the preferred embodiment, the above-described embodiment is for a description thereof should be noted that not for the limitation. 또한, 본 발명의 기술 분야의 통상의 전문가라면 본 발명의 기술 사상의범위 내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다. In addition, if an ordinary specialist in the art of the present invention will be understood by example various embodiments are possible within the scope of the technical idea of ​​the present invention.

상술한 바와 같은 본 발명의 에스램셀의 제조 방법은 셀노드콘택 형성시 버팅콘택을 이용하지 않고 구동트랜지스터의 게이트라인을 패드로 이용하여 종횡비(Aspect ratio)가 작은 콘택을 형성하므로써, 셀노드콘택의 저항을 감소시킬 수 있는 효과가 있다. By the S preparation of raemsel of the invention is to form a small contact the aspect ratio (Aspect ratio) by using a gate line of the driving transistor without using a butting contact in forming the contact cell node to the pad as described above, the cell node contact It has the effect of reducing the resistance.

그리고, 금속을 이용하여 V SS 콘택 및 V SS 라인을 구성하므로써 V SS 콘택의 저항을 감소시킬 수 있으며, 하부의 셀노드콘택을 포함하는 제 2 배선층을 TFT의 게이트전극으로 이용하므로써 공정에 소용되는 배선층의 수를 감소시켜 소자의 집적도를 향상시킬 수 있는 효과가 있다. Then, using a metal V SS contact and a V SS By configuring the line V SS can reduce the resistance of the contact, which use a second wiring layer including a cell node contacts the lower the process By using the gate electrode of the TFT reduce the number of wiring layers to the effect to improve the integration degree of the device.

Claims (9)

  1. 엑세스 트랜지스터, 구동 트랜지스터 및 하부게이트구조의 박막트랜지스터를 구비하는 에스램셀의 제조 방법에 있어서, In the method of S. raemsel having an access transistor, a drive transistor, and a bottom gate structure thin film transistor of,
    반도체기판에 대각선 대칭구조를 갖는 활성영역을 형성하는 단계; Forming an active region having a diagonal symmetrical structure in a semiconductor substrate;
    상기 활성영역상에 횡방향으로 배선되며 대각선 대칭구조를 갖는 제 1 배선층을 형성하는 단계; And the step of the wiring on the active region in the lateral direction to form a first wiring layer having a diagonal symmetry;
    상기 제 1 배선층상에 종방향으로 배선되며 상기 제 1 배선층의 소정부분과 상기 활성영역을 교차결합시키는 제 2 배선층을 형성하는 단계; And the step of the wiring in the longitudinal direction of the first wiring layer, forming a second wiring layer to cross-link the predetermined section and the active region of the first wiring layer;
    상기 제 2 배선층상에 상기 제 2 배선층을 하부게이트로 이용하는 제 3 배선층을 형성하는 단계; Forming a third wiring layer using the second wiring layer in the second wiring layer, a bottom gate;
    상기 제 3 배선층상에 횡방향으로 배선되며 상기 제 1 배선층 하부의 상기 활성영역에 접속되는 제 4 배선층을 형성하는 단계; Wherein said third wiring is in the horizontal direction to the wiring layer to form a fourth wiring layer is connected to the active region of the first wiring layer bottom; And
    상기 제 4 배선층상에 상기 제 4 배선층과 교차하는 방향으로 배선되는 제 5 배선층을 형성하는 단계 Wherein the step of forming the fifth wiring layer to be wired in a direction that crosses the fourth wiring layers 4 on the wiring layer,
    를 포함하여 이루어짐을 특징으로 하는 에스램셀의 제조 방법. And S. The method of raemsel characterized by including yirueojim.
  2. 제 1 항에 있어서, According to claim 1,
    상기 제 1 배선층은 상기 구동트랜지스터와 엑세스트랜지스터의 게이트라인을 포함하며, 폴리실리콘, 살리사이드 또는 금속 중 어느 하나를 이용하여 형성되는 것을 특징으로 하는 에스램셀의 제조 방법. The first wiring layer process for producing a S. raemsel, characterized in that formed using any one of a and a gate line of the driving transistor and the access transistor, polysilicon, or a metal salicide.
  3. 제 1 항에 있어서, According to claim 1,
    상기 제 2 배선층은 정셀노드/부셀노드, 정비트라인패드/부비트라인패드를 포함하며, 폴리실리콘을 이용하여 형성되는 것을 특징으로 하는 에스램셀의 제조 방법. The second wiring layer process for producing a S. raemsel characterized in that the node comprises a jeongsel / bushel node, maintenance trad the pad / sub bit line pad, formed of a polysilicon.
  4. 제 1 항에 있어서, According to claim 1,
    상기 제 3 배선층은 상기 박막트랜지스터의 활성층, 채널 및 소스/드레인을 포함하고, V CC 라인을 더 포함하는 것을 특징으로 하는 에스램셀의 제조 방법. The third wiring layer process for producing a S. raemsel according to claim 1, further including an active layer, channel and source / a drain, and V CC line of the thin film transistor.
  5. 제 4 항에 있어서, 5. The method of claim 4,
    상기 박막트랜지스터의 채널과 소스/드레인은 굴곡진 형태로 연결되는 것을 특징으로 하는 에스램셀의 제조 방법. Channel and the source / drain of the thin film transistor manufacturing method of S. raemsel characterized in that the connection to the curved form.
  6. 제 1 항에 있어서, According to claim 1,
    상기 제 4 배선층은 V SS 라인, 글로발워드라인 및 워드라인스트랩핑을 포함하며, 금속을 이용하여 형성되는 것을 특징으로 하는 에스램셀의 제조 방법. The fourth wiring layer process for producing a S. raemsel, characterized in that formed using a metal, comprises a V SS line, Global word lines and word line straps ping.
  7. 제 1 항에 있어서, According to claim 1,
    상기 제 5 배선층은 정비트라인 및 부비트라인을 포함하며, 금속을 이용하여 형성되는 것을 특징으로 하는 에스램셀의 제조 방법. The method of S. raemsel characterized in that the fifth wiring layer comprises a maintenance of Tra and the sub-bit line, formed using a metal.
  8. 제 1 항에 있어서, According to claim 1,
    상기 제 1 배선층은 상기 제 2 배선층과 상기 제 1 배선층을 연결하기 위한 콘택홀 형성시 패드로 이용하는 것을 특징으로 하는 에스램셀의 제조 방법. The first wiring layer process for producing a S. raemsel, characterized in that when forming the contact hole by using the pad for connecting the second wiring layer and the first wiring layer.
  9. 제 1 항에 있어서, According to claim 1,
    상기 제 4 배선층은 텅스텐 와이어링 또는 텅스텐 플러깅 중 어느 하나를 이용하여 형성되는 것을 특징으로 하는 에스램셀의 제조 방법. The fourth wiring layer process for producing a S. raemsel, characterized in that formed using any one of a tungsten or tungsten wiring plugging.
KR1020000064437A 2000-10-31 2000-10-31 Method of manufacturing sram cell KR20020034313A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020000064437A KR20020034313A (en) 2000-10-31 2000-10-31 Method of manufacturing sram cell

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020000064437A KR20020034313A (en) 2000-10-31 2000-10-31 Method of manufacturing sram cell

Publications (1)

Publication Number Publication Date
KR20020034313A true KR20020034313A (en) 2002-05-09

Family

ID=19696508

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020000064437A KR20020034313A (en) 2000-10-31 2000-10-31 Method of manufacturing sram cell

Country Status (1)

Country Link
KR (1) KR20020034313A (en)

Cited By (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8835989B2 (en) 2008-03-13 2014-09-16 Tela Innovations, Inc. Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with gate electrode placement specifications
US8839175B2 (en) 2006-03-09 2014-09-16 Tela Innovations, Inc. Scalable meta-data objects
US8863063B2 (en) 2009-05-06 2014-10-14 Tela Innovations, Inc. Finfet transistor circuit
US8921897B2 (en) 2006-03-09 2014-12-30 Tela Innovations, Inc. Integrated circuit with gate electrode conductive structures having offset ends
US8951916B2 (en) 2007-12-13 2015-02-10 Tela Innovations, Inc. Super-self-aligned contacts and method for making the same
US8966424B2 (en) 2007-03-07 2015-02-24 Tela Innovations, Inc. Methods for cell phasing and placement in dynamic array architecture and implementation of the same
US9035359B2 (en) 2006-03-09 2015-05-19 Tela Innovations, Inc. Semiconductor chip including region including linear-shaped conductive structures forming gate electrodes and having electrical connection areas arranged relative to inner region between transistors of different types and associated methods
US9122832B2 (en) 2008-08-01 2015-09-01 Tela Innovations, Inc. Methods for controlling microloading variation in semiconductor wafer layout and fabrication
US9159627B2 (en) 2010-11-12 2015-10-13 Tela Innovations, Inc. Methods for linewidth modification and apparatus implementing the same
US9202779B2 (en) 2008-01-31 2015-12-01 Tela Innovations, Inc. Enforcement of semiconductor structure regularity for localized transistors and interconnect
US9230910B2 (en) 2006-03-09 2016-01-05 Tela Innovations, Inc. Oversized contacts and vias in layout defined by linearly constrained topology
US9240413B2 (en) 2006-03-09 2016-01-19 Tela Innovations, Inc. Methods, structures, and designs for self-aligning local interconnects used in integrated circuits
US9269702B2 (en) 2009-10-13 2016-02-23 Tela Innovations, Inc. Methods for cell boundary encroachment and layouts implementing the same
US9336344B2 (en) 2006-03-09 2016-05-10 Tela Innovations, Inc. Coarse grid design methods and structures
US9390215B2 (en) 2008-03-27 2016-07-12 Tela Innovations, Inc. Methods for multi-wire routing and apparatus implementing same
US9563733B2 (en) 2009-05-06 2017-02-07 Tela Innovations, Inc. Cell circuit and layout with linear finfet structures
US9595515B2 (en) 2007-03-07 2017-03-14 Tela Innovations, Inc. Semiconductor chip including integrated circuit defined within dynamic array section
US9633987B2 (en) 2007-03-05 2017-04-25 Tela Innovations, Inc. Integrated circuit cell library for multiple patterning
US9673825B2 (en) 2006-03-09 2017-06-06 Tela Innovations, Inc. Circuitry and layouts for XOR and XNOR logic
US9754878B2 (en) 2006-03-09 2017-09-05 Tela Innovations, Inc. Semiconductor chip including a chip level based on a layout that includes both regular and irregular wires

Cited By (63)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9589091B2 (en) 2006-03-09 2017-03-07 Tela Innovations, Inc. Scalable meta-data objects
US8839175B2 (en) 2006-03-09 2014-09-16 Tela Innovations, Inc. Scalable meta-data objects
US9859277B2 (en) 2006-03-09 2018-01-02 Tela Innovations, Inc. Methods, structures, and designs for self-aligning local interconnects used in integrated circuits
US9443947B2 (en) 2006-03-09 2016-09-13 Tela Innovations, Inc. Semiconductor chip including region having integrated circuit transistor gate electrodes formed by various conductive structures of specified shape and position and method for manufacturing the same
US9905576B2 (en) 2006-03-09 2018-02-27 Tela Innovations, Inc. Semiconductor chip including region having rectangular-shaped gate structures and first metal structures
US9754878B2 (en) 2006-03-09 2017-09-05 Tela Innovations, Inc. Semiconductor chip including a chip level based on a layout that includes both regular and irregular wires
US9741719B2 (en) 2006-03-09 2017-08-22 Tela Innovations, Inc. Methods, structures, and designs for self-aligning local interconnects used in integrated circuits
US8952425B2 (en) 2006-03-09 2015-02-10 Tela Innovations, Inc. Integrated circuit including at least four linear-shaped conductive structures having extending portions of different length
US9711495B2 (en) 2006-03-09 2017-07-18 Tela Innovations, Inc. Oversized contacts and vias in layout defined by linearly constrained topology
US9425272B2 (en) 2006-03-09 2016-08-23 Tela Innovations, Inc. Semiconductor chip including integrated circuit including four transistors of first transistor type and four transistors of second transistor type with electrical connections between various transistors and methods for manufacturing the same
US8921897B2 (en) 2006-03-09 2014-12-30 Tela Innovations, Inc. Integrated circuit with gate electrode conductive structures having offset ends
US8921896B2 (en) 2006-03-09 2014-12-30 Tela Innovations, Inc. Integrated circuit including linear gate electrode structures having different extension distances beyond contact
US8946781B2 (en) 2006-03-09 2015-02-03 Tela Innovations, Inc. Integrated circuit including gate electrode conductive structures with different extension distances beyond contact
US9425145B2 (en) 2006-03-09 2016-08-23 Tela Innovations, Inc. Oversized contacts and vias in layout defined by linearly constrained topology
US10217763B2 (en) 2006-03-09 2019-02-26 Tela Innovations, Inc. Semiconductor chip having region including gate electrode features of rectangular shape on gate horizontal grid and first-metal structures of rectangular shape on at least eight first-metal gridlines of first-metal vertical grid
US9425273B2 (en) 2006-03-09 2016-08-23 Tela Innovations, Inc. Semiconductor chip including integrated circuit including at least five gate level conductive structures having particular spatial and electrical relationship and method for manufacturing the same
US9009641B2 (en) 2006-03-09 2015-04-14 Tela Innovations, Inc. Circuits with linear finfet structures
US9035359B2 (en) 2006-03-09 2015-05-19 Tela Innovations, Inc. Semiconductor chip including region including linear-shaped conductive structures forming gate electrodes and having electrical connection areas arranged relative to inner region between transistors of different types and associated methods
US9673825B2 (en) 2006-03-09 2017-06-06 Tela Innovations, Inc. Circuitry and layouts for XOR and XNOR logic
US9917056B2 (en) 2006-03-09 2018-03-13 Tela Innovations, Inc. Coarse grid design methods and structures
US10186523B2 (en) 2006-03-09 2019-01-22 Tela Innovations, Inc. Semiconductor chip having region including gate electrode features formed in part from rectangular layout shapes on gate horizontal grid and first-metal structures formed in part from rectangular layout shapes on at least eight first-metal gridlines of first-metal vertical grid
US10141335B2 (en) 2006-03-09 2018-11-27 Tela Innovations, Inc. Semiconductor CIP including region having rectangular-shaped gate structures and first metal structures
US10230377B2 (en) 2006-03-09 2019-03-12 Tela Innovations, Inc. Circuitry and layouts for XOR and XNOR logic
US9336344B2 (en) 2006-03-09 2016-05-10 Tela Innovations, Inc. Coarse grid design methods and structures
US10141334B2 (en) 2006-03-09 2018-11-27 Tela Innovations, Inc. Semiconductor chip including region having rectangular-shaped gate structures and first-metal structures
US9230910B2 (en) 2006-03-09 2016-01-05 Tela Innovations, Inc. Oversized contacts and vias in layout defined by linearly constrained topology
US9240413B2 (en) 2006-03-09 2016-01-19 Tela Innovations, Inc. Methods, structures, and designs for self-aligning local interconnects used in integrated circuits
US9633987B2 (en) 2007-03-05 2017-04-25 Tela Innovations, Inc. Integrated circuit cell library for multiple patterning
US10074640B2 (en) 2007-03-05 2018-09-11 Tela Innovations, Inc. Integrated circuit cell library for multiple patterning
US9910950B2 (en) 2007-03-07 2018-03-06 Tela Innovations, Inc. Methods for cell phasing and placement in dynamic array architecture and implementation of the same
US9595515B2 (en) 2007-03-07 2017-03-14 Tela Innovations, Inc. Semiconductor chip including integrated circuit defined within dynamic array section
US9424387B2 (en) 2007-03-07 2016-08-23 Tela Innovations, Inc. Methods for cell phasing and placement in dynamic array architecture and implementation of the same
US8966424B2 (en) 2007-03-07 2015-02-24 Tela Innovations, Inc. Methods for cell phasing and placement in dynamic array architecture and implementation of the same
US8951916B2 (en) 2007-12-13 2015-02-10 Tela Innovations, Inc. Super-self-aligned contacts and method for making the same
US9281371B2 (en) 2007-12-13 2016-03-08 Tela Innovations, Inc. Super-self-aligned contacts and method for making the same
US9818747B2 (en) 2007-12-13 2017-11-14 Tela Innovations, Inc. Super-self-aligned contacts and method for making the same
US9530734B2 (en) 2008-01-31 2016-12-27 Tela Innovations, Inc. Enforcement of semiconductor structure regularity for localized transistors and interconnect
US9202779B2 (en) 2008-01-31 2015-12-01 Tela Innovations, Inc. Enforcement of semiconductor structure regularity for localized transistors and interconnect
US9213792B2 (en) 2008-03-13 2015-12-15 Tela Innovations, Inc. Semiconductor chip including digital logic circuit including at least six transistors with some transistors forming cross-coupled transistor configuration and associated methods
US9536899B2 (en) 2008-03-13 2017-01-03 Tela Innovations, Inc. Semiconductor chip including integrated circuit having cross-coupled transistor configuration and method for manufacturing the same
US10020321B2 (en) 2008-03-13 2018-07-10 Tela Innovations, Inc. Cross-coupled transistor circuit defined on two gate electrode tracks
US9245081B2 (en) 2008-03-13 2016-01-26 Tela Innovations, Inc. Semiconductor chip including digital logic circuit including at least nine linear-shaped conductive structures collectively forming gate electrodes of at least six transistors with some transistors forming cross-coupled transistor configuration and associated methods
US9208279B2 (en) 2008-03-13 2015-12-08 Tela Innovations, Inc. Semiconductor chip including digital logic circuit including linear-shaped conductive structures having electrical connection areas located within inner region between transistors of different type and associated methods
US9117050B2 (en) 2008-03-13 2015-08-25 Tela Innovations, Inc. Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with gate contact position and offset specifications
US9081931B2 (en) 2008-03-13 2015-07-14 Tela Innovations, Inc. Cross-coupled transistor circuit having diffusion regions of common node on opposing sides of same gate electrode track and gate node connection through single interconnect layer
US8872283B2 (en) 2008-03-13 2014-10-28 Tela Innovations, Inc. Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with shared diffusion regions on opposite sides of two-transistor-forming gate level feature
US8866197B2 (en) 2008-03-13 2014-10-21 Tela Innovations, Inc. Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with at least two gate electrodes electrically connected to each other through another transistor forming gate level feature
US8853793B2 (en) 2008-03-13 2014-10-07 Tela Innovations, Inc. Integrated circuit including gate electrode level region including cross-coupled transistors having gate contacts located over inner portion of gate electrode level region and offset gate level feature line ends
US8853794B2 (en) 2008-03-13 2014-10-07 Tela Innovations, Inc. Integrated circuit within semiconductor chip including cross-coupled transistor configuration
US8847331B2 (en) 2008-03-13 2014-09-30 Tela Innovations, Inc. Semiconductor chip including region having cross-coupled transistor configuration with offset electrical connection areas on gate electrode forming conductive structures and at least two different inner extension distances of gate electrode forming conductive structures
US8847329B2 (en) 2008-03-13 2014-09-30 Tela Innovations, Inc. Cross-coupled transistor circuit defined having diffusion regions of common node on opposing sides of same gate electrode track with at least two non-inner positioned gate contacts
US8836045B2 (en) 2008-03-13 2014-09-16 Tela Innovations, Inc. Cross-coupled transistor circuit having diffusion regions of common node on opposing sides of same gate electrode track
US9871056B2 (en) 2008-03-13 2018-01-16 Tela Innovations, Inc. Semiconductor chip including integrated circuit having cross-coupled transistor configuration and method for manufacturing the same
US8835989B2 (en) 2008-03-13 2014-09-16 Tela Innovations, Inc. Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with gate electrode placement specifications
US9390215B2 (en) 2008-03-27 2016-07-12 Tela Innovations, Inc. Methods for multi-wire routing and apparatus implementing same
US9779200B2 (en) 2008-03-27 2017-10-03 Tela Innovations, Inc. Methods for multi-wire routing and apparatus implementing same
US9122832B2 (en) 2008-08-01 2015-09-01 Tela Innovations, Inc. Methods for controlling microloading variation in semiconductor wafer layout and fabrication
US9563733B2 (en) 2009-05-06 2017-02-07 Tela Innovations, Inc. Cell circuit and layout with linear finfet structures
US8863063B2 (en) 2009-05-06 2014-10-14 Tela Innovations, Inc. Finfet transistor circuit
US9530795B2 (en) 2009-10-13 2016-12-27 Tela Innovations, Inc. Methods for cell boundary encroachment and semiconductor devices implementing the same
US9269702B2 (en) 2009-10-13 2016-02-23 Tela Innovations, Inc. Methods for cell boundary encroachment and layouts implementing the same
US9159627B2 (en) 2010-11-12 2015-10-13 Tela Innovations, Inc. Methods for linewidth modification and apparatus implementing the same
US9704845B2 (en) 2010-11-12 2017-07-11 Tela Innovations, Inc. Methods for linewidth modification and apparatus implementing the same

Similar Documents

Publication Publication Date Title
US8004042B2 (en) Static random access memory (SRAM) cell and method for forming same
US6677649B2 (en) SRAM cells with two P-well structure
US7586149B2 (en) Circuit device including vertical transistors connected to buried bitlines and method of manufacturing the same
JP4885365B2 (en) Semiconductor device
US6670642B2 (en) Semiconductor memory device using vertical-channel transistors
CN100539157C (en) Semiconductor memory and its manufacture method
JP3989888B2 (en) Vertical mosfetsram cell and manufacturing method thereof
JP3749101B2 (en) Semiconductor device
CN103165177B (en) The storage unit
US6642555B1 (en) Semiconductor memory device
CN103366800B (en) Method and apparatus for cell structure sram
US20040005755A1 (en) Semiconductor memory device and a method of manufacturing the same
CN103151070B (en) A method and apparatus for FinFET SRAM array integrated circuit
US6417549B1 (en) Static random access memory device and method for manufacturing the same
JP4493398B2 (en) Semiconductor device
CN101989604B (en) Memory element
US7193278B2 (en) Static random access memories (SRAMS) having vertical transistors
US5300814A (en) Semiconductor device having a semiconductor substrate with reduced step between memory cells
US6606276B2 (en) SRAM device using MIS transistors
KR20140070306A (en) Contact plugs in sram cells and the method of forming the same
JP2005203777A (en) Semiconductor integrated circuit for adopting laminated node-contact structure and laminated thin-film transistor, and manufacturing method thereof
JPH0613582A (en) Manufacture of thin-film pseudo-planar pfet device
JPH06318681A (en) Semiconductor storage and its manufacture
US6271081B2 (en) Semiconductor memory device
US6870231B2 (en) Layouts for CMOS SRAM cells and devices

Legal Events

Date Code Title Description
WITN Withdrawal due to no request for examination