JP2703970B2 - MOS type semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial application field) The present invention relates to a MOS type semiconductor device, and in particular, a MOS transistor structure capable of effectively utilizing a substrate area, and integration using the same. Circuit.

(Prior Art) Semiconductor integrated circuits, especially integrated circuits using MOS transistors, are continually being highly integrated. With this high integration, the MOS transistors used therein have been miniaturized to the submicron region. Although the basic circuit of a digital circuit is an inverter circuit, various adverse effects appear as the MOS transistors constituting the inverter circuit are miniaturized. First, when the gate size of the MOS transistor is reduced, a so-called short channel effect causes punch-through between the source and the drain, making it difficult to suppress a leak current. As a result, the standby current of the inverter circuit increases. Second, the internal electric field of the MOS transistor increases, and the threshold value and transconductance of the transistor fluctuate due to the hot carrier effect. As a result, the transistor characteristics deteriorate and the circuit characteristics (operation speed, operation margin, etc.) deteriorate. Occurs. Third
In addition, even if the gate length is shortened due to miniaturization, the gate width must be more than a certain amount in order to secure the necessary current amount. As a result, the area occupied by the inverter circuit must be sufficiently small. difficult. For example dynamic
In RAM (DRAM), memory cell miniaturization technology is remarkably progressing, but there are many parts in peripheral circuits where the gate width cannot be reduced in order to secure the required current amount, and this is the whole DRAM chip. This hinders miniaturization.

Further, when the gate electrode is formed of a polycrystalline silicon film, the propagation of signals to the gate electrode is delayed due to the CR time constant composed of the polycrystalline silicon film resistance and the gate capacitor. With the miniaturization of the device, the thickness of the gate oxide film is reduced and the switching speed is improved, so that the signal delay at the gate electrode occupies most of the switching time of the inverter. Source,
The junction capacitance of the drain is also increasing due to an increase in the substrate concentration with miniaturization, which causes a reduction in switching speed.

(Problems to be Solved by the Invention) As described above, in the conventional MOS integrated circuit technology, it is difficult to suppress the leakage current of the inverter circuit, the reliability is reduced due to the hot carrier effect, and the required current amount is reduced. There is a problem that the area occupied by the circuit cannot be easily reduced due to the demand for securing the gate, and the delay at the gate electrode is large, so that the gate width cannot be increased. A similar problem exists not only in an inverter circuit but also in a case where a flip-flop circuit is configured.

An object of the present invention is to provide a MOS semiconductor device which solves such a problem.

[Structure of the Invention] (Means for Solving the Problems) A MOS transistor according to the present invention is constituted by using a plurality of columnar semiconductor layers formed in an array on a semiconductor substrate and separated by grooves. A gate insulating film is formed on side surfaces of the plurality of columnar semiconductor layers, and a gate electrode is continuously provided in the trench so as to surround these columnar semiconductor layers.
Source and drain diffusion layers are respectively formed on the upper surface and the groove bottom of each columnar semiconductor layer, the first main electrode is commonly connected to the upper surface diffusion layers of the plurality of columnar semiconductor layers, and the second main electrode is formed on the groove bottom. Connected to the diffusion layer.

The plurality of columnar semiconductor layers constituting one MOS transistor preferably have a pattern dimension of about the minimum processing dimension and a distance between the columnar semiconductor layers of the minimum processing dimension of 2 to 2.
Approximately three times or less.

In the present invention, a basic circuit of an integrated circuit such as an inverter or a flip-flop is formed using the MOS transistor as described above.

(Operation) In the structure of the present invention, the sub-threshold characteristic of the MOS transistor is steep, and the sub-threshold swing is extremely small. This is explained in more detail below.
This is due to the strong controllability of the gate to the channel. Therefore, the leakage current of the inverter circuit and the like is effectively suppressed.

Further, the side wall of the columnar semiconductor layer serves as a channel region, and there is no portion where the channel region is in contact with the field region as in a normal planar MOS transistor. Therefore, there is no effect of the high electric field at the field edge on the channel region.
The hot carrier effect is suppressed. Further, the channel length can be increased by increasing the height of the columnar semiconductor layer, that is, the depth of the groove, without increasing the occupied area, which is also effective in suppressing the hot carrier effect. By suppressing the hot carrier effect, a highly reliable inverter circuit and flip-flop circuit can be obtained.

Further, since a channel region is provided so as to surround the periphery of the plurality of columnar semiconductor layers, a large gate width can be realized with a small chip occupation area, and the occupation area is particularly reduced in a portion requiring a certain amount of current. The effect is obtained. Furthermore, if the pattern size of one columnar semiconductor layer is a rectangle having a small size, for example, about the minimum processing size (actually, it becomes a round shape due to processing roundness), it easily extends from the drain layer at the bottom of the groove during operation. A state in which the depletion layer electrically separates the columnar semiconductor layer region from the underlying semiconductor layer region, or a state in which the columnar semiconductor layer is depleted by the depletion layer extending from the side surface is obtained. This also leads to an improvement in the sub-threshold characteristic, and also makes it possible to obtain a characteristic with extremely low substrate bias dependence.

Also, since the gate width utilization rate per unit area of the substrate is high, when compared with the same gate width, a MOS transistor with a normal flat structure
The junction area between the source and the drain can be extremely small as compared with the transistor. Thereby, the operation speed is improved. Since the gate electrode is provided so as to surround the plurality of columnar semiconductor layers, a signal delay at the gate electrode is reduced, which also contributes to an improvement in operation speed.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

1 (a) and 1 (b) are a plan view and an equivalent circuit diagram of a CMOS inverter circuit according to one embodiment. FIG. 2 (a),
(B), (c) and (d) are each shown in FIG.
AA ', BB', CC 'and DD' sectional views of FIG. In a silicon substrate 1, an n-type well 2 and a p-type well 3
Are formed, and a plurality of pillar-shaped silicon layers 5 and 6 which are projected in an island shape and surrounded by the groove 4 are arranged in each well region. MO by 2x4 columnar silicon layer 5
S transistor Q _P is formed, n-channel MOS transistor Q _N is formed by the pillar-shaped silicon layer 6 of 2 rows × 2 columns. MOS transistors Q _P and Q _N are each composed of a columnar silicon layer.
It has a vertical structure with the entire side walls 5 and 6 as channel regions. That is, an element isolation oxide film is formed in an element isolation region in the groove 4, a gate oxide film 7 is formed on the outer peripheral surfaces of the silicon layers 5 and 6, and a gate electrode 8 is formed in the groove 4 so as to surround the outer periphery. It is embedded and continuously arranged. The gate electrode 8 is formed, for example, by depositing a p ⁺ -type or n ⁺ -type polycrystalline silicon film, and forming it on the side surfaces of the columnar silicon layers 5 and 6 by a resist process and anisotropic etching such as reactive ion etching. It is obtained by leaving it on a flat portion serving as a connection portion of a gate electrode of a transistor. After the formation of the gate electrode 8, a source diffusion layer 9 is formed on each upper surface of the plurality of columnar silicon layers 5 and a drain diffusion layer 10 is formed on the bottom of the groove by ion implantation of p-type impurities. Similarly, ion implantation of n-type impurities is performed. Source and drain layers 11 and 12 on the n-channel side are formed. Part of the drain diffusion layers 10 and 12 is formed in advance between the plurality of columnar silicon layers 5 and between the plurality of columnar silicon layers 6 before forming the gate electrode. The substrate thus formed is covered with a CVD oxide film 13, a contact hole is formed in the substrate, and necessary terminal wirings, that is, _Vcc wiring 14, _VSS wiring,
An input terminal (Vin) wiring 16 and an output terminal (Vout) wiring 17 are formed.

In this embodiment, when the channel of each transistor is inverted in the operation of the inverter circuit, each columnar silicon layer region is electrically separated from a region below it by a depletion layer extending from the drain layer. Is set. Particularly preferably, the pattern dimension of one columnar silicon layer is set to about the minimum processing dimension. Specifically illustrating such a state in FIG. 3 for one of the silicon layer of p-channel MOS transistor Q _P side. When the depletion layers 19 extending so as to be sandwiched from the drain 12 formed at the bottom of the groove come into contact with each other, the columnar silicon layer 6 is separated from the substrate region therebelow and enters a floating state. For example, to satisfy such a condition, p
The impurity concentration of the mold well 3 may be 3 × 10 ¹⁶ / cm ³ , the width of the columnar silicon layer 3 may be 1 μm, and the gate oxide film thickness may be 120 °. The same condition is also satisfied on the n-channel side.

The advantages of the inverter circuit according to this embodiment will be specifically clarified while comparing with the conventional structure. In the structure of this embodiment, the channel length of the MOS transistor is substantially the depth of the groove 4. 19 now required channel width, 38.4μm a p-channel MOS transistor Q _P, an n-channel MOS transistor.
2 μm. When one side of the rectangular plane of the pillar-shaped silicon layer 5, and 6 and 1 [mu] m, the pillar-shaped silicon layer of p-channel MOS transistor Q _P and an n-channel MOS transistor Q _N 5
The desired channel width can be obtained by setting the numbers of and 6 to 8 and 4, respectively, as shown in FIG. 1 (a). At this time, the area occupied by the pattern in FIG. 1A is approximately 5.4 × 12.3 = 66.4 μm ² . For comparison, FIG. 23 shows a pattern in the case where a CMOS inverter circuit having the same current driving capability is formed by a conventional planar structure. The channel length is 0.5 μm for both the p-channel and the n-channel. The channel width is 38.4 μm for the p-channel side and 19.2 μm for the n-channel side.
μm. At this time, the area occupied by the inverter circuit is approximately 3 × 60.6 = 181.8 μm ² .

As is apparent from the above comparison results, according to this embodiment, the area occupied by the circuit can be significantly reduced. In a portion where the required current amount is small, that is, in a portion where the channel width may be small, the ratio of the contact hole area to the circuit occupation area is originally large. The contact hole area is not different between the present invention and the conventional structure. Therefore, the effect of reducing the occupied area according to the present invention is greatly exhibited in a circuit portion having a large channel width. In this sense, the present invention can provide a great effect when applied to a peripheral circuit section such as a DRAM. In DRAMs, a technology for high integration by introducing a trench capacitor structure into memory cells is promising, but if trenches in the memory cell area and trenches in the inverter part of the peripheral circuit are performed at the same time, It is advantageous also in the process.

FIGS. 19 (a) and 19 (b) show the sub-threshold characteristics of the conventional p-channel MOS transistor of the planar structure and the p-channel MOS transistor of the embodiment, respectively. The channel width / channel length is W / L = 8.0 μm / 0.8 μm. The relationship between the channel width W and the channel length L in this embodiment is clearly shown in FIG. Gate oxide film is equally 200
測定, the measurement conditions were drain voltage Vd = 0.05 V, and the substrate bias was changed to Vsub = 0, 2, 4, 6 [V]. In the transistor of this embodiment, the subthreshold characteristic is clearly steep as compared with the conventional structure. The swing S (= dVg / d (log Id)) is 98mV / deca in the conventional structure.
In contrast to de, in this embodiment, it is as small as 72 mV / decade. This indicates that in the case of this embodiment, the controllability of the gate to the channel is strong. In particular, when the size of the unit silicon layer is small, the silicon layer is easily completely depleted when a gate voltage is applied, and the change in the channel potential with respect to the gate voltage becomes large. Because of this sub-threshold characteristic, this embodiment has an advantage that the standby current of the inverter circuit can be suppressed. Fig. 19 (a)
As is clear from the comparison of (b), in this embodiment, there is no variation due to the substrate bias Vsub in the region where the drain current rises, that is, the region where channel inversion occurs.
This is because, as described with reference to FIG. 3, in the case of this embodiment, at the time of channel inversion, the transistor portion is substantially electrically separated from the lower substrate region by the depletion layer from the drain layer. As a result, the circuit of this embodiment exhibits strong resistance to substrate noise.

FIGS. 20 (a) and 20 (b) show the amount of deterioration ΔGm / Gmo of the mutual conductance and the amount of deterioration ΔIds / Id of the drain current when the hot carrier effect stress is applied to the n-channel MOS transistor in the inverter circuit of this embodiment.
The stress time dependence of the so
It is shown in comparison with a transistor. From this data,
It can be seen that in the structure of this embodiment, the amount of deterioration of the characteristics is small and the reliability is improved. An inverter circuit using such a highly reliable transistor is advantageous in operation speed and operation margin.

FIGS. 22 (a) and 22 (b) show a comparison of the static characteristics of the transistor between the conventional structure and the structure of the present invention. The channel width W and the channel length L are W / L = 4.0 μm / 0.8 μm, the gate oxide film thickness is Tox = 200 °, and the substrate bias voltage is Vsub = 0 V, which is occupied by the conventional structure as shown in FIG. Area 5
× 6 = 30 μm ² , and in the present invention, 5 × 2.4 =
It is formed to 12 μm ² . As described above, in the device of the present invention, even if the transistor area is 1/2 or less, the same drain current as that of the conventional structure is obtained, and the device has high driving capability. Therefore, according to the embodiment of the present invention, high integration of various integrated circuits can be achieved.

In the above embodiment, the gate electrodes 8 of the n-channel MOS transistor and the p-channel MOS transistor are continuously and commonly formed, but they may be different depending on the configuration of the channel. FIG. 4 shows the pattern of the embodiment in that case in correspondence with FIG. 1 (a). The gate electrode ₈₂ of the gate electrode ₈₁ and the n-channel side of the p-channel side formed separately, it is common connecting the input lines 16. As a result, although the area slightly increases, the characteristics of each transistor can be optimized.

The present invention can be similarly applied to inverter circuits other than the CMOS inverter. Such another embodiment will now be described. In the following drawings, parts corresponding to those in FIGS. 1 and 2 are denoted by the same reference numerals, and detailed description is omitted.

FIGS. 5A and 5B are a plan view showing an embodiment of the E / R type inverter circuit and an equivalent circuit thereof. FIG. 6 (a),
(B) is a sectional view taken along line AA 'and BB' of FIG. 5 (a), respectively. A plurality of (two in the figure) columnar silicon layers 6 are formed in the p-type silicon layer 3 (well or substrate itself) by the grooves 4 in the same manner as in the previous embodiment. n-channel in the same manner as in example, to form a MOS transistor Q _n E-type. A resistor 20 made of, for example, a polycrystalline silicon film is formed as a load element R adjacent to the transistor.

According to this embodiment, the area occupied can be further reduced as is apparent from comparison with FIG.

FIGS. 7A and 7B are a plan view showing an embodiment of the E / D inverter and an equivalent circuit thereof. Fig. 8 (a), (b)
7A and 7B are sectional views taken along the lines AA 'and BB' of FIG. 7A, respectively. In this embodiment, the pillar-shaped silicon layer ₆₁ one by two into p-type silicon layer 3, 6 ₂ is formed, n-channel for the driver in the same manner as the still previous embodiments each, E type MO
S transistor Q _NE and n-channel, D type MOS for load
A transistor Q _ND is formed. In this case, the load side
MOS transistors because a D-type, the sidewall of the pillar-shaped silicon layer 6 ₂ is required to form the n-type layer 21.

9 (a) and 9 (b) are a plan view of an embodiment of the E / E type inverter circuit and an equivalent circuit thereof. Fig. 10 (a), (b)
9A and 9B are sectional views taken along the lines AA 'and BB' of FIG. 9A, respectively. This embodiment is the same as the previous embodiment except that both the driver and the load are E type, n-channel MOS transistors Q _NE1 and Q _NE2 , and the gate on the load side is connected to the _VCC wiring 14. It is.

11 (a) and 11 (b) are a plan view of an embodiment of a dynamic inverter circuit and an equivalent circuit thereof. FIGS. 12 (a) and 12 (b) are AA 'and B of FIG. 11 (a), respectively.
It is -B 'sectional drawing. This embodiment, independent terminals wiring 22 is provided to the gate terminal of the load side, except that the inverted amplified signal phi _B input terminal Vin is to enter, basically above Example Is the same as

The above E / R type inverter, E / D type inverter, E / E type inverter, and dynamic type inverter are composed of only n-channel MOS transistors, do not require a well isolation region, and the process is simpler. Also, the occupied area can be reduced. A similar configuration can be configured using only p-channel MOS transistors. In the above description, only the case where the gate electrode completely surrounds the outer periphery of the columnar semiconductor layer is shown. However, the present invention is also effective when the gate electrode does not constitute a complete closed circuit.

In the above, MOS composed of multiple silicon layers
Although the embodiment in which the transistor is applied to the inverter circuit has been described, the present invention can be similarly applied to other circuits. For example, a flip-flop is a basic circuit of various integrated circuits. Therefore, an embodiment in which the present invention is applied to a flip-flop circuit will be described next.

13 (a) and 13 (b) are a plan view and an AA 'sectional view of an embodiment in which the present invention is applied to a DRAM bit number sense amplifier. FIG. 14 shows an equivalent circuit thereof.

FIGS. 13 (a) and 13 (b) show an NMOS sense amplifier section constituted by a flip-flop comprising two n-channel MOS transistors Q ₁ and Q ₂ . A p-type well 32 is formed in a silicon substrate 31, and a plurality of columnar silicon layers 34 projecting in an island shape surrounded by a groove 33 in the p-type well 32.
(34 ₁ , 34 ₂ ,...) Are formed. MOS transistor Q
₁ is constituted by using two silicon layers 34 ₃₁ and 34 ₃₂ among them, and the other MOS transistor Q ₂ is constituted by using other two silicon layers 34 ₂₁ and 34 ₂₂ . That is, the gate insulating film 35 on the outer peripheral surface of the silicon layer 34 _2, 34 ₃ of the two by two, respectively is formed, a gate electrode 36 made of polycrystalline silicon film so as to surround the outer peripheral surface is buried in the groove I have. Drain in the silicon layer 34 _2, 34 ₂ of the top surface and the groove 33, n ⁺ -type diffusion layer 37, 38 serving as a source is formed. Bit lines 39 ₁ paired, 39 _2, polycrystalline silicon film by MOS transistors Q ₁ respectively, drains i.e. silicon layer 34 _{and second} Q _2, 34 ₃ of the upper surface of the n ⁺ -type diffusion layer 37 is contact with arranged Have been. The gate electrode 36 of the MOS transistor Q ₁ is withdrawn until the Figure 13 silicon layer 34 on ₄ in lower right in the layout of (a), the bit line 39 ₂ is made to contact where the gate electrode 36. The gate electrode 36 of the MOS transistor Q ₂ are taken out to the silicon layer 34 on _one of the left diagonally on the layout of FIG. 13 (a), the bit line 39 ₁ is brought into contact wherein the gate electrode 36. That pillar-shaped silicon layer 34 _1, 34 ₄ are not necessarily provided for forming a MOS transistor, is provided as a seat for ensuring a bit line contact for connecting a bit line to the gate electrode . By that taking these silicon layers 34 _1, 34 ₄ gate electrode on the drain layer and a gate electrode contact portion is from substantially the same plane, the depth of the contact hole of the bit line can be made uniform. The source diffusion layer 38 formed at the bottom of the groove 33 is a common source node, to which an Al wiring 40 is in contact. This common source node is not shown in FIG. 13, but as shown in the equivalent circuit of FIG.
It is connected to the ground potential V _SS via the MOS transistor Q ₃ .

Although not shown in the figure, p along the same bit line
A PMOS sense amplifier using channel MOS transistors is formed with a similar structure and layout.

In the bit line sense amplifier according to this embodiment, as described in the previous embodiment of the inverter circuit, the chip occupation area due to the gate width is very small as compared with the case where a MOS transistor having a planar structure is used. Further, the subthreshold characteristic of the MOS transistor is steep, the signal delay at the gate electrode is small, and high-speed operation is possible.

In this embodiment, when the sense amplifier MOS transistor operates, a depletion layer is formed on the silicon layer as shown in FIG.
It extends from the side of 34 toward the center. Therefore, if the size and the impurity concentration of the silicon layer 34 are selected, for example, if one silicon layer is reduced to the size of the minimum processing size,
Depletion is easily caused up to the center of the silicon layer 34, and the resistance of the silicon layer 34 in the vertical direction becomes sufficiently large. As a result, a flip-flop operation resistant to substrate noise is obtained. Further, the limitation of the extension of the depletion layer means that the controllability of the gate with respect to the channel is strong, as described in the previous embodiment, thereby obtaining excellent characteristics.

An embodiment in which the present invention is applied to an SRAM will be described below. MOS
In a typical SRAM using a transistor, a memory cell is configured by a flip-flop, and this flip-flop can have a vertical structure using a plurality of columnar silicon layers as in the above-described embodiment.

FIG. 16 is a plan view of the SRAM cell part of the embodiment, and FIG.
Figure 17 shows the equivalent circuit. By forming a groove in the silicon substrate in the same manner as in the previous embodiment, the columnar silicon layer is formed.
41 (41 ₁ , 41 ₂ ,...) Are arranged and formed. MOS transistors T ₁ and T ₂ for the transfer gates are formed respectively by using a silicon layer 41 ₁ and 41 ₂ of one by one. The structure is basically the same as the previous embodiment, a drain diffusion layer is formed on the upper surface of the silicon layer, and a source diffusion layer is formed in the groove,
These silicon layers 41 _1, 41 ₂ gate electrode 42 ₁ by the polycrystalline silicon film to surround the is formed. Gate electrode 4
2 ₁ constitutes a word line WL is continuously formed for the two MOS transistors T _1, T _2. MOS for one driver
Transistor T ₃ by using two silicon layers 41 _31, 41 _32, MOS transistors T ₄ for the other drivers are formed by using the other two silicon layers 41 _61, 41 _62. These MOS transistors also have the same structure as the previous embodiment. The gate electrode 42 ₂ of the MOS transistor T ₃ is
Extended to the silicon layer 41 ₄ as the base, and wherein by contact with the gate electrode 42 ₂ polycrystalline silicon film wires 43 ₂ connected between the drain of the MOS transistor T ₂ and T _4. Similarly, the gate electrode 42 ₃ of the MOS transistor T ₄ is
Extended to the silicon layer 41 ₅ as the base, and wherein by contact with the gate electrode 42 ₃ of the MOS transistors T ₁ and the polycrystalline silicon film wires 43 ₁ connected between the drain of T _3. The drain wiring 43 _1, 43 ₂ are connected to a power source (V _CC) line 43 ₃ by a high-resistance polycrystalline silicon film 44 _1, 44 ₂ via the polycrystalline silicon film serving as a load resistor. A
l Data lines 45 ₁ and 45 ₂ and ground ( _VSS ) line 45 ₃
Is cut off in the middle. Data lines 45 _1, 45 ₂ are disposed in contact with the contact portion 46 _1, 46 ₂ for the source diffusion layer formed in the groove of the MOS transistors T _1, T _2, respectively. Ground line 45 _3, MOS transistor T _3,
It is disposed in contact with the contact portion 46 ₃ to a common source diffusion layer to T _4. A region 47 surrounded by a dashed line in the drawing indicates an element region.

According to this embodiment, the same effect as that of the previous embodiment can be obtained. However, an SRAM cell does not originally require a large gate width unlike a bit line sense amplifier of a DRAM. Therefore, although the effect of reducing the occupied area is not so large, the effect of improving the characteristics by configuring the driver MOS transistor using a plurality of small silicon layers is large.

Fig. 16 shows an SRAM using a high resistance polycrystalline silicon load.
In the above, the CMOS type flip-flop, E
The present invention can be similarly applied to an SRAM using a / E flip-flop or an E / D flip-flop.

[Effects of the Invention] As described above, according to the present invention, by using a MOS transistor having a vertical structure in which the side walls of a plurality of columnar semiconductor layers are used as channels, various types of MOs whose occupied area is significantly reduced can be obtained.
An S integrated circuit can be obtained. Further, since the channel region is not in contact with the field, resistance to the hot carrier effect is strong, and excellent circuit characteristics can be obtained. Furthermore,
By improving the sub-threshold characteristics, the current consumption during standby can be greatly reduced. In particular, by making the size of the unit silicon layer as small as the minimum processing size, the junction capacitance of the source and drain can be made very small with respect to the required gate width, and at the same time, the signal delay at the gate electrode can be reduced. It is possible to realize a circuit capable of performing a high-speed switching operation with a remarkable reduction.

[Brief description of the drawings]

1 (a) and 1 (b) are a plan view and an equivalent circuit diagram showing a CMOS inverter circuit according to one embodiment of the present invention, and FIG. 2 (a).
3 (d) are cross-sectional views of the respective parts, FIG. 3 is a diagram for explaining the characteristics of the transistor of the above embodiment during operation, and FIG. 4 is a diagram in which the gate electrodes of the two transistors in FIG. 5 (a) and 5 (b) are plan views showing an embodiment according to the present invention.
Plan view and an equivalent circuit diagram showing an embodiment of the type inverter circuit, FIGS. 6 (a) and 6 (b) are cross-sectional views of each part, and FIG.
FIGS. 8 (a) and 8 (b) are cross-sectional views of respective parts, and FIGS. 9 (a) and 9 (b) are implementations of an E / E type inverter circuit. FIGS. 10 (a) and 10 (b) are cross-sectional views of respective parts, and FIGS. 11 (a) and 11 (b) are plan views of an embodiment of a dynamic inverter circuit and its equivalent circuit. Figures 12 (a) and 12 (b) are cross-sectional views of each part, and Figs. 13 (a) and 13 (b)
Plan view and sectional view of an embodiment of a DRAM sense amplifier, FIG.
FIG. 15 is an equivalent circuit diagram of the sense amplifier, FIG. 15 is a diagram for explaining characteristics during operation of the MOS transistor of this embodiment, FIG. 16 is a plan view of the SRAM embodiment, and FIG. 18 (a) and 18 (b) are diagrams schematically showing the p-channel MOS transistor structure of the embodiment of FIG. 1, and FIGS. 19 (a) and (b) are diagrams of the embodiment of FIG. FIGS. 20 (a) and 20 (b) show the subthreshold characteristics of the p-channel MOS transistor in comparison with the conventional structure. FIGS. 20 (a) and (b) show the characteristics change due to the hot carrier effect stress in comparison with the conventional structure. FIG. 22 (a) is a diagram showing the transistor area according to the present invention prototyped for the test in comparison with the conventional structure.
(B) is a diagram showing the static characteristics in comparison with the conventional structure, and FIG.
FIG. 23 is a plan view showing a conventional MOS transistor structure having element parameters corresponding to FIG. 1 (a). 1 ... silicon substrate, 2 ... n-type well, 3 ... p-type well, 4 ... groove, 5, 6 ... columnar silicon layer, 7 ... gate oxide film, 8 ... gate electrode, 9, 10 ... p-type source / drain diffusion layers, 11, 12 ... n-type source / drain diffusion layers, 13 ... CVD
Oxide film, 14-17: Al wiring, 19: Depletion layer.

Claims (4)

(57) [Claims] In a semiconductor device including an inverter circuit formed by using MOS transistors, a plurality of columnar semiconductor layers are arranged and formed on a semiconductor substrate by separating the MOS transistors forming the inverter circuit by grooves.
A gate insulating film is formed on the outer peripheral surface of each columnar semiconductor layer, and a gate electrode is continuously disposed in the groove so as to surround the plurality of columnar semiconductor layers. A MOS type semiconductor device having a structure in which a source and a drain diffusion layer are respectively formed at the bottom of a groove surrounding a layer. 2. A semiconductor device including a flip-flop circuit formed by using MOS transistors, wherein the MOS transistors forming the flip-flop circuit are separated by grooves on a semiconductor substrate and a plurality of columnar semiconductor layers are formed in an array. A gate insulating film is formed on the outer peripheral surface of each columnar semiconductor layer, and a gate electrode is continuously disposed in the trench so as to surround the plurality of columnar semiconductor layers. A MOS type semiconductor device having a structure in which a source and a drain diffusion layer are respectively formed at the bottom of a groove surrounding a columnar semiconductor layer. 3. The semiconductor device according to claim 1, wherein said columnar semiconductor layer is electrically separated from the semiconductor region thereunder by a depletion layer extending from an outer peripheral surface during operation or depleted inside. 3. The MOS type semiconductor device according to item 2. 4. The MOS semiconductor device according to claim 1, wherein said columnar semiconductor layer is patterned with a minimum processing dimension.