JPH04146670A - Memory cell and semiconductor device having mos inverter - Google Patents

Abstract

PURPOSE:To realize the simplification of a process and a reduction in the dimensions of connection parts by a method wherein a thin film transistor is used as an N-channel MOS transistor having source and drain regions consisting of an N-type doped polycrystalline silicon film and this N-channel MOS transistor is used in respect to the region of the negative characteristics out of U-shaped characteristics peculiar to a polycrystalline silicon thin film transistor and is substantially made to perform the operation of a P-channel MOS transistor. CONSTITUTION:The title device has a flip-flop 3 constituted by connecting a pair of CMOS inverters 1 and 2 into a loop connection, a bit line BIT, which is turned ON/OFF by an address line 4, and transfer gates 5 and 6 of an N- channel MOS transistor for controlling the receipt and delivery of data on the BIT and a flip-flop 3, but the inverters 1 and 2 are respectively constituted of series-connected N-channel MOS drive transistors T1N and T2N between supply voltage (VDD and VSS) and load transistors T'1N and T'2N which are N-channel thin film transistors. That is, the transistors T'1N and T'2N are not P-channel transistors but are the N-channel thin film transistors.

Description

Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a semiconductor static RAM (Random Access Memory) using a CMO3 (complementary MO3) transistor, and in particular to a semiconductor static RAM (Random Access Memory) using an n-channel thin film transistor as a load transistor. Regarding the MOS inverter used.

[Prior Art] As shown in FIG. 5, a 5M0S static type memory cell is turned on/off by a flip-flop 3 in which a pair of CMOS inverters 1.2 are connected in a loop, and an address line 4.
It has n-channel MO3 transfer gates 5 and 6 that are turned off to control the flow of data between the bit lines BIT and BIT and the flip-flop 3. Each CMOS inverter1.
2 are n-channel MO3 drive transistors TIN and TE connected in series between power supply voltages (VDD, VSS).
N and p-channel enhancement type MO3 load transistors T, , T2 . Almost no current flows at a stable point (data retention), and current flows only when transitioning from one stable point to another (during read/write).

Conventionally, as shown in FIG. 6, the structure of the MOS inverter in this 6M0S static memory cell is to use a P-channel thin film transistor as the load transistor, which is stacked on top of an N-channel drive transistor formed in bulk silicon. (joint MO3 structure) is known. That is, the n-channel drive transistors T, . n-type source region 14 and LD formed by self-line with 12 and sidewall 13 as a mask.
It has a D-structure n-type drain region 15, and the load transistors T, , T, of the thin film transistors
n-channel drive transistor TIN.

T2. The gate electrode 12 of 1 is shared as a gate electrode, and the glabellar insulating film formed thereon is used as a gate insulating film 16. , a source region 18° and a drain region 19 in which a second layer of polycrystalline silicon is doped with P type. and load transistors T, ,T, ,
drain region 19 and drive transistors T, N, T, N
The connection structure of the drain region 15 is such that the n-type connection portion 20 using the first layer of polycrystalline silicon is connected to both drain regions 15.1.
9. This n-type doped connection portion 20 and the p-type doped drain region 19 connected thereto exhibit diode characteristics. However, its diode characteristics have a low reverse breakdown voltage and a large reverse current, so it does not pose much of a problem. In addition, 21 is a local oxide film (LOCO3)
22 is a second interlayer insulating film.

In this way, the gate electrode 12 is shared and the driving transistors T, . . . T2 . On top of that load transistor T, ,
, T, , are stacked, it is possible to reduce the cell area and obtain a large capacity SRAM.

[Problem to be solved by the invention]

However, the above memory cell structure has the following problems.

That is, in the connection structure of both drains, a connection part 2 made of n-type doped first layer polycrystalline silicon is provided in order to make ohmic contact.
0 formation is required. The connection part 2o is obtained by forming the first layer of polycrystalline silicon like the gate electrode 12, but since it is necessary to make conductive contact with the drain region 15 by a buried contact, a photoresist process is performed to open a window in the surface silicon oxide film. This results in an increase in man-hours. Furthermore, the presence of this connection portion 20 increases the memory cell size accordingly. In a submicron process using an LDD structure, sidewalls 13 are inevitably parasitic on both sides of the connection portion 2o, so the area of the connection portion, including the sidewalls 13, is as large as the drive transistor T. ,,,T2. It has reached about half of the area occupied by
It has a non-negligible occupation ratio in the reduction of memory cell size.

Furthermore, in order to improve the characteristics of the P-channel thin film transistor formed in the second layer polycrystalline silicon, when the crystallinity of the second layer polycrystalline silicon is improved, the characteristics of the diode formed in the connection portion 20 are also improved. Resulting in. That is, the connecting portion 20 made of n-type doped polycrystalline silicon and the connecting portion 20 made of p-doped polycrystalline silicon.
The junction of the layered polycrystalline silicon becomes a current barrier as a normal diode characteristic, and the electrical characteristics of the entire CMO3 circuit deteriorate.

Therefore, the present invention solves the above problems,
The problem is to load the second polycrystalline silicon layer with MO3
A semiconductor device having a MOS inverter structure that enables direct contact to the drain region of the MOS inverter and eliminates the first layer polycrystalline silicon connection, thereby simplifying the process and reducing the size of the connection. Our goal is to provide the following.

[Means to solve the problem]

In order to solve the above problems, the measures taken by the present invention are p
A thin film transistor that shares the gate electrode of a channel load transistor is formed above this load transistor.The thin film transistor is an n-channel MO3 having source and drain regions of n-type doped polycrystalline silicon film, It is used for the negative characteristic region of the U-shaped characteristics peculiar to silicon thin film transistors, and operates essentially as a P-channel MO3.

[Function] In general, n-channel thin film transistors exhibit a unique U-shaped characteristic in which drain current increases as the negative gate voltage increases. The cause of this U-shaped characteristic has not been investigated in detail, but since the jump characteristic in the negative region corresponds to the off-state current, attempts have been made to reduce the off-state current by adopting an offset structure, etc. There is. However, the present inventor has discovered that when an n-channel thin film transistor is operated in the negative region of this U-shaped characteristic, a substantial P-channel MO
I found that it functions equally well as 3.

Therefore, even if a structure in which an n-channel thin film transistor is formed on the common gate electrode of the drive transistors is adopted, the n-channel thin film transistor operates in the same manner as the p-type load MO3. By using an n-channel thin film transistor as the load MO3, the n-type doped drain region of this n-channel thin film transistor and the n-type doped region of the drive transistor are
It has the same conductivity type as the drain region. Therefore, it is possible to connect the polycrystalline silicon drain film directly to the bulk silicon n-type drain region, thereby simplifying the manufacturing process and reducing the dimensions of the connection portion. Furthermore, since both drain regions are in direct contact, no diode characteristics occur at the junction of both drains, and good ohmic contact can be obtained.

〔Example〕

Next, embodiments of the present invention will be described based on the accompanying drawings.

FIG. 1 is a circuit diagram showing the circuit configuration of a CMOS memory cell according to an embodiment of the present invention.

The circuit configuration of this embodiment consists of a pair of CMOS inverters 1
. However, each C
The MOS inverter 1゜2 has a power supply voltage (■., Vs
s) consists of an n-channel MO3 drive transistor TINI'I'zN and n-channel thin film transistor load transistors TIN', T, , ', which are connected in series between them. That is, the load transistors TIN', T
tH' is not a p-channel but an n-channel thin film transistor.

Such an n-channel drive transistor T,N.

T ZN and n-channel load transistor T IN' +
As shown in FIG. 2, the irregular inverter structure made of T2O is a structure (joint structure) in which thin film transistors are stacked on top of a drive transistor. That is,
Inverter n-channel drive transistors T, , T,
, is a common gate electrode 12 of n-doped polycrystalline silicon formed via a gate insulating film 11 on the main surface of a P-type bulk silicon single crystal 10, and a self-line with this gate electrode 12 and sidewall 13 as a mask. It has an n-type source region 14' formed and an n-type drain region 15' having an LDD structure. In addition, the load transistor T,,', T2,4' of the n-channel thin film transistor
The shared gate electrode 12 and the interlayer insulating film 16 formed thereon are used as gate insulating films, and the second layer polycrystalline silicon channel region 17 formed on the glabellar insulating film 16 is used as a gate insulating film.
and a source region 18' and a drain region 19' in which a second layer of polycrystalline silicon is doped with n-type. The drain regions 19' of the load transistors TIN', TzH' and the drive transistors TI, T2. The connection structure of the drain region 15' is directly connected to the contact hole 23.
Conductive contact is made through the .

FIG. 3 is a graph showing the gate voltage versus drain current characteristics of an n-channel thin film transistor with a channel thickness of approximately 300 mm formed by a low temperature (600° C. or less) process. Although there are variations depending on the manufacturing process, the characteristic curve when the drain voltage is 4V is shown. Polycrystalline silicon gates generally exhibit a unique U-shaped characteristic, that is, a negative region jump characteristic in which the drain current (leakage current or off-state current) increases as the negative gate voltage increases.

This leakage current is said to be mainly caused by re-emission of carriers via traps at grain boundaries, but the details have not been investigated. Conventionally, in order to reduce this bounce characteristic, measures have been taken to reduce the trap density at grain boundaries by adopting an offset structure or applying heat treatment after the growth of amorphous silicon. However, in this embodiment, this U-shaped characteristic is actively utilized to operate the n-channel thin film transistor T IN' l TAN' as a P-channel transistor.

In a structure in which an n-channel thin film transistor T IN' l TzN' is formed instead of the conventional P-channel thin film transistor, as shown in FIG.
A structure can be obtained in which the doped drain region 19' is in conductive contact with the bulk silicon drain region 15.

In other words, the contact portion 2 of the first layer of polycrystalline silicon shown in FIG.
0 intermediary is not required.

Therefore, not only the process is simplified, but also the contact part 20
Also, since the area occupied by the sidewall 13 is eliminated, the cell area can be reduced. Furthermore, contact resistance is reduced and ohmic contact is improved.

Next, a method of manufacturing the above inverter structure will be explained.

First, as shown in FIG. 4A, Lacos (
After forming a local oxide film 21, gate oxidation is performed to form a thin gate insulating film 11. Next, a first layer of polycrystalline silicon film is formed using the CVD method, and after diffusing phosphorus,
Unnecessary polycrystalline silicon is removed leaving the gate electrode 12. Then, phosphorus ions are implanted using the gate electrode 12 as a mask, and a low concentration n-type source region 14' and drain region 15' are formed by self-alignment.

Next, as shown in FIG. 4(B), a side wall 13 is provided on the side surface of the gate electrode 12, and then phosphorus ions are implanted to form a highly concentrated source region 14' and drain region 15'. . This results in an LDD structure.

Next, as shown in FIG. 4C, a glabellar insulating film that will become the gate insulating film 16 of the thin film transistor is formed by CVD, and a contact hole 23 is formed by opening a window directly above the drain region 15'. .

Next, as shown in FIG. 4D, a second layer of polycrystalline silicon film, which is to become the channel region 17, is deposited on the glabella insulating film by CVD. As a result, the contact hole 23
The second layer of polycrystalline silicon film is connected to the drain region 15 through
′.

Next, as shown in FIG. 4E, after covering the second layer of polycrystalline silicon directly above the gate electrode 16 with a mask 24 such as photoresist, phosphorous ions are implanted to form a highly concentrated n-type doped layer. source region 18' and drain region 19'
form. Note that after this, a second layer insulating film, wiring, etc. are formed.

Compared to the conventional process, the structure shown in FIG. 6 requires photo-etching of the silicon oxide film on the drain region 15 and photo-etching of the interlayer insulating film on the connection part 20, but in this example, bulk silicon is required. It is sufficient to photo-etch the upper silicon oxide film and the interlayer insulating film all at once, and it is possible to reduce the number of photo-etching processes for forming the connection portion.

It goes without saying that the above MOS inverter structure is applicable not only to memory cells but also to semiconductor devices having inverter circuits.

〔Effect of the invention〕

As explained above, the present invention is applicable to a semiconductor device having a MOS inverter such as a memory cell.
Among the inverters, the load MO3 is formed as an n-channel thin film transistor on the upper part of the bulk silicon, and the negative region of the n-channel thin film transistor is used as the operating region, so that the following effects are achieved.

That is, an n-channel thin film transistor utilizes its U-shaped characteristic to essentially operate as a p-channel transistor in its negative region, but the drain region of an n-channel thin film transistor in a joint MO3 structure is n
Therefore, this drain region and the n-type drain region of the driving MO3 have the same conductivity type. Therefore, since it is possible to realize a structure in which both drain regions are brought into direct conductive contact, the area occupied by the connection structure can be reduced, and the cell area can be reduced. The miniaturization process that uses the LDD structure eliminates the formation of unnecessary sidewalls at the connection parts.
Accordingly, the cell can be reduced in size. Since the connection portion of the first layer of polycrystalline silicon as in the conventional method is not required, the photo-etching process can be reduced and the process can be simplified. Furthermore, since both drain regions are in direct contact with each other, good ohmic contact can be obtained without having diode characteristics.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing the circuit configuration of a CMOS memory cell according to an embodiment of the present invention. FIG. 2 is a sectional view showing the inverter structure in the same embodiment. FIG. 3 is a graph showing the gate voltage versus drain current characteristics of an n-channel thin film transistor with a channel thickness of about 300 mm formed by a low temperature (600'C or less) process. FIGS. 4(A) to 4(E) are process cross-sectional views showing the manufacturing process of the same structure. FIG. 5 is a circuit diagram showing the circuit configuration of a conventional CMOS memory cell. FIG. 6 is a sectional view showing the inverter structure in the conventional example. [Explanation of symbols] 1.2...Inverter 3...Flip-flop 5.6...Transfer gate 4...Address line BIT, er...Focus line T,..., T, N'... ...Load transistors T, N, T, N of n-channel thin film transistors...Drive transistor 10 of n-channel MO3...P-type bulk silicon single crystal 11...Gate insulating film 12...Common gate electrode 13... ... Sidewall 14'... Source region 15' in bulk silicon...
- Drain region 16 in bulk silicon...Gate insulating film 17 of thin film transistor...Channel region 18' of thin film transistor...Source region 19' of thin film transistor...Drain region 21 of thin film transistor...
...LOCO3 22...Second interlayer insulating film 23...Contact hole and above Applicant Seiko Epson Corporation Representative Patent Attorney Yama 1) Minoru 1 Figure 2 Figure 3 Figure 4

Claims (2)

[Claims] (1) In a memory cell having a flop-flop formed by loop-connecting a pair of MOS inverters, the MO
The S inverter consists of an n-channel drive transistor formed in bulk silicon below a shared gate electrode, and a load transistor that is an n-channel thin film transistor made of polycrystalline silicon formed above the shared gate electrode. A memory cell characterized in that the operating region of the transistor is a negative region of its U-shaped characteristic. (2) A semiconductor device having a MOS inverter,
The drive transistor as an element of the MOS inverter is an n-channel drive transistor formed in bulk silicon, and the load transistor as an element of the MOS inverter is an n-channel thin film transistor formed on the bulk silicon. A semiconductor device having a MOS inverter characterized in that its operating region is a negative region of its U-shaped characteristic.