JPS61129852A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS61129852A
JPS61129852A JP25257384A JP25257384A JPS61129852A JP S61129852 A JPS61129852 A JP S61129852A JP 25257384 A JP25257384 A JP 25257384A JP 25257384 A JP25257384 A JP 25257384A JP S61129852 A JPS61129852 A JP S61129852A
Authority
JP
Japan
Prior art keywords
drain
polycrystalline
source
semiconductor device
fet
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP25257384A
Other languages
Japanese (ja)
Other versions
JPH079972B2 (en
Inventor
Yasutaka Nakasaki
中崎　泰貴
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP25257384A priority Critical patent/JPH079972B2/en
Publication of JPS61129852A publication Critical patent/JPS61129852A/en
Publication of JPH079972B2 publication Critical patent/JPH079972B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0688—Integrated circuits having a three-dimensional layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To contrive to increase the integration by reducing margins to positional shifts, by a method wherein contact holes to make electrical contacts between the drain or source of a FET and wirings are bored through the polycrystalline Si forming the upper MOSFET. CONSTITUTION:The polycrystalline Si of the upper MOSFET if opened through in order that the source or drain of a FET on the Si substrate and the source or drain of a FET formed thereon make electrical contacts with a wiring 601 which is a constituent of the title device. The electrical contact of this polycrystalline Si with the wiring is made on the side surface of the aperture of the polycrystalline Si. This manner enables the semiconductors of high integration degree to be obtained with the need of little margin to positional shift.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、半導体装置に関し、その改良に関す条、特に
本発明は、８＜基板上のＭＯＥｉＦＩＴ上に更に、多結
晶Ｓｉ又はその前結晶膜によるＭＯａｙｍτを集積した
半導体装置の改良に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device and its improvement. This invention relates to improvements in semiconductor devices that integrate MOaymτ using films.

〔従来の技術〕[Conventional technology]

本発明の関する素子構造の１部断面ｆｔ第１図及び第２
図に示す。Partial cross-section ft of the device structure related to the present invention FIGS. 1 and 2
As shown in the figure.

１０１はａ４基板で１０４のソース・ドレイン。101 is an A4 board and 104 is a source/drain.

１０８のゲートで通常のＭＯ１ｉ］ＦＩＴを示し、１０
７．１０８で多結晶８（によるＦＦＩＴを示す。It shows the normal MO1i]FIT with gates of 108 and 10
7.108 shows the FFIT with polycrystalline 8 (.

１０７はソース・ドレインで１０８が伝導領域である。107 is a source/drain, and 108 is a conduction region.

この例では、ゲートを１０８で共通にしている。共通に
しない例をｗＸｚ図に示し、多結晶ＳｉによるＦ］Ｉｆ
Ｔのゲートは２０９である。この時、該集積回路を構成
する一要紫である配線材は、第８図、第４図の如く配線
される。配線材は３０１．４０１で示す、この例は、上
下のＦｌ！！Ｔのドレインを結線した例で、９８図の例
の上部から見た平面図を第６図に示す。In this example, 108 gates are used in common. The wXz diagram shows an example in which they are not common.
The gate of T is 209. At this time, the wiring material, which is mainly purple, constituting the integrated circuit is wired as shown in FIGS. 8 and 4. The wiring materials are shown as 301.401. In this example, the upper and lower Fl! ! FIG. 6 shows a plan view from above of the example shown in FIG. 98, in which the drain of T is connected.

各部は第１図の各部と同一番号で示す。Each part is indicated by the same number as each part in FIG.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

配線材との電気的接触をとるための開孔穴６０１は、１
０８と１０４の両方に配線材を接触させるために、大き
くなるとともに、位置ズレを考慮するための余裕も大き
くなる０本発明はかかる問題点を解決するものである。The opening hole 601 for making electrical contact with the wiring material is 1
Since the wiring material is brought into contact with both 08 and 104, the size increases and the margin for considering positional deviation also increases.The present invention solves this problem.

〔問題点を解決するための手段〕[Means for solving problems]

本発明では、配線材との電気的接触をとるためのコンタ
クト開孔を該上部ＭＯ８ＦＥＴを形成する多結晶シリコ
ンを貫通して開孔するもので、該多結晶シリコンと配線
材との電気的接触を、該多結晶シリコンの開孔部側面で
とるものである。In the present invention, a contact hole for making electrical contact with the wiring material is formed through the polycrystalline silicon forming the upper MO8FET, and electrical contact between the polycrystalline silicon and the wiring material is made. is taken at the side surface of the opening in the polycrystalline silicon.

〔実施例〕〔Example〕

第６図、第７図に実施例を示す、開孔７０１を６０４の
多結晶シリコン層を貫通してｇ４基板の拡散＃６０２１
で開けたものであり、配線材６０１と多結晶Ｅ３ｓ６０
４の電気的接触を、６０４の開孔側面でとるものである
。An example is shown in FIG. 6 and FIG.
It was opened with wiring material 601 and polycrystalline E3s60.
4 is made on the side surface of the opening 604.

〔発明の効果〕〔Effect of the invention〕

第６図と第７図を比較すればわかるように、第７図の開
孔は、６０４上に開孔するに、その大きさは、加工が可
能な限り小さくてもよく、また、その位置ズレに対する
余裕も殆ど必要ない。したがってより高い集積度の半導
体装置を提供できる。As can be seen by comparing FIG. 6 and FIG. 7, the hole in FIG. There is almost no need for any margin for misalignment. Therefore, a semiconductor device with a higher degree of integration can be provided.

【図面の簡単な説明】[Brief explanation of the drawing]

第２１図、第２図は本発明の関する素子構造を示す図。 第８図、第４図、第６図は従来例を示す図。 第６図、第７図社本発明の実施例を示す図。 以　　　上 FIG. 21 and FIG. 2 are diagrams showing element structures related to the present invention. FIG. 8, FIG. 4, and FIG. 6 are diagrams showing conventional examples. Figures 6 and 7 are diagrams showing embodiments of the present invention. that's all

Claims (1)

【特許請求の範囲】[Claims] 　Ｓｉ基板上に複数個のＭＯＳＦＥＴを集積した半導体
装置であり、該ＭＯＳＦＥＴの上に、更に多結晶シリコ
ンやその前結晶膜を電気伝導領域とするＭＯＳＦＥＴを
集積して構成される半導体装置に於いて、該基板上のＦ
ＥＴのソース又はドレインと、更にその上に形成される
ＦＥＴのソース又はドレインと、該半導体装置の構成要
素である配線材との電気的接触をとるためのコンタクト
孔を、該上部ＭＯＳＦＥＴを形成する多結晶シリコンを
貫通して開孔することにより形成された半導体装置。A semiconductor device in which a plurality of MOSFETs are integrated on a Si substrate, and a MOSFET in which polycrystalline silicon or a pre-crystalline film is used as an electrical conduction region is further integrated on the MOSFET. , F on the substrate
A contact hole is formed in the upper MOSFET for making electrical contact between the source or drain of the ET, the source or drain of the FET formed thereon, and a wiring material that is a component of the semiconductor device. A semiconductor device formed by drilling holes through polycrystalline silicon.
JP25257384A 1984-11-28 1984-11-28 Semiconductor device Expired - Lifetime JPH079972B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP25257384A JPH079972B2 (en) 1984-11-28 1984-11-28 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP25257384A JPH079972B2 (en) 1984-11-28 1984-11-28 Semiconductor device

Publications (2)

Publication Number Publication Date
JPS61129852A true JPS61129852A (en) 1986-06-17
JPH079972B2 JPH079972B2 (en) 1995-02-01

Family

ID=17239255

Family Applications (1)

Application Number Title Priority Date Filing Date
JP25257384A Expired - Lifetime JPH079972B2 (en) 1984-11-28 1984-11-28 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH079972B2 (en)

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62190744A (en) * 1986-02-18 1987-08-20 Agency Of Ind Science & Technol Vertical wiring structure
JPS62203359A (en) * 1986-03-03 1987-09-08 Mitsubishi Electric Corp Laminated semiconductor device
JPS63169755A (en) * 1987-01-07 1988-07-13 Agency Of Ind Science & Technol Manufacture of laminating type semiconductor device
JPS6450444A (en) * 1987-08-21 1989-02-27 Agency Ind Science Techn Manufacture of semiconductor device
JPH0391243A (en) * 1989-09-01 1991-04-16 Matsushita Electron Corp Manufacture of semiconductor device
JPH04226081A (en) * 1990-04-27 1992-08-14 Nec Corp Semiconductor device
JPH04252052A (en) * 1991-01-28 1992-09-08 Nec Corp Wiring formation method for active layer laminated element
WO2012056663A1 (en) * 2010-10-28 2012-05-03 シャープ株式会社 Circuit board, method for manufacturing same and display device

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62190744A (en) * 1986-02-18 1987-08-20 Agency Of Ind Science & Technol Vertical wiring structure
JPS62203359A (en) * 1986-03-03 1987-09-08 Mitsubishi Electric Corp Laminated semiconductor device
JPS63169755A (en) * 1987-01-07 1988-07-13 Agency Of Ind Science & Technol Manufacture of laminating type semiconductor device
JPS6450444A (en) * 1987-08-21 1989-02-27 Agency Ind Science Techn Manufacture of semiconductor device
JPH0391243A (en) * 1989-09-01 1991-04-16 Matsushita Electron Corp Manufacture of semiconductor device
JPH04226081A (en) * 1990-04-27 1992-08-14 Nec Corp Semiconductor device
JPH04252052A (en) * 1991-01-28 1992-09-08 Nec Corp Wiring formation method for active layer laminated element
WO2012056663A1 (en) * 2010-10-28 2012-05-03 シャープ株式会社 Circuit board, method for manufacturing same and display device

Also Published As

Publication number Publication date
JPH079972B2 (en) 1995-02-01

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EXPY Cancellation because of completion of term