JPH0222868A - Insulated-gate field-effect transistor - Google Patents

Abstract

PURPOSE:To obtain a transistor where a required ON current flows in a comparatively small area on a semiconductor substrate by a method wherein a gate electrode of an insulated-gate field-effect transistor is installed in a groove part inside the semiconductor substrate in order to make an effective cross-sectional area of a conducting channel large as compared with an apparent gate width and to reduce an ON resistance. CONSTITUTION:A conductive layer 3 corresponds to a gate electrode; a source region 1s and a drain region 1d as N-type diffusion layers are installed on both sides of the layer. A groove 7 is formed in a part sandwiched between the source region 1s and the drain region 1d; the surface of the groove 7 is coated with a gate insulating film 2 and is filled with a conductive layer 3 composed of polycrystalline silicon. Accordingly, when a positive voltage is applied to the conductive layer 3, an N-channel 6 is formed inside a P-type semiconductor substrate in its immediate neighborhood, and reaches a periphery of the groove; accordingly, a channel length is increased as compared with a case where the groove does not exist.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to insulated gate field effect transistors, and in particular to the structure of MOS transistors.

[Conventional technology]

Conventional MO3) transistors generally have a structure in which an impurity diffusion layer serving as a source region and a drain region, and a gate region located between the two are arranged in a plane on a semiconductor substrate surface.

[Problem to be solved by the invention]

In the conventional MOS transistor described above, the gate part has a structure in which an insulating film and a conductive material as an electrode are simply stacked on the surface of a semiconductor substrate, so the conduction channel formed under the gate electrode when the MOS transistor is turned on is
The layer is formed only in a layer extremely close to the surface of the semiconductor substrate, which is the range covered by the electric field from the voltage applied to the gate electrode. Therefore, in this structure, the cross-sectional area of the conduction channel under the gate electrode is not very large, so it is difficult to reduce the on-resistance of the MOS transistor, and the only way to achieve this is to increase the length of the gate electrode. However, there was a drawback in that it became a constraint on increasing the degree of integration.

[Means to solve the problem]

The insulated gate field effect transistor of the present invention includes a source region and a drain region comprising a second conductivity type diffusion layer selectively provided in a first conductivity type semiconductor substrate, and a portion sandwiched between the source region and the drain region. The semiconductor device includes a gate insulating film on the surface of the groove provided, and a gate electrode made of a conductive layer filling the groove with the gate insulating film interposed therebetween.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

1 shows a first embodiment of the present invention, FIG. 1(a) is a plan view of the semiconductor substrate surface viewed from above, and FIG. 1(b) is a first embodiment of the invention.
Figure 1 (C) is a sectional view taken along the line xx' of Figure
It is a YY' line sectional view of a).

Conductive M! J3 corresponds to a gate electrode, and a source region IS and a drain region 1d, which are N expansion diffusion layers, are provided on both sides of J3. A groove 7 is provided in a portion sandwiched between the source region IS and the drain region 1d, and the surface of the groove 7 is covered with a gate insulating film 2, and a conductive layer 3 made of polycrystalline silicon.
It is filled with Therefore, when a positive voltage is applied to the conductive layer 3, an N channel 6 is formed in the P-type semiconductor substrate immediately adjacent to the conductive layer 3, and this also extends around the groove, so that the channel length increases compared to the case without the groove. Note that this structure can be easily realized by forming grooves in advance by a photoresist process and an etching process before the usual gate electrode forming process. Note that the source electrode and drain electrode are not shown for convenience.

FIG. 2 is a plan view of a second embodiment of the invention. In this embodiment, since grooves serving as gate electrodes are provided at both ends, there is an advantage that the channel length of the N channel when the MOS transistor is conductive is further increased.

〔Effect of the invention〕

As explained above, the present invention makes the gate electrode structure of an insulated gate field effect transistor intricate inside the semiconductor substrate (provided in the groove), thereby reducing the range in which the field effect of the gate voltage extends inside the semiconductor substrate. This has the effect of increasing the effective cross-sectional area of the conduction channel compared to the apparently planar gate width and reducing the on-resistance. Therefore, when it is necessary to configure a drive circuit that requires a large current, the present invention can be used to realize a transistor that can flow the required on-current in a relatively small area on a semiconductor substrate. When used in integrated circuits, the degree of integration can be improved.

[Brief explanation of the drawing]

FIG. 1(a) is a plan view showing the first embodiment of the present invention, and FIGS. 1(b) and (C) are xx' in FIG. 1(a), respectively.
FIG. 2 is a plan view showing a second embodiment of the present invention. IS...source region, 1d...drain region, 2.
... Gate insulating film, 3... Conductive layer, 4... P-type semiconductor substrate, 5... Field oxide film, 6... N channel, 7.7-1.7-2... Groove . Monthly 1st figure

Claims (1)

[Claims] a source region and a drain region made of a second conductivity type diffusion layer selectively provided on a first conductivity type semiconductor substrate; and a gate insulating film on a groove surface provided in a portion sandwiched between the source region and the drain region. , and a gate electrode made of a conductive layer filling the groove with the gate insulating film interposed therebetween.