JPH01111378A - Vertical mosfet - Google Patents
Vertical mosfetInfo
- Publication number
- JPH01111378A JPH01111378A JP62269844A JP26984487A JPH01111378A JP H01111378 A JPH01111378 A JP H01111378A JP 62269844 A JP62269844 A JP 62269844A JP 26984487 A JP26984487 A JP 26984487A JP H01111378 A JPH01111378 A JP H01111378A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- type
- semiconductor layer
- region
- gate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims abstract description 41
- 239000010410 layer Substances 0.000 description 24
- 108010075750 P-Type Calcium Channels Proteins 0.000 description 5
- 239000011229 interlayer Substances 0.000 description 4
- 239000000758 substrate Substances 0.000 description 4
- 230000015556 catabolic process Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
- H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
- H01L29/0873—Drain regions
- H01L29/0878—Impurity concentration or distribution
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
- H01L29/42376—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the length or the sectional shape
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、ゲート・ドレイン間容量の小さい縦型ＭＯＳ
ＦＥＴ に関するものである。[Detailed Description of the Invention] [Industrial Application Field] The present invention is directed to a vertical MOS with small gate-drain capacitance.
It is related to FET.
第３図は従来の縦型ＭＯＳＦＥＴの構造を示す断面図で
ある。、同図において、低比折抗のＮ＋基板１と比較的
比抵抗の高いＮ型エピタキシャル層２を有し１ゲート絶
縁膜３の上に形成名れたポリシリコンよりなるゲート電
極４をマスクとしてＰ型チャネル形成領域５およびＮ＋
ソース領域６が拡散によって形成名れ、ゲート電極４の
表面に層間絶縁膜７を形成し、Ｐ型チャネル形成頌域５
およびＮ＋ソース領域６に接するようにソース電極８が
形成名れ Ｎ＋基板１の裏面にドレイン電極９が形成名
れている。FIG. 3 is a sectional view showing the structure of a conventional vertical MOSFET. In the figure, a gate electrode 4 made of polysilicon, which is formed on a gate insulating film 3 and has an N+ substrate 1 with a low specific resistance and an N-type epitaxial layer 2 with a relatively high resistivity, is used as a mask. P-type channel forming region 5 and N+
A source region 6 is formed by diffusion, an interlayer insulating film 7 is formed on the surface of the gate electrode 4, and a P-type channel forming region 5 is formed.
A source electrode 8 is formed in contact with the N+ source region 6, and a drain electrode 9 is formed on the back surface of the N+ substrate 1.
また、他の縦型ＭＯＳＦＥＴ として第４図に示すよう
に第３図の従来の縦型ＭＯ８Ｆ’ＥＴにおいてＮ！エピ
タキシャル層層上上ゲート電極４の一部を除去し、ゲー
ト電極４とドレイン電極９との重々シ面積を低減し、ゲ
ート・ドレイン間容量の低減を図る構造が提案されてい
る。As another vertical MOSFET, as shown in FIG. 4, in the conventional vertical MO8F'ET shown in FIG. 3, N! A structure has been proposed in which a portion of the upper gate electrode 4 on the epitaxial layer is removed to reduce the area between the gate electrode 4 and the drain electrode 9, thereby reducing the gate-drain capacitance.
しかしながら、第３図に示す縦型ＭＯＳＦＥＴは、ゲー
ト絶縁膜３を介してＮ型エピタキシャル層２とゲート電
極４とが重なる面積が広く、ゲート・ドレイン間容量が
大きくなるという問題があった。However, the vertical MOSFET shown in FIG. 3 has a problem in that the area where the N-type epitaxial layer 2 and the gate electrode 4 overlap with each other via the gate insulating film 3 is large, resulting in a large gate-drain capacitance.
また、第４図に示す縦型ＭＯＳＦＥＴ・は第３図の場合
とは異なり、ゲ、−）−に極４に正の電圧を印加したオ
ン状態で、除去されたゲート電極４下のＮ型エピタキシ
ャル層２０表面に電子よシなる蓄積店が形成名れないた
め、素子のオン抵抗増加を抑制するには、ゲート電極４
の除去幅Ｗ１を一定以上には大きくできず、ゲート・ド
レイン間容量を大幅には低減することはできないという
問題があった。Furthermore, unlike the case shown in FIG. 3, the vertical MOSFET shown in FIG. Since no storage stores such as electrons are formed on the surface of the epitaxial layer 20, in order to suppress an increase in the on-resistance of the device, it is necessary to
There is a problem in that the removal width W1 cannot be increased beyond a certain level, and the gate-drain capacitance cannot be significantly reduced.
本発明の目的は、従来の縦型ＭＯＳＦＥＴ における
上述の問題点を改善し、オン抵抗の増加を伴うことなく
、ゲート・ドレイン間容量を低減できる縦型ＭＯＳＦＥ
Ｔ を提供することにある。The purpose of the present invention is to improve the above-mentioned problems in conventional vertical MOSFETs, and to provide a vertical MOSFET that can reduce gate-drain capacitance without increasing on-resistance.
The goal is to provide T.
本発明による縦型ＭＯＳＦＥＴは、第１導電型の第１の
半導体層上に形成名れた第１導電型でかつ第１の半導体
層に比して高い比抵抗の第２の半導体層の表面において
第１の絶縁層を介して第１の導電性層が重なる領域の第
１の導電性層を一部を除去し、かつ第２の半導体層の表
面近傍に第１導電型でかつ第２の半導体層に比して低い
比抵抗の第３の半導体領域もしくは第３の半導体領域と
第２導電型の第４の半導体領域とを形成したものである
。In the vertical MOSFET according to the present invention, a surface of a second semiconductor layer of the first conductivity type and having a higher specific resistance than the first semiconductor layer is formed on the first semiconductor layer of the first conductivity type. In the step, a part of the first conductive layer is removed in a region where the first conductive layer overlaps with the first insulating layer interposed therebetween, and a semiconductor layer of the first conductivity type and a second conductive layer is added near the surface of the second semiconductor layer. A third semiconductor region having a resistivity lower than that of the semiconductor layer, or a third semiconductor region and a fourth semiconductor region of a second conductivity type are formed.
本発明においては、第３の半導体領域によってオン状態
における電流路が確保される。In the present invention, the third semiconductor region ensures a current path in the on state.
第１図は本発明による縦型ＭＯＳＦＥＴ の一実施例を
示す断面図である。同図において、１はＮ＋基板、２は
Ｎ世エピタキシャル層、３はゲート絶・ 縁膜、４は
ゲート電極、５はＰ型チャネル形成領域、６はＮ＋ソー
ス領域、Ｔは層間絶縁膜、８はソース電極、９はドレイ
ン電極、１０はＮ型エピタキシャル層２の表面において
ゲート絶縁膜３を介してゲート電極４が重なる領域のゲ
ート電極４を一部除去し、さらに除去したゲート電極を
マスクとしてＮ型エピタキシャル層２の表面近傍に形成
名れたＮ型半導体領域である。FIG. 1 is a sectional view showing an embodiment of a vertical MOSFET according to the present invention. In the figure, 1 is an N+ substrate, 2 is an N-series epitaxial layer, 3 is a gate insulating film, 4 is a gate electrode, 5 is a P-type channel forming region, 6 is an N+ source region, T is an interlayer insulating film, 8 10 is a source electrode, 9 is a drain electrode, and 10 is a portion of the surface of the N-type epitaxial layer 2 where the gate electrode 4 overlaps with the gate insulating film 3, and the removed gate electrode is used as a mask. This is an N-type semiconductor region formed near the surface of the N-type epitaxial layer 2.
このような構成によれば、Ｎ型エピタキシャル層２の表
面に形成名れたＮ型半導体領域１０によってオン状態に
おける電流路が確保され、ゲート電極４の除去幅Ｗ２を
第４図の従来の縦型ＭＯＳＦＥＴの除去幅Ｗｌ ようも
太きく （Ｗ２ ＞ Ｗｔ ）することができ、ゲート
・ドレイン間容量を大幅に低減することが可能となる。According to such a structure, a current path in the on state is secured by the N-type semiconductor region 10 formed on the surface of the N-type epitaxial layer 2, and the removal width W2 of the gate electrode 4 can be changed from the conventional vertical direction shown in FIG. The removal width Wl of the type MOSFET can be increased (W2 > Wt), and the gate-drain capacitance can be significantly reduced.
第２図は本発明による縦型ＭＯＳＦＥＴの他の実施例を
示す断面図である。同図において、１はＮ＋基板、２は
Ｎ型エピタキシャル層、３はゲート絶縁膜、４はゲート
電極、５はＰ型チャネル形成領域、６はＮ＋ソース領域
、Ｔは層間絶縁膜、８はソース電極、９はドレイン電極
、１０はＮ型半導体領域、１１はＮ型半導体領域１０内
に形成名れたＰ型半導体領域である。FIG. 2 is a sectional view showing another embodiment of the vertical MOSFET according to the present invention. In the figure, 1 is an N+ substrate, 2 is an N-type epitaxial layer, 3 is a gate insulating film, 4 is a gate electrode, 5 is a P-type channel forming region, 6 is an N+ source region, T is an interlayer insulating film, and 8 is a source 9 is a drain electrode, 10 is an N-type semiconductor region, and 11 is a P-type semiconductor region formed within the N-type semiconductor region 10.
このような構成によれば、Ｎ型エピタキシャル層２内は
形成し？ｃＮ型半導体領域１０によってオン状態におけ
る電流路が確保されるため、ゲート電極４の除去幅Ｗ２
を第４図の従来の縦型ＭＯＳＦＥＴの除去幅Ｗ、 より
も大きくすることができ、ゲート・ドレイン間容量を大
幅に低減することが可能となる。さらに特に低耐圧の縦
型ＭＯＳＦＥＴにおいては、ゲート電極４を零あるいは
負の電圧を加え、ドレイン電極９にソース電極８に対し
て正の電圧を加えたオフ状態において、Ｎ型エピタキシ
ャル層２内に延びる空乏層幅が小さいため、Ｎ型エピタ
キシャル層２表面にドレイン電圧の大部分が加わ夛、こ
の部分で降伏を生じる可能性があるが、Ｐ型半導体領域
１１の形成によってＮ型エピタキシャル層２表面にドレ
イン電圧の大部分が加わることが避けられ、素子耐圧を
高く保つことが可能となる。According to such a configuration, the inside of the N-type epitaxial layer 2 is not formed. Since the cN-type semiconductor region 10 ensures a current path in the on state, the removal width W2 of the gate electrode 4 is
can be made larger than the removal width W of the conventional vertical MOSFET shown in FIG. 4, making it possible to significantly reduce the gate-drain capacitance. Furthermore, especially in a low-voltage vertical MOSFET, in an off state in which a zero or negative voltage is applied to the gate electrode 4 and a positive voltage is applied to the drain electrode 9 with respect to the source electrode 8, the N-type epitaxial layer 2 is Since the extending depletion layer width is small, most of the drain voltage is applied to the surface of the N-type epitaxial layer 2, and breakdown may occur in this area. This prevents most of the drain voltage from being applied to the device, making it possible to maintain a high device breakdown voltage.
以上説明したように本発明によれば、オン抵抗。 As explained above, according to the present invention, the on-resistance.
耐圧は従来の縦型ＭＯ８Ｆ’ＥＴとほぼ同等に保ち、か
つゲート・ドレイン間容量を大幅に低減できる。The breakdown voltage can be kept almost the same as that of conventional vertical MO8F'ET, and the gate-drain capacitance can be significantly reduced.
したがって、スイッチング時間の短縮およびスイッチン
グ損失の低減が図れるので、小型で高効率であることが
袂求されるスイッチ／グミ源用の主スィッチ素子として
最適である。Therefore, it is possible to shorten the switching time and reduce switching loss, making it ideal as a main switch element for a switch/gummy source that is required to be small and highly efficient.
第１図は本発明による縦型ＭＯ８ＦｇＴの一実施例を示
す断面図、第２図は本発明による縦型ＭＯＳＦＥＴの他
の実施例を示す断面図、第３図および第４図は従来の縦
型ＭＯＳＦＥＴの断面図である。
１ ＊ ｅ ＠ ＩＩＮ＋基板、２ｅ ｅ ＊ ｅ Ｎ
型エピタキシャル層、３・・・・ゲート絶縁膜、４・・
・・ゲート電極、５・・・・Ｐ型チャネル形成領域、Ｇ
・・・・Ｎ＋ソース領域、７・・・・層間絶縁膜、８・
・・・ソース電極、９・φ・・ドレイン電極、１０・・
・・Ｎ型半導体領域、１１・・・・Ｐ型半導体領域。
特許出願人 日本電信電話株式会社FIG. 1 is a sectional view showing one embodiment of the vertical MOSFET according to the present invention, FIG. 2 is a sectional view showing another embodiment of the vertical MOSFET according to the present invention, and FIGS. FIG. 2 is a cross-sectional view of a type MOSFET. 1 * e @ IIN + board, 2e e * e N
type epitaxial layer, 3...gate insulating film, 4...
...Gate electrode, 5...P-type channel formation region, G
... N+ source region, 7... interlayer insulating film, 8.
・・・Source electrode, 9・φ・・Drain electrode, 10・・
...N-type semiconductor region, 11...P-type semiconductor region. Patent applicant Nippon Telegraph and Telephone Corporation
Claims (2)
体層上に形成名れた第１導電量でかつ前記第１の半導体
層に比して高い比抵抗の第２の半導体層とを有し、前記
第２の半導体層内に第１導電量とは逆のチャネル形成用
の第２導電型を有する第１の半導体領域と、第１導電型
の第２の半導体領域とがチャネルを形成すべく形成され
、前記チャネルおよび第２の半導体層の表面に第１の絶
縁層を介して第１の導電性層が形成され、前記第１の半
導体領域および第２の半導体領域に接して第２の導電性
層および第１の半導体層表面に第３の導電性層が形成さ
れた縦型ＭＯＳＦＥＴにおいて、前記第１の導電性層が
第１の絶縁層を介して第２の半導体層と重なる領域にお
いてその一部が除去され、かつ第２の半導体層内の表面
近傍に第１導電型でかつ第２の半導体層に比して低い比
抵抗の第３の半導体領域が形成されたことを特徴とする
縦型ＭＯＳＦＥＴ。(1) A first semiconductor layer of a first conductivity type, and a second semiconductor layer formed on the first semiconductor layer and having a first conductivity and a higher resistivity than the first semiconductor layer. a first semiconductor region having a second conductivity type for forming a channel opposite to the first conductivity in the second semiconductor layer; and a second semiconductor region of the first conductivity type. is formed to form a channel, a first conductive layer is formed on the surface of the channel and the second semiconductor layer via a first insulating layer, and the first conductive layer is formed on the surface of the channel and the second semiconductor layer, and In a vertical MOSFET in which a second conductive layer and a third conductive layer are formed on the surface of the first semiconductor layer in contact with a region, the first conductive layer is connected to the first conductive layer through the first insulating layer. A third semiconductor region having a first conductivity type and a resistivity lower than that of the second semiconductor layer is removed in a region overlapping with the second semiconductor layer, and is located near the surface of the second semiconductor layer. A vertical MOSFET characterized by being formed.
かつ第２の半導体層に比して低い比抵抗の第３の半導体
領域と第２導電型の第４の半導体領域とが形成されたこ
とを特徴とする特許請求の範囲第１項記載の縦型ＭＯＳ
ＦＥＴ。(2) A third semiconductor region of the first conductivity type and having a lower specific resistance than the second semiconductor layer and a fourth semiconductor region of the second conductivity type near the surface of the second semiconductor layer. The vertical MOS according to claim 1, characterized in that:
FET.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62269844A JPH01111378A (en) | 1987-10-26 | 1987-10-26 | Vertical mosfet |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62269844A JPH01111378A (en) | 1987-10-26 | 1987-10-26 | Vertical mosfet |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01111378A true JPH01111378A (en) | 1989-04-28 |
Family
ID=17477976
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62269844A Pending JPH01111378A (en) | 1987-10-26 | 1987-10-26 | Vertical mosfet |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01111378A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2004022693A (en) * | 2002-06-14 | 2004-01-22 | Toshiba Corp | Semiconductor device |
| JP2008004872A (en) * | 2006-06-26 | 2008-01-10 | Toshiba Corp | Semiconductor device |
| JP2009224811A (en) * | 2009-07-06 | 2009-10-01 | Toshiba Corp | Semiconductor device |
| US7851852B2 (en) | 2004-09-16 | 2010-12-14 | Semiconductor Components Industries, L.L.C. | Method of forming a low capacitance semiconductor device and structure therefor |
| CN109786465A (en) * | 2018-12-17 | 2019-05-21 | 重庆平伟实业股份有限公司 | Power semiconductor and its manufacturing method |
-
1987
- 1987-10-26 JP JP62269844A patent/JPH01111378A/en active Pending
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2004022693A (en) * | 2002-06-14 | 2004-01-22 | Toshiba Corp | Semiconductor device |
| JP4537646B2 (en) * | 2002-06-14 | 2010-09-01 | 株式会社東芝 | Semiconductor device |
| US7851852B2 (en) | 2004-09-16 | 2010-12-14 | Semiconductor Components Industries, L.L.C. | Method of forming a low capacitance semiconductor device and structure therefor |
| JP2008004872A (en) * | 2006-06-26 | 2008-01-10 | Toshiba Corp | Semiconductor device |
| JP2009224811A (en) * | 2009-07-06 | 2009-10-01 | Toshiba Corp | Semiconductor device |
| CN109786465A (en) * | 2018-12-17 | 2019-05-21 | 重庆平伟实业股份有限公司 | Power semiconductor and its manufacturing method |
| CN109786465B (en) * | 2018-12-17 | 2022-07-15 | 重庆平伟实业股份有限公司 | Power semiconductor device and method for manufacturing the same |
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