JP2001015742A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JP2001015742A JP2001015742A JP11186545A JP18654599A JP2001015742A JP 2001015742 A JP2001015742 A JP 2001015742A JP 11186545 A JP11186545 A JP 11186545A JP 18654599 A JP18654599 A JP 18654599A JP 2001015742 A JP2001015742 A JP 2001015742A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- drain
- conductivity type
- source
- semiconductor substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 67
- 239000000758 substrate Substances 0.000 claims abstract description 56
- 238000005468 ion implantation Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
- H01L29/7825—Lateral DMOS transistors, i.e. LDMOS transistors with trench gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
- H01L29/42376—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the length or the sectional shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は半導体装置に係り、
特に横型パワーＭＯＳＦＥＴに関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device,
In particular, it relates to a lateral power MOSFET.
【０００２】[0002]
【従来の技術】図７は従来の横型トレンチＭＯＳＦＥＴ
の断面図の一例である。Ｎ型半導体基板１０１表面に選
択的にＰ型ウェル層１０２が形成され、 Ｎ型半導体基
板１０１表面に選択的にＮ型ドレイン層１０３が形成さ
れ、 Ｐ型ウェル層１０２表面に選択的にＮ型ソース層
１０４が形成され、 Ｎ型ドレイン層１０３とＮ型ソー
ス層１０４の間には溝１０５がドレイン−ソース方向と
ほぼ平行に形成され、Ｎ型ドレイン層１０３とＮ型ソー
ス層１０４の間と溝１０５表面にはゲート絶縁膜１０５
が形成され、ゲート絶縁膜１０５上にゲート電極１０６
が形成され、Ｎ型ドレイン層１０３と電気的にコンタク
トするドレイン電極１０７が形成され、Ｎ型ソース層１
０４とＰ型ウェル層１０２とに電気的にコンタクトする
ソース電極１０８が形成されている。2. Description of the Related Art FIG. 7 shows a conventional lateral trench MOSFET.
1 is an example of a cross-sectional view of FIG. A P-type well layer 102 is selectively formed on the surface of the N-type semiconductor substrate 101, an N-type drain layer 103 is selectively formed on the surface of the N-type semiconductor substrate 101, and an N-type is selectively formed on the surface of the P-type well layer 102. A source layer 104 is formed. A groove 105 is formed between the N-type drain layer 103 and the N-type source layer 104 substantially in parallel with the drain-source direction. A gate insulating film 105 is formed on the surface of the groove 105.
Is formed, and a gate electrode 106 is formed on the gate insulating film 105.
Is formed, and a drain electrode 107 that is in electrical contact with the N-type drain layer 103 is formed.
A source electrode 108 is formed which is in electrical contact with the substrate 04 and the P-type well layer 102.
【０００３】また、図８は従来の横型トレンチＭＯＳＦ
ＥＴの断面図の一例である。Ｐ型半導体基板１１０表面
に選択的にＰ型ウェル層１０２が形成され、 Ｐ型ウェ
ル層１０２表面に選択的にＮ型ドレイン層１０３、Ｎ型
ソース層１０４が形成され、Ｎ型ドレイン層１０３とＮ
型ソース層１０４の間には溝１０５がドレイン−ソース
方向とほぼ平行に形成され、Ｎ型ドレイン層１０３とＮ
型ソース層１０４の間と溝１０５表面にはゲート絶縁膜
１０５が形成され、ゲート絶縁膜１０５上にゲート電極
１０６が形成され、Ｎ型ドレイン層１０３と電気的にコ
ンタクトするドレイン電極１０７が形成され、Ｎ型ソー
ス層１０４とＰ型ウェル層１０２とに電気的にコンタク
トするソース電極１０８が形成されている。FIG. 8 shows a conventional lateral trench MOSF.
It is an example of a sectional view of ET. A P-type well layer 102 is selectively formed on the surface of a P-type semiconductor substrate 110, and an N-type drain layer 103 and an N-type source layer 104 are selectively formed on the surface of the P-type well layer 102. N
A trench 105 is formed substantially parallel to the drain-source direction between the N-type drain layer 103 and the N-type drain layer 103.
A gate insulating film 105 is formed between the mold source layers 104 and on the surface of the groove 105, a gate electrode 106 is formed on the gate insulating film 105, and a drain electrode 107 that is in electrical contact with the N-type drain layer 103 is formed. , A source electrode 108 that electrically contacts the N-type source layer 104 and the P-type well layer 102 is formed.
【０００４】このような素子を大電流のスイッチング素
子として用いた場合、オン時の素子の抵抗を低く抑える
ことが重要であるが、このような素子は溝を形成し、溝
の側壁をチャネルとして用いているため、素子のオン抵
抗を低くすることができる。たとえば、図７の構造では
耐圧２５Ｖに対しオン抵抗２０ｍΩ・ｍｍ２、図８の構
造では耐圧１２Ｖに対し、オン抵抗１２ｍΩ・ｍｍ２が
可能である。しかしながら、Ｎ型ソース層と溝、ゲート
電極とがオーバーラップする必要があるため、素子長が
長くなる、すなわち素子面積が大きくなるという問題が
あった。When such an element is used as a high-current switching element, it is important to suppress the resistance of the element at the time of ON. However, such an element forms a groove and uses the side wall of the groove as a channel. Since it is used, the on-resistance of the element can be reduced. For example, in the structure of FIG. 7, the on-resistance is 20 mΩ · mm 2 for the withstand voltage of 25 V, and in the structure of FIG. 8, the on-resistance is 12 mΩ · mm 2 for the withstand voltage of 12 V. However, since the N-type source layer must overlap the trench and the gate electrode, there is a problem that the element length is increased, that is, the element area is increased.
【０００５】[0005]
【発明が解決しようとする課題】従来の素子ではオン抵
抗を小さくするためには素子面積が大きくなってしまう
という問題があった。In the conventional device, there is a problem that the device area becomes large in order to reduce the on-resistance.
【０００６】本発明はオン抵抗の小さいＭＯＳＦＥＴを
提供することを目的とする。An object of the present invention is to provide a MOSFET having a low on-resistance.
【０００７】[0007]
【課題を解決するための手段】前記課題を解決するた
め、本発明（請求項１）は、半導体基板と、前記半導体
基板表面に形成された第２導電型ウェル層と、この第２
導電型ウェル層と異なる前記半導体基板表面に選択的に
形成された第１導電型ドレイン層と、前記第２導電型ウ
ェル層表面に選択的に形成された第１導電型ソース層
と、前記第１導電型ドレイン層と前記第１導電型ソース
層の間の前記半導体基板表面に、ドレイン−ソース間方
向にほぼ平行な方向に形成された溝と、前記第１導電型
ドレイン層と前記第１導電型ソース層の間の前記半導体
基板表面および前記溝の表面に形成されたゲート絶縁膜
と、前記ゲート絶縁膜上に形成されたゲート電極と、前
記第２導電型ドレイン層に電気的にコンタクトするドレ
イン電極と、前記第２導電型ソース層と前記第１導電型
ウェル層に電気的にコンタクトするソース電極とを具備
し、前記溝のソース側端から前記ソース電極までの距離
が、前記半導体基板表面上の前記ゲート電極部分のソー
ス側端から前記ソース電極までの距離よりも短いことを
特徴とする半導体装置を提供する。In order to solve the above problems, the present invention (claim 1) provides a semiconductor substrate, a second conductivity type well layer formed on a surface of the semiconductor substrate,
A first conductivity type drain layer selectively formed on the semiconductor substrate surface different from the conductivity type well layer; a first conductivity type source layer selectively formed on the second conductivity type well layer surface; A groove formed in the surface of the semiconductor substrate between the drain layer of one conductivity type and the source layer of the first conductivity type in a direction substantially parallel to the direction between the drain and the source; A gate insulating film formed on the surface of the semiconductor substrate and the trench between conductive type source layers, a gate electrode formed on the gate insulating film, and an electrical contact with the second conductive type drain layer A drain electrode, and a source electrode electrically contacting the second conductivity type source layer and the first conductivity type well layer, wherein a distance from a source side end of the trench to the source electrode is the semiconductor. substrate To provide a semiconductor device, characterized in that shorter than the distance from the source side edge of the gate electrode portion on the surface to the source electrode.
【０００８】また、本発明（請求項２）は、半導体基板
と、前記半導体基板表面に形成された第２導電型ウェル
層と、この第２導電型ウェル層と異なる前記半導体基板
表面に選択的に形成された第１導電型ドレイン層と、前
記第２導電型ウェル層表面に選択的に形成された第１導
電型ソース層と、前記第１導電型ドレイン層と前記第１
導電型ソース層の間の前記半導体基板表面に、ドレイン
−ソース間方向にほぼ平行な方向に形成された溝と、前
記第１導電型ドレイン層と前記第１導電型ソース層の間
の前記半導体基板表面および前記溝の表面に形成された
ゲート絶縁膜と、前記ゲート絶縁膜上に形成されたゲー
ト電極と、前記第２導電型ドレイン層に電気的にコンタ
クトするドレイン電極と、前記第２導電型ソース層と前
記第１導電型ウェル層に電気的にコンタクトするソース
電極とを具備し、前記溝のドレイン側端から前記ドレイ
ン電極までの距離が、前記半導体基板表面上の前記ゲー
ト電極部分のドレイン側端から前記ドレイン電極までの
距離よりも短いことを特徴とする半導体装置を提供す
る。Further, the present invention (claim 2) provides a semiconductor substrate, a second conductivity type well layer formed on the semiconductor substrate surface, and a semiconductor substrate surface different from the second conductivity type well layer. A first conductivity type drain layer selectively formed on the surface of the second conductivity type well layer; a first conductivity type drain layer selectively formed on a surface of the second conductivity type well layer;
A groove formed in the surface of the semiconductor substrate between the conductive type source layers in a direction substantially parallel to the direction between the drain and the source; and the semiconductor between the first conductive type drain layer and the first conductive type source layer. A gate insulating film formed on the surface of the substrate and the surface of the trench, a gate electrode formed on the gate insulating film, a drain electrode electrically contacting the drain layer of the second conductivity type; A source electrode electrically contacting the first conductivity type well layer, and a distance from a drain side end of the trench to the drain electrode is equal to a distance of the gate electrode portion on the semiconductor substrate surface. A semiconductor device is provided which is shorter than a distance from a drain side end to the drain electrode.
【０００９】また、本発明（請求項３）は、半導体基板
と、前記半導体基板表面に形成された第２導電型ウェル
層と、この第２導電型ウェル層と異なる前記半導体基板
表面に選択的に形成された第１導電型ドレイン層と、前
記第２導電型ウェル層表面に選択的に形成された第１導
電型ソース層と、前記第１導電型ドレイン層と前記第１
導電型ソース層の間の前記半導体基板表面に、ドレイン
−ソース間方向にほぼ平行な方向に形成された溝と、前
記第１導電型ドレイン層と前記第１導電型ソース層の間
の前記半導体基板表面および前記溝の表面に形成された
ゲート絶縁膜と、前記ゲート絶縁膜上に形成されたゲー
ト電極と、前記第２導電型ドレイン層に電気的にコンタ
クトするドレイン電極と、前記第２導電型ソース層と前
記第１導電型ウェル層に電気的にコンタクトするソース
電極とを具備し、前記溝のソース側端から前記ソース電
極までの距離が、前記半導体基板表面上の前記ゲート電
極部分のソース側端から前記ソース電極までの距離より
も短く、かつ前記溝のドレイン側端から前記ドレイン電
極までの距離が、前記半導体基板表面上の前記ゲート電
極部分のドレイン側端から前記ドレイン電極までの距離
よりも短いことを特徴とする半導体装置を提供する。Further, the present invention (claim 3) provides a semiconductor substrate, a second conductivity type well layer formed on the semiconductor substrate surface, and a semiconductor substrate surface different from the second conductivity type well layer. A first conductivity type drain layer selectively formed on the surface of the second conductivity type well layer; a first conductivity type drain layer selectively formed on a surface of the second conductivity type well layer;
A groove formed in the surface of the semiconductor substrate between the conductive type source layers in a direction substantially parallel to the direction between the drain and the source; and the semiconductor between the first conductive type drain layer and the first conductive type source layer. A gate insulating film formed on the surface of the substrate and the surface of the trench, a gate electrode formed on the gate insulating film, a drain electrode electrically contacting the drain layer of the second conductivity type; A source electrode electrically contacting the first conductivity type well layer, wherein a distance from a source side end of the trench to the source electrode is equal to a distance of the gate electrode portion on the semiconductor substrate surface. The distance from the source-side end to the source electrode is shorter than the distance from the drain-side end of the trench to the drain electrode, and the drain of the gate electrode portion on the semiconductor substrate surface To provide a semiconductor device, characterized in that shorter than the distance from the edge to the drain electrode.
【００１０】本発明によれば、素子長を短くできるた
め、同じ素子のオン抵抗で面積を小さくできる。According to the present invention, since the element length can be reduced, the area can be reduced by the on-resistance of the same element.
【００１１】[0011]
【発明の実施の形態】図１は本発明の第１の実施形態を
説明する平面図であり、図２（ａ）は図１での線Ａ−Ａ
‘、図２（ｂ）は図１での線Ｂ−Ｂ'での断面図であ
る。図中１はＮ型半導体基板を示しており、Ｎ型半導体
基板１表面に選択的にＰ型ウェル層２が形成されてお
り、Ｎ型半導体基板１表面に選択的にＮ型ドレイン層３
が形成され、Ｐ型ウェル層２の表面に選択的にＮ型ソー
ス層４が形成され、Ｎ型ドレイン層３とＮ型ソース層４
の間には溝５がドレイン−ソース方向とほぼ平行に形成
され、Ｎ型ドレイン層３とＮ型ソース層４のＰ型ウェル
層２表面と溝５表面にはゲート絶縁膜６が形成され、ゲ
ート絶縁膜６上にはゲート電極７が形成され、Ｎ型ドレ
イン層３と電気的にコンタクトするドレイン電極８と、
Ｎ型ソース層及びＰ型ウェル層に電気的にコンタクトす
るソース電極９が形成されている。また、溝５はドレイ
ン−ソース方向とほぼ９０度の角度をなして繰り返し複
数形成されている。また、溝５のソース側端からソース
電極９までの距離はゲート電極７のソース側端からソー
ス電極までの距離よりも短い。このような構造にするこ
とにより、図７のＬに相当する距離を短くすることがで
きる。また、さらにソースｎ＋層をゲートポリシリコン
をマスクとしてイオン注入により形成できるので、プロ
セス上の精度も向上する。本構造により、耐圧２５Ｖで
オン抵抗は１３ｍΩ・ｍｍ２に低減する。FIG. 1 is a plan view for explaining a first embodiment of the present invention, and FIG. 2A is a line AA in FIG.
2B is a cross-sectional view taken along line BB 'in FIG. In the figure, reference numeral 1 denotes an N-type semiconductor substrate, in which a P-type well layer 2 is selectively formed on the surface of an N-type semiconductor substrate 1, and an N-type drain layer 3 is selectively formed on the surface of the N-type semiconductor substrate 1.
Is formed, an N-type source layer 4 is selectively formed on the surface of the P-type well layer 2, and an N-type drain layer 3 and an N-type source layer 4 are formed.
A groove 5 is formed substantially in parallel with the drain-source direction, and a gate insulating film 6 is formed on the surface of the P-type well layer 2 of the N-type drain layer 3 and the N-type source layer 4 and on the surface of the groove 5. A gate electrode 7 is formed on the gate insulating film 6, and a drain electrode 8 electrically contacting the N-type drain layer 3;
A source electrode 9 is formed to electrically contact the N-type source layer and the P-type well layer. Also, a plurality of grooves 5 are repeatedly formed at an angle of about 90 degrees with the drain-source direction. The distance from the source side end of the groove 5 to the source electrode 9 is shorter than the distance from the source side end of the gate electrode 7 to the source electrode. With such a structure, the distance corresponding to L in FIG. 7 can be reduced. Further, since the source n + layer can be formed by ion implantation using the gate polysilicon as a mask, the accuracy in the process is improved. With this structure, the on-resistance is reduced to 13 mΩ · mm 2 at a withstand voltage of 25 V.
【００１２】図３は本発明の第２の実施形態を説明する
平面図であり、図４は図３での線Ａ−Ａ‘での断面図で
ある。図中１はＮ型半導体基板を示しており、Ｎ型半導
体基板１表面に選択的にＰ型ウェル層２が形成されてお
り、Ｎ型半導体基板１表面に選択的にＮ型ドレイン層３
が形成され、Ｐ型ウェル層２の表面に選択的にＮ型ソー
ス層４が形成され、Ｎ型ドレイン層３とＮ型ソース層４
の間には溝５がドレイン−ソース方向とほぼ平行に形成
され、Ｎ型ドレイン層３とＮ型ソース層４のＰ型ウェル
層２表面と溝５表面にはゲート絶縁膜６が形成され、ゲ
ート絶縁膜６上にはゲート電極７が形成され、Ｎ型ドレ
イン層３と電気的にコンタクトするドレイン電極８と、
Ｎ型ソース層及びＰ型ウェル層に電気的にコンタクトす
るソース電極９が形成されている。また、溝５はドレイ
ン−ソース方向とほぼ９０度の角度をなして繰り返し複
数形成されている。また、溝５のドレイン側端からドレ
イン電極９までの距離はゲート電極７のドレイン側端か
らドレイン電極までの距離よりも短い。このような構造
にすることにより、図７のＬ‘に相当する距離を短くす
ることができる。これにより、耐圧２５Ｖでオン抵抗は
１５ｍΩ・ｍｍ２に低減する。FIG. 3 is a plan view illustrating a second embodiment of the present invention, and FIG. 4 is a cross-sectional view taken along line AA 'in FIG. In the figure, reference numeral 1 denotes an N-type semiconductor substrate, in which a P-type well layer 2 is selectively formed on the surface of an N-type semiconductor substrate 1, and an N-type drain layer 3 is selectively formed on the surface of the N-type semiconductor substrate 1.
Is formed, an N-type source layer 4 is selectively formed on the surface of the P-type well layer 2, and an N-type drain layer 3 and an N-type source layer 4 are formed.
A groove 5 is formed substantially in parallel with the drain-source direction, and a gate insulating film 6 is formed on the surface of the P-type well layer 2 of the N-type drain layer 3 and the N-type source layer 4 and on the surface of the groove 5. A gate electrode 7 is formed on the gate insulating film 6, and a drain electrode 8 electrically contacting the N-type drain layer 3;
A source electrode 9 is formed to electrically contact the N-type source layer and the P-type well layer. Also, a plurality of grooves 5 are repeatedly formed at an angle of about 90 degrees with the drain-source direction. The distance from the drain side end of the groove 5 to the drain electrode 9 is shorter than the distance from the drain side end of the gate electrode 7 to the drain electrode. With such a structure, the distance corresponding to L ′ in FIG. 7 can be reduced. Thereby, the on-resistance is reduced to 15 mΩ · mm 2 at a withstand voltage of 25 V.
【００１３】図５は本発明の第３の実施形態を説明する
平面図であり、図６は図５での線Ａ−Ａ‘での断面図で
ある。図中１０はＰ型半導体基板を示しており、Ｐ型半
導体基板１０表面にＰ型ウェル層２が形成されており、
Ｐ型ウェル層２表面に選択的にＮ型ドレイン層３が形成
され、Ｐ型ウェル層２の表面に選択的にＮ型ソース層４
が形成され、Ｎ型ドレイン層３とＮ型ソース層４の間に
は溝５がドレイン−ソース方向とほぼ平行に形成され、
Ｎ型ドレイン層３とＮ型ソース層４のＰ型ウェル層２表
面と溝５表面にはゲート絶縁膜６が形成され、ゲート絶
縁膜６上にはゲート電極７が形成され、Ｎ型ドレイン層
３と電気的にコンタクトするドレイン電極８と、Ｎ型ソ
ース層及びＰ型ウェル層に電気的にコンタクトするソー
ス電極９が形成されている。また、溝５はドレイン−ソ
ース方向とほぼ９０度の角度をなして繰り返し複数形成
されている。また、溝５のソース側端からソース電極９
までの距離はゲート電極７のソース側端からソース電極
までの距離よりも短く、溝５のドレイン側端からドレイ
ン電極９までの距離はゲート電極７のドレイン側端から
ドレイン電極までの距離よりも短い。このような構造に
することにより、図８のＬとＬ'に相当する距離を短く
することができる。また、さらにソースｎ＋層をゲート
ポリシリコンをマスクとしてイオン注入により形成でき
るので、プロセス上の精度も向上する。本構造により、
耐圧１２Ｖでオン抵抗は５ｍΩ・ｍｍ２に低減する。FIG. 5 is a plan view for explaining a third embodiment of the present invention, and FIG. 6 is a sectional view taken along line AA 'in FIG. In the drawing, reference numeral 10 denotes a P-type semiconductor substrate, and a P-type well layer 2 is formed on the surface of the P-type semiconductor substrate 10;
An N-type drain layer 3 is selectively formed on the surface of the P-type well layer 2, and an N-type source layer 4 is selectively formed on the surface of the P-type well layer 2.
Is formed, and a groove 5 is formed between the N-type drain layer 3 and the N-type source layer 4 substantially in parallel with the drain-source direction.
A gate insulating film 6 is formed on the surface of the P-type well layer 2 and the surface of the trench 5 of the N-type drain layer 3 and the N-type source layer 4, and a gate electrode 7 is formed on the gate insulating film 6; A drain electrode 8 electrically contacting with the gate electrode 3 and a source electrode 9 electrically contacting the N-type source layer and the P-type well layer are formed. Also, a plurality of grooves 5 are repeatedly formed at an angle of about 90 degrees with the drain-source direction. Further, the source electrode 9 extends from the source side end of the groove 5.
Is shorter than the distance from the source side end of the gate electrode 7 to the source electrode, and the distance from the drain side end of the groove 5 to the drain electrode 9 is shorter than the distance from the drain side end of the gate electrode 7 to the drain electrode. short. With such a structure, the distance corresponding to L and L ′ in FIG. 8 can be reduced. Further, since the source n + layer can be formed by ion implantation using the gate polysilicon as a mask, the accuracy in the process is improved. With this structure,
At a withstand voltage of 12 V, the on-resistance is reduced to 5 mΩ · mm 2.
【００１４】なお、本発明は上記実施形態に限定される
ことはなく、その趣旨を逸脱しない範囲で種々変形して
実施可能である。It should be noted that the present invention is not limited to the above-described embodiment, and can be implemented in various modifications without departing from the spirit thereof.
【００１５】[0015]
【発明の効果】以上説明したように、本発明が提供する
ＭＯＳＦＥＴでは素子長を短くできるため、同じ素子の
オン抵抗で面積を小さくできる。As described above, in the MOSFET provided by the present invention, since the element length can be shortened, the area can be reduced by the ON resistance of the same element.
【図１】本発明による半導体装置の第１の実施形態を示
す平面図。FIG. 1 is a plan view showing a first embodiment of a semiconductor device according to the present invention.
【図２】図１のＡ−Ａ‘及びＢ−Ｂ‘での断面図。FIG. 2 is a cross-sectional view taken along AA # and BB # in FIG.
【図３】本発明による半導体装置の第２の実施形態を示
す平面図。FIG. 3 is a plan view showing a second embodiment of the semiconductor device according to the present invention.
【図４】図３のＡ−Ａ‘での断面図。FIG. 4 is a sectional view taken along the line AA in FIG. 3;
【図５】本発明による半導体装置の第３の実施形態を示
す平面図。FIG. 5 is a plan view showing a third embodiment of the semiconductor device according to the present invention.
【図６】図５のＡ−Ａ‘での断面図。FIG. 6 is a sectional view taken along line AA ′ of FIG. 5;
【図７】従来の半導体装置の構成を示す断面図。FIG. 7 is a cross-sectional view illustrating a configuration of a conventional semiconductor device.
【図８】従来の他の半導体装置の構成を示す断面図。FIG. 8 is a cross-sectional view illustrating a configuration of another conventional semiconductor device.
１ … Ｎ型半導体基板 ２ … Ｐ型ウェル層 ３ … Ｎ型ドレイン層 ４ … Ｎ型ソース層 ５ … 溝 ６ … ゲート絶縁膜 ７ … ゲート電極 ８ … ドレイン電極 ９ … ソース電極 １０ … Ｐ型半導体基板 １０１ … Ｎ型半導体基板 １０２ … Ｐ型ウェル層 １０３ … Ｎ型ドレイン層 １０４ … Ｎ型ソース層 １０５ … 溝 １０６ … ゲート絶縁膜 １０７ … ゲート電極 １０８ … ドレイン電極 １０９ … ソース電極 １１０ … Ｐ型半導体基板 DESCRIPTION OF SYMBOLS 1 ... N-type semiconductor substrate 2 ... P-type well layer 3 ... N-type drain layer 4 ... N-type source layer 5 ... Groove 6 ... Gate insulating film 7 ... Gate electrode 8 ... Drain electrode 9 ... Source electrode 10 ... P-type semiconductor substrate 101 ... N-type semiconductor substrate 102 ... P-type well layer 103 ... N-type drain layer 104 ... N-type source layer 105 ... groove 106 ... gate insulating film 107 ... gate electrode 108 ... drain electrode 109 ... source electrode 110 ... P-type semiconductor substrate
───────────────────────────────────────────────────── フロントページの続き (72)発明者 中川 明夫 神奈川県川崎市幸区小向東芝町１番地 株 式会社東芝研究開発センター内 Ｆターム(参考） 5F040 DA22 EB01 EB13 EC16 EC20 EF18 ────────────────────────────────────────────────── ─── Continuing from the front page (72) Inventor Akio Nakagawa 1 Kosuka Toshiba-cho, Saiwai-ku, Kawasaki-shi, Kanagawa F-term in the Toshiba R & D Center (reference) 5F040 DA22 EB01 EB13 EC16 EC20 EF18
Claims (3)
成された第２導電型ウェル層と、この第２導電型ウェル
層と異なる前記半導体基板表面に選択的に形成された第
１導電型ドレイン層と、前記第２導電型ウェル層表面に
選択的に形成された第１導電型ソース層と、前記第１導
電型ドレイン層と前記第１導電型ソース層の間の前記半
導体基板表面に、ドレイン−ソース間方向にほぼ平行な
方向に形成された溝と、前記第１導電型ドレイン層と前
記第１導電型ソース層の間の前記半導体基板表面および
前記溝の表面に形成されたゲート絶縁膜と、前記ゲート
絶縁膜上に形成されたゲート電極と、前記第２導電型ド
レイン層に電気的にコンタクトするドレイン電極と、前
記第２導電型ソース層と前記第１導電型ウェル層に電気
的にコンタクトするソース電極とを具備し、前記溝のソ
ース側端から前記ソース電極までの距離が、前記半導体
基板表面上の前記ゲート電極部分のソース側端から前記
ソース電極までの距離よりも短いことを特徴とする半導
体装置。1. A semiconductor substrate, a second conductivity type well layer formed on a surface of the semiconductor substrate, and a first conductivity type drain selectively formed on a surface of the semiconductor substrate different from the second conductivity type well layer. A layer, a first conductivity type source layer selectively formed on the surface of the second conductivity type well layer, and a surface of the semiconductor substrate between the first conductivity type drain layer and the first conductivity type source layer. A groove formed in a direction substantially parallel to the direction between the drain and the source; and a gate insulating layer formed on the surface of the semiconductor substrate and the surface of the groove between the first conductivity type drain layer and the first conductivity type source layer. A film, a gate electrode formed on the gate insulating film, a drain electrode in electrical contact with the second conductivity type drain layer, and an electrical connection in the second conductivity type source layer and the first conductivity type well layer. Contact A source electrode, wherein a distance from the source side end of the trench to the source electrode is shorter than a distance from the source side end of the gate electrode portion on the semiconductor substrate surface to the source electrode. Semiconductor device.
成された第２導電型ウェル層と、この第２導電型ウェル
層と異なる前記半導体基板表面に選択的に形成された第
１導電型ドレイン層と、前記第２導電型ウェル層表面に
選択的に形成された第１導電型ソース層と、前記第１導
電型ドレイン層と前記第１導電型ソース層の間の前記半
導体基板表面に、ドレイン−ソース間方向にほぼ平行な
方向に形成された溝と、前記第１導電型ドレイン層と前
記第１導電型ソース層の間の前記半導体基板表面および
前記溝の表面に形成されたゲート絶縁膜と、前記ゲート
絶縁膜上に形成されたゲート電極と、前記第２導電型ド
レイン層に電気的にコンタクトするドレイン電極と、前
記第２導電型ソース層と前記第１導電型ウェル層に電気
的にコンタクトするソース電極とを具備し、前記溝のド
レイン側端から前記ドレイン電極までの距離が、前記半
導体基板表面上の前記ゲート電極部分のドレイン側端か
ら前記ドレイン電極までの距離よりも短いことを特徴と
する半導体装置。2. A semiconductor substrate, a second conductivity type well layer formed on the semiconductor substrate surface, and a first conductivity type drain selectively formed on the semiconductor substrate surface different from the second conductivity type well layer. A layer, a first conductivity type source layer selectively formed on the surface of the second conductivity type well layer, and a surface of the semiconductor substrate between the first conductivity type drain layer and the first conductivity type source layer. A groove formed in a direction substantially parallel to the direction between the drain and the source; A film, a gate electrode formed on the gate insulating film, a drain electrode in electrical contact with the second conductivity type drain layer, and an electrical connection in the second conductivity type source layer and the first conductivity type well layer. Contact A distance from the drain-side end of the trench to the drain electrode is shorter than a distance from the drain-side end of the gate electrode portion on the surface of the semiconductor substrate to the drain electrode. Semiconductor device.
成された第２導電型ウェル層と、この第２導電型ウェル
層と異なる前記半導体基板表面に選択的に形成された第
１導電型ドレイン層と、前記第２導電型ウェル層表面に
選択的に形成された第１導電型ソース層と、前記第１導
電型ドレイン層と前記第１導電型ソース層の間の前記半
導体基板表面に、ドレイン−ソース間方向にほぼ平行な
方向に形成された溝と、前記第１導電型ドレイン層と前
記第１導電型ソース層の間の前記半導体基板表面および
前記溝の表面に形成されたゲート絶縁膜と、前記ゲート
絶縁膜上に形成されたゲート電極と、前記第２導電型ド
レイン層に電気的にコンタクトするドレイン電極と、前
記第２導電型ソース層と前記第１導電型ウェル層に電気
的にコンタクトするソース電極とを具備し、前記溝のソ
ース側端から前記ソース電極までの距離が、前記半導体
基板表面上の前記ゲート電極部分のソース側端から前記
ソース電極までの距離よりも短く、かつ前記溝のドレイ
ン側端から前記ドレイン電極までの距離が、前記半導体
基板表面上の前記ゲート電極部分のドレイン側端から前
記ドレイン電極までの距離よりも短いことを特徴とする
半導体装置。3. A semiconductor substrate, a second conductivity type well layer formed on the semiconductor substrate surface, and a first conductivity type drain selectively formed on the semiconductor substrate surface different from the second conductivity type well layer. A layer, a first conductivity type source layer selectively formed on the surface of the second conductivity type well layer, and a surface of the semiconductor substrate between the first conductivity type drain layer and the first conductivity type source layer. A groove formed in a direction substantially parallel to the direction between the drain and the source; and a gate insulating layer formed on the surface of the semiconductor substrate and the surface of the groove between the first conductivity type drain layer and the first conductivity type source layer. A film, a gate electrode formed on the gate insulating film, a drain electrode in electrical contact with the second conductivity type drain layer, and an electrical connection in the second conductivity type source layer and the first conductivity type well layer. Contact A distance from the source side end of the trench to the source electrode is shorter than a distance from the source side end of the gate electrode portion on the surface of the semiconductor substrate to the source electrode, and Wherein the distance from the drain side end to the drain electrode is shorter than the distance from the drain side end of the gate electrode portion on the surface of the semiconductor substrate to the drain electrode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11186545A JP2001015742A (en) | 1999-06-30 | 1999-06-30 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11186545A JP2001015742A (en) | 1999-06-30 | 1999-06-30 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2001015742A true JP2001015742A (en) | 2001-01-19 |
Family
ID=16190390
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11186545A Pending JP2001015742A (en) | 1999-06-30 | 1999-06-30 | Semiconductor device |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006294645A (en) * | 2005-04-05 | 2006-10-26 | Seiko Instruments Inc | Semiconductor device and manufacturing method thereof |
| KR100878287B1 (en) * | 2006-08-28 | 2009-01-13 | 미쓰비시덴키 가부시키가이샤 | Insulated gate semiconductor device and method for manufacturing the same |
| JP2015141922A (en) * | 2014-01-27 | 2015-08-03 | 世界先進積體電路股▲ふん▼有限公司 | Semiconductor device and method of manufacturing the same |
| US9130033B2 (en) | 2013-12-03 | 2015-09-08 | Vanguard International Semiconductor Corporation | Semiconductor device and method for fabricating the same |
| WO2019202350A1 (en) * | 2018-04-19 | 2019-10-24 | 日産自動車株式会社 | Semiconductor device and method of manufacturing semiconductor device |
| CN114975601A (en) * | 2022-07-28 | 2022-08-30 | 合肥晶合集成电路股份有限公司 | Semiconductor device and manufacturing method thereof |
-
1999
- 1999-06-30 JP JP11186545A patent/JP2001015742A/en active Pending
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006294645A (en) * | 2005-04-05 | 2006-10-26 | Seiko Instruments Inc | Semiconductor device and manufacturing method thereof |
| KR101235502B1 (en) * | 2005-04-05 | 2013-02-20 | 세이코 인스트루 가부시키가이샤 | Semiconductor device and method of manufacturing the same |
| KR100878287B1 (en) * | 2006-08-28 | 2009-01-13 | 미쓰비시덴키 가부시키가이샤 | Insulated gate semiconductor device and method for manufacturing the same |
| US9130033B2 (en) | 2013-12-03 | 2015-09-08 | Vanguard International Semiconductor Corporation | Semiconductor device and method for fabricating the same |
| JP2015141922A (en) * | 2014-01-27 | 2015-08-03 | 世界先進積體電路股▲ふん▼有限公司 | Semiconductor device and method of manufacturing the same |
| WO2019202350A1 (en) * | 2018-04-19 | 2019-10-24 | 日産自動車株式会社 | Semiconductor device and method of manufacturing semiconductor device |
| JPWO2019202350A1 (en) * | 2018-04-19 | 2021-04-22 | 日産自動車株式会社 | Semiconductor devices and methods for manufacturing semiconductor devices |
| CN114975601A (en) * | 2022-07-28 | 2022-08-30 | 合肥晶合集成电路股份有限公司 | Semiconductor device and manufacturing method thereof |
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