JP2001094099A - Silicon carbide semiconductor device and fabrication method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To decrease ON resistance furthermore in a storage mode MOSFET. SOLUTION: A mechanism for holding charges is provided between a gate electrode 8 and a surface channel layer 5. More specifically, a floating gate 12 is provided between the gate electrode 8 and the surface channel layer 5 to form a two layer gate structure. The floating gate 12 is injected with electrons in order to offset the relation between the gate potential and the field on the surface of a semiconductor. Since the charge holding mechanism can have a negative potential even if the gate potential is equal to or higher than zero, an MOSFET having ON resistance equivalent to that of a depletion type device can be obtained while keeping normally off characteristics.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a silicon carbide semiconductor device and a method of manufacturing the same, and more particularly to an insulated gate field effect transistor, especially a power MOSFET for high power.
It is about.

[0002]

2. Description of the Related Art Conventionally, as a planar type MOSFET which operates in a storage mode, a MOSFET disclosed in Japanese Patent Application Laid-Open No. H11-308510 is known.

FIG. 16 is a sectional view of this planar type MOSFET. Based on this diagram, a planar MOSFET
Will be described.

An n ⁺ -type silicon carbide semiconductor substrate (hereinafter referred to as an n ⁺ -type substrate) 1 has an upper surface as a main surface 1a and a lower surface opposite to the main surface as a back surface 1b. On the main surface of this n ⁺ type semiconductor substrate 1, an n ⁻ type silicon carbide epitaxial layer (hereinafter referred to as n
^- that type epi layer) 2 are laminated.

[0005] n^-Region in the surface layer portion of the mold epi layer 2
Has a predetermined depth p^--Type silicon carbide base region 3a
And p^--Type silicon carbide base region 3b (hereinafter, p^-Type
Source regions 3a and 3b) are formed apart from each other.
You. Also, p^-Predetermined at the surface portion of the mold base region 3a
The region contains p^-N shallower than mold base region 3a⁺Mold saw
Region 4a also has p^-On the surface of the mold base region 3b
The predetermined area in the ^-Shallower than mold base region 3b
n⁺The mold source regions 4b are respectively formed.

Further, the n ⁻ type epi layer 2 and the p ⁻ layer between the n ⁺ type source region 4a and the n ⁺ type source region 4b are provided.
N ⁻ -type SiC layer 5 is provided on the surface of base regions 3a and 3b.
Is extended. That is, the p ⁻ -type base regions 3a, 3a
An n ⁻ -type SiC layer 5 is arranged so as to connect the source regions 4a and 4b and the n ⁻ -type epi layer 2 on the surface of the surface b. This n ⁻ -type SiC layer 5 is formed by epitaxial growth, and the crystal of the epitaxial film is
H, 6H and 3C are used. The epitaxial layer can form various crystals regardless of the underlying substrate. When the device operates, it functions as a channel forming layer on the device surface. Hereinafter, n ⁻ -type SiC layer 5 is referred to as a surface channel layer.

The dopant concentration of the surface channel layer 5 is 1
It has a low concentration of about × 10 ¹⁵ cm ⁻³ to 1 × 10 ¹⁷ cm ⁻³ , and has an n ⁻ -type epi layer 2 and a p ⁻ -type base region 3.
a, 3b or less. Thereby, low on-resistance is achieved.

Further, the p ^- type base regions 3a, 3b, n ⁺
Concave portions 6a and 6b are formed in the surface portions of the mold source regions 4a and 4b.

A gate insulating film (silicon oxide film) 7 is formed on the upper surface of the surface channel layer 5 and the upper surfaces of the n ⁺ type source regions 4a and 4b. Further, a gate electrode 8 is formed on the gate insulating film 7. Gate electrode 8 is covered with insulating film 9. LTO (L
(Operating Temperature Oxide) film. A source electrode 10 is formed thereon, and the source electrode 10 has n ⁺ type source regions 4a, 4b and p ⁻
It is in contact with the mold base regions 3a, 3b. Further, a drain electrode layer 11 is formed on the back surface of the n ⁺ type substrate 1.

[0010]

SUMMARY OF THE INVENTION The above conventional MOSFE
At T, the on-resistance is reduced by operating in the accumulation mode. However, further reduction in on-resistance is desired.

The present invention has been made in view of the above points, and has as its object to further reduce the on-resistance in a storage mode MOSFET.

[0012]

Means for Solving the Problems In order to achieve the above object, the present inventors have studied a MOSFET in an accumulation mode. As a result, the higher the surface channel layer concentration and the lower the threshold voltage, the lower the on-state current. Is increased, that is, the on-resistance can be reduced.
FIG. 17 shows the relationship between the concentration of the surface channel layer and the ON current.

As shown in this figure, the lower the threshold voltage is, the larger the on-current is. Particularly, the on-current is significantly increased by using a negative depletion type MOS. I understood.

However, the depletion type MOS
The FET has normally-on characteristics and is therefore not preferable from the viewpoint of fail-safe. Thus, the present inventors
Further investigation was made on obtaining a MOSFET having an ON current equivalent to that of a depletion-type MOSFET and having normally-on characteristics.

Since the depletion-type MOSFET has normally-on characteristics, switching can be performed by applying a negative voltage to the surface channel layer.

That is, if a negative voltage is applied to the surface channel layer when no voltage is applied to the gate electrode (gate voltage is zero), the threshold value becomes positive (normally off characteristic). ) Enhancement type MOSFET
It can be.

Therefore, in order to achieve the above object, the invention according to claim 1 or 2 has a mechanism capable of retaining charges between the gate electrode (8) and the surface channel layer (5). It is characterized by: Specifically, claim 3
As shown in (1), the charge is injected into a mechanism capable of holding the charge, and the relationship between the gate potential and the electric field on the semiconductor surface is offset.

As described above, by providing the charge holding mechanism, the charge holding mechanism can be set to a negative potential even when the gate potential is used at zero or more. A silicon carbide semiconductor device having on-resistance can be obtained.

For example, the gate insulating film may be composed of a composite film of a silicon oxide film and a silicon nitride film, and charge may be held at an interface between the silicon oxide film and the silicon nitride film. In this case, since the conventional manufacturing process can be dealt with only by changing the gate insulating film to a composite film of the silicon oxide film and the silicon nitride film, the charge holding mechanism can be realized with a small load on the process. .

According to a fifth aspect of the present invention, the gate insulating film includes a first gate insulating film (7a, 57a) and a second gate insulating film (7b, 57b). 1,
A conductive floating gate (12, 60) is provided between the second gate insulating films, and the floating gate can hold charges. Such a charge holding mechanism using a floating gate can hold charges with high reliability.

According to the sixth aspect of the present invention, the semiconductor substrate forms an MOS operation by forming a channel region.
An S operation region and a write region provided at a position different from the MOS operation region. The floating gate extends from the MOS operation region to the write region. In the write region, charges are injected. It is characterized by having become.

As described above, by limiting the area instead of performing writing using the entire MOSFET, it is easy to control the writing amount and a large writing amount can be obtained. Also, by providing the write terminal, even if the gate insulating film is damaged in the charge injection portion at the time of writing, the damaged region is located at a position different from the MOS operation region, so that the normal MOS is not affected by the damaged region. Operation becomes possible.

For example, in the writing area, a gate electrode extends from the MOS operation area to the writing area, and on the surface of the semiconductor substrate, both sides of the gate electrode and the floating gate in the writing area. A writing source and a writing drain may be formed in the device, and a writing terminal may be connected to each of the writing source and the writing drain.

In such a configuration, charge injection can be performed using hot carriers. As described above, by using hot carrier injection, writing can be performed at high speed.

Further, in the writing region, a writing gate which is not electrically connected to the gate electrode in the MOS operation region is formed on the floating gate, and the writing terminal is formed on the gate. May be connected.

According to a tenth aspect of the present invention, a gate electrode extending from the MOS operation region to the write region is provided in the write region, and a gate region or a well region disposed below the floating gate is provided. A configuration may be employed in which a second-conduction-type writing drain that is not electrically connected is provided, and a writing terminal that is connected to the writing drain is provided.

In such a configuration, charge injection can be performed using the FN current. in this way,
By using the FN current, a writing region and a writing terminal can be simplified and downsizing can be achieved.

According to a ninth aspect of the present invention, the writing source is also used as a source region.

As described above, by making a part of the writing area common to other areas, the size of the apparatus can be reduced.

[0030] The invention according to claim 11 is characterized in that the first gate insulating film or the second gate insulating film is partially thinned in the writing region.

As described above, by partially reducing the thickness of the first and second insulating films, a writing area can be set without providing a writing terminal. And MOSF
By limiting the area instead of performing writing using the entire ET, control of the writing amount is facilitated and a large writing amount can be obtained. Further, since there is no writing terminal, downsizing can be achieved.

In the twelfth aspect of the present invention, the surface channel layer has a structure in which, when no charge is held by the mechanism capable of holding the charge, even if the voltage is not applied to the gate electrode. It is characterized in that electrical conduction between them is possible.

As described above, if there is no offset of the gate voltage by the charge holding mechanism, the depletion type MOSF
In the case of ET, a particularly high current capability can be obtained, which is preferable.

The reference numerals in parentheses of the above means indicate the correspondence with specific means described in the embodiments described later.

[0035]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing a first embodiment of the present invention.

FIG. 1 shows a cross-sectional configuration of a MOSFET according to the present embodiment. Hereinafter, M of this embodiment will be described with reference to FIG.
The structure of the OSFET will be described. However, among the MOSFETs of this embodiment, the conventional MOSFET shown in FIG.
Components similar to or equivalent to those in T are denoted by the same reference numerals as in FIG. 16, and only different portions will be described.

As shown in FIG. 1, M in the present embodiment
In the OSFET, a floating gate 12 is formed on a surface channel layer 5 via a silicon oxide film 7a as a first insulating film, and a silicon oxide film 7b as a second insulating film is formed on the floating gate 12. , And the gate electrode 8 is formed therethrough. That is, this MOSFET employs a two-layer gate structure. Electrons having negative charges are injected into the floating gate 12. In addition, the surface channel layer 5
Is higher than the conventional one, and for example, the dopant concentration is about 1 × 10 ¹⁶ cm ⁻³ to 1 × 10 ¹⁸ cm ⁻³ . Note that a suitable dopant concentration depends on the thickness of the surface channel layer 5, and it is preferable that the dopant concentration be higher when the surface channel layer 5 is thinner than when the surface channel layer 5 is thicker.

In the MOSFET configured as described above, the floating gate 12 as a charge holding mechanism is provided between the gate electrode 8 and the surface channel layer 5 so that the surface of the surface channel layer 5 is Is changed.

That is, since the floating gate 12 is provided on the surface channel layer 5, the channel between the source and the drain is formed at the floating gate potential. Therefore, this point is different from the conventional one shown in FIG. 16 in which the channel is formed by the gate potential.

The total thickness of the silicon oxide films 7a and 7b is equal to that of the conventional MOSF shown in FIG.
The thickness corresponds to the thickness of the oxide film 7 of the ET. When the gate potential of the MOS of the present embodiment is the same as that of the conventional MOSFET, the same operating state as that of the conventional MOSFET is obtained. Is about to take.

Then, electrons are injected into the floating gate 12. As a result, the floating gate potential is set to a desired value, and the relationship between the gate voltage and the electric field on the semiconductor surface is offset.

The offset of the electric field is set as follows.

The floating gate potential is expressed by the following equation, assuming that the potential on the surface channel layer 5 side is zero.

[0044]

Vfg = (C2Vg + Q) / (C1 + C2) where Vfg is the floating gate potential, Vg is the gate potential, C1 is the capacitance between the floating gate 12 and the semiconductor, C2 is the floating gate 12 and the gate electrode 8.
Is a charge in the floating gate 12.

Therefore, by arbitrarily setting the charge Q in the floating gate 12, it is possible to offset the relationship between the floating gate potential Vfg and the gate potential Vg.

Therefore, as described above, by injecting electrons as a negative charge into the floating gate 12, the floating gate 12 can take a negative potential when the gate potential is used at zero or more. .

FIG. 2 shows the potential of the gate electrode 8 before and after the electrons are injected into the floating gate 12 (hereinafter referred to as “potential”).
The relationship between the gate potential and the floating gate potential will be described, and the relationship between the gate potential and the potential applied to the surface channel layer 5 (that is, the floating gate potential) will be described.

This figure shows a case where the thicknesses of the silicon oxide films 7a and 7b are set so that the floating gate potential becomes 2/3 of the gate potential before the charge injection.

As shown in this figure, when electrons are injected into the floating gate 12, the relationship between the floating gate potential and the gate potential is shifted. Therefore, even when only the gate potential is used as positive, the floating gate 12 can be set to a negative potential.
As described above, even if the gate potential is a positive potential, the floating gate potential can be set to a negative potential, and a negative voltage can be applied to the surface channel layer 5.

FIG. 3 shows the relationship between the gate potential, the floating gate potential, and the drain current when the floating gate 12 is provided.

As shown in this figure, the surface channel layer 5 is so concentrated that a negative voltage is required to turn off the channel. If the floating gate potential does not become a negative potential, the drain current becomes zero. That is, the channel is not turned off. However, since the charge of Q <0 is present in the floating gate 12, the floating gate potential can be made negative even when the gate potential is zero or more, and the channel is turned off at the gate potential Vg = 0V. Can be.

Next, the operation (operation) of the MOSFET in this embodiment will be described.

The present MOSFET operates in a normally-off storage mode. When no voltage is applied to the gate electrode 8, a negative potential is applied to the surface channel layer 5 by the floating gate 12. Therefore, carriers in the surface channel layer 5 are p ⁻ type base regions 3.
The channel is turned off by a depletion layer formed by the difference in electrostatic potential between a, 3b and surface channel layer 5, and a depletion layer formed on the surface of surface channel layer 5 by the negative potential of floating gate 12. You.

Subsequently, by applying a voltage to the gate electrode 8, the potential of the floating gate 12 is raised. As a result, the depletion layer on the surface of the surface channel layer 5 is reduced, and the channel region extending from the n ⁺ -type source regions 4a and 4b toward the n ^-- type drift region 2 at the interface between the silicon oxide film 7a and the surface channel layer 5 Are formed and switched to the ON state.

At this time, electrons are supplied to the n ⁺ type source region 4.
a, 4b pass through the surface channel layer 5 and flow from the surface channel layer 5 to the n ⁻ -type epi layer 2. Then, when reaching the n ⁻ type epi layer 2 (drift region), the electrons are transferred to the n ⁺ type substrate 1
It flows vertically to (n ⁺ drain).

As described above, the MOSFET which operates as a depletion type without the floating gate 12 into which electrons are injected can turn off the channel by the negative potential of the floating gate 12 when the gate potential is substantially zero. It operates as an enhancement-type MOSFET with normally-off characteristics.

As a result, as shown in FIG. 17, when the floating gate 12 is not provided, the on-resistance is equivalent to that of a depletion-type MOSFET, and the on-resistance can be further reduced. In addition, this can increase the power of the device and the size of the chip. In addition, by holding charges in the floating gate 12 in this manner, charge can be held with high reliability.

Next, a manufacturing process of the MOSFET according to the present embodiment will be described with reference to FIGS. The semiconductor region is described in the related art (Japanese Unexamined Patent Application Publication No.
No. 0 publication), only different parts will be described.

[Step shown in FIG. 4A] First, a 4H or 6H SiC substrate, that is, an n ⁺ type substrate 1 is prepared. Here, the n ⁺ type substrate 1 has a thickness of 400 μm, and the main surface 1a has a (0001) Si plane or (11)
2-0) The a-plane. The main surface 1a of the substrate 1 has a thickness of 5
A μm n ⁻ -type epi layer 2 is epitaxially grown. In this example, the same crystal as that of the underlying substrate 1 is obtained as the n ⁻ -type epi layer 2, which becomes an n-type 4H or 6H or 3C—SiC layer.

[Step shown in FIG. 4B] n ^- type epi layer 2
The LTO film 20 is arranged in a predetermined region above, and B ⁺ (or aluminum) is ion-implanted using the LTO film 20 as a mask to form p ⁻ -type base regions 3a and 3b. The ion implantation conditions at this time are a temperature of 700 ° C. and a dose of 1
× 10 ¹⁶ cm ^-2 .

[Step shown in FIG. 4C] After removing the LTO film 20, a surface channel layer 5 is formed on the n ⁻ -type epi layer 2 including the p ⁻ -type base regions 3a and 3b by a chemical vapor deposition method ( CV
D method). At this time, SiH ₄ , C ₃ H ₈ , H ₂ , and N ₂ are used as a source gas. Here, N ₂ is used to make the surface channel layer 5 n-type.

[Step shown in FIG. 5 (a)] An LTO film 21 is disposed in a predetermined region on the surface channel layer 5, and using this as a mask, N ⁺ ions are implanted to form an n ⁺ source region 4a,
4b is formed. The ion implantation condition at this time is 700
C. and the dose is 1 × 10 ¹⁵ cm ⁻² .

[Steps shown in FIG. 5 (b)]
After removing the film 21, an LTO film 22 is disposed in a predetermined region on the surface channel layer 5 by using a photoresist method, and the p ^- type base region 3 a is formed by RIE using the LTO film 22 as a mask.
The surface channel layer 5 on 3b is partially etched away.

[Step shown in FIG. 5C] After removing the LTO film 22, a gate oxide film 7a is formed on the substrate by wet oxidation. At this time, the ambient temperature is 1080 ° C.
And

Next, in order to form the floating gate 12 on the gate oxide film 7a, 1st-polyS
i20 is deposited by LPCVD.

Subsequently, after oxidizing the 1st-polySi 20 to form a gate oxide film 7b, to form a gate electrode 8 on the gate oxide film 7b, 2nd-polySi 20 is formed.
PolySi 21 is deposited by LPCVD.

[Step shown in FIG. 6 (a)] Then, the second-polySi 21, the silicon oxide film 7b, and the first-poly Si 20 are patterned through the lithography step. Thereby, the gate electrode 8 and the floating gate 12 are formed.

Subsequently, the surfaces of the gate electrode 8 and the floating gate 12 are covered with an oxide film by thermal oxidation. Thereafter, an interlayer insulating film 9 made of LTO is formed to cover the gate insulating film 7.

[Step shown in FIG. 6C] Then, after forming a contact hole in the interlayer insulating film 9 and the oxide film,
The source electrode 10 and the drain electrode 11 are arranged by metal sputtering at room temperature. After the film formation, 1000
Anneal at ℃.

Thereafter, charge injection into the floating gate 12 is performed. The schematic diagram of the charge injection is shown in FIG. 7, and the charge injection will be described with reference to FIG.

The charge is injected into the floating gate 12
And semiconductor (surface channel layer 5 and source regions 4a and 4b)
This is performed by applying a potential to the gate electrode 8 such that charge transfer occurs between the gate electrodes 8 or between the floating gate 12 and the gate electrode 8. This is between the floating gate 12 and the semiconductor and the floating gate 12
The selection is made depending on which one between the gate electrode 8 and the gate electrode 8 is easy to pass a current. That is, the silicon oxide films 7a, 7b
The ease of current flow is determined by the film quality (thickness distribution, defects, etc.), so that the film quality of the silicon oxide films 7a and 7b can be set in advance so as to facilitate charge injection.

In the case where a current flows more easily between the floating gate 12 and the semiconductor than between the floating gate 12 and the gate electrode 8, FIG.
As shown in (1), a positive voltage is applied to the gate electrode 8 with the source electrode 10 and the drain electrode 11 grounded. As a result, electrons are injected into the floating gate 12 as negative charges. In the case where a current flows more easily between the floating gate 12 and the gate electrode 8 than between the floating gate 12 and the semiconductor, FIG.
As shown in (b), the source electrode 10 and the drain electrode 1
1 is grounded, and a negative voltage is applied to the gate electrode 12. As a result, electrons are injected into the floating gate 12 as negative charges.

Thus, the MOSFET shown in FIG. 1 is completed.

(Second Embodiment) FIG. 8 shows a cross-sectional configuration of a MOSFET according to this embodiment. In this embodiment, since the gate structure of the MOSFET of the first embodiment is changed, only the changed portion will be described.

As shown in FIG. 8, the MOSF of this embodiment is
In the ET, a silicon nitride film 13 is formed on a surface channel layer 5 via a silicon oxide film 7a as a first insulating film. Then, a gate electrode 8 is formed on the silicon nitride film 13. Thus, the silicon oxide film 7 is provided between the gate electrode 8 and the surface channel layer 5.
a and a composite film composed of the silicon nitride film 13.

In such a configuration, charges can be trapped at the interface between silicon nitride film 13 and silicon oxide film 7a. Therefore, the charge trapped at this interface plays a role similar to that of the floating gate 12 of the first embodiment, and can offset the voltage of the gate electrode 8. Thereby, the same effect as in the first embodiment can be obtained.

The MOSFET according to the present embodiment
Only increases the number of steps for forming the silicon nitride film 13 with respect to the conventional MOSFET shown in FIG. 16, so that the charge holding mechanism can be realized with a small load on the steps.

(Third Embodiment) FIG. 9 shows a cross-sectional configuration of a MOSFET according to the third embodiment. This embodiment is different from the first embodiment in that a region where charge injection is performed is defined when a charge is injected into a floating gate.

As shown in FIG. 9, the MOSF of this embodiment is
The ET forms a writing region for performing charge injection in addition to the MOS operation region. The write area is provided on a section different from that of the MOS operation area.
Assuming that the MOS FET is formed by laying the OSFETs, it is separately provided at a position away from the laid region.

The write area has the same structure as that of a so-called EPROM. A source area 4c and a drain area 14 are provided on both sides of a two-layer structure of a floating gate 12a and a gate electrode (control gate) 8a. A surface channel layer 5c serving as a channel region is provided between the drain channel 4c and the drain region 14. Note that the source region 4c is the source region 4b
Are extended, and are connected to the source electrode 10. As described above, by using the source region 4c and the source region 4b in common, the size of the device is reduced. The drain region 15 is connected to the drain electrode 15.

Then, the structure is such that the gate electrodes 8 and 8a in the MOS operation region and the write region are connected, and the structure is such that the floating gates 12 and 12a in the MOS operation region and the write region are connected (in the figure). Dotted line).

In such a configuration, charge injection is performed in the write region as shown in FIG. That is, the source electrode 10 and the drain electrode 11 are grounded, and the positive potential V1 is applied to the gate electrode 8a and the positive potential V2 is applied to the drain electrode. As a result, hot carriers can be generated and hot electrons can be injected into the floating gate 12a.

As a result, the floating gate 12a
Is injected into the floating gate 12, the floating gate 12 is connected to the floating gate 12a, so that the potential of the floating gate 12 becomes negative even if the potential of the gate electrode 8 is zero. Thereby, the MOS operation region can be operated in the same manner as in the first embodiment, and the same effect as in the first embodiment can be obtained.

Then, by using a hot carrier,
Writing can be performed at high speed. Also, since writing is performed in an area other than the MOS operation area, the silicon oxide film 7 under the floating gate 12a is written at the time of writing.
Even if a is damaged, it does not affect the MOS operation because it is not related to the MOS operation area. In the MOS operation, the effect of the electric field of the drain region 14 can be neglected because the drain electrode 15 is kept open.

Note that the manufacture of the MOSFET according to the present embodiment only requires changing the mask in the photolithography step of the step of FIG. 6A in the first embodiment, and a description thereof will be omitted.

(Fourth Embodiment) FIG. 11 shows a cross-sectional configuration of a MOSFET according to this embodiment. In this embodiment,
As compared with the first embodiment, when a charge is injected into the floating gate, a region where the charge is injected is defined.

As shown in FIG. 11, the MOS of the present embodiment is
The FET forms a write region for performing charge injection in addition to the MOS operation region. The write area is MOS
The active region is provided on another cross section. For example, if a plurality of MOSFETs are spread to form a MOS active region, the MOS active region is separately provided at a position away from the spread region.

The write area is the floating gate 1
It has a two-layer structure of 2a and a gate electrode (control gate) 8a, and has a two-layer structure formed on a source region 4c extending from the source region 4b.

Further, the floating gates 12 and 12a in the MOS operation region and the write region are connected (see the dotted line in the figure). However, MOS
The gate electrodes 8 and 8a in the operation region and the writing region are not connected.

In such a configuration, charge injection is performed in the write area as shown in FIG. That is, the gate electrode 8, the source electrode 10, and the drain electrode 11 are grounded, and the negative potential −V
Is applied.

Normally, the capacitance between the gate electrode 8a in the writing region and the floating gate 12a is determined by the capacitance between the gate electrode 8 and the floating gate 12 in the MOS operation region, or between the floating gate 12 and the semiconductor (in this embodiment, Since the capacitance is very small compared to the capacitance between the surface channel layer 5 and the source regions 4a and 4b), the potential of the floating gate 12 is hardly affected by the potential of the gate electrode 8a in the write region, and A potential, that is, a ground state (however, the potential fluctuates by an amount corresponding to the written charge). For this reason, the electric field between the gate electrode 8a and the floating gate 12a in the writing region is maximized, so that charge injection can be performed only in the writing region and a large amount of writing can be performed by the FN current.

As described above, with the above configuration,
Since a large amount of writing can be performed and writing can be performed in a region other than the MOS operation region as in the third embodiment, the silicon oxide film 7b on the floating gate 12a is damaged at the time of writing. Even if it does, it does not affect the MOS operation.
Further, since the FN current is used, a writing region and a writing terminal as a contact with each region can be simplified, and the size of the device can be reduced.

The MOSFET according to the present embodiment is manufactured by using a 2nd-poly as a mask in the photolithography step of the step of FIG. 6A in the first embodiment.
Since a mask that divides the gate electrode 8 and the gate electrode 8a at the time of etching of Si is used, and other operations may be the same as those in the third embodiment, the description will be omitted.

In the present embodiment, the lower part of the floating gate 12 in the write area is placed in the source area 4.
c, that is, an n ⁺ -type layer, but may be an n ⁻ -type layer by extending the surface channel layer 5 or the like, or a p-type layer by extending the base region 3b. Or you may.

(Fifth Embodiment) FIG. 13 shows a sectional configuration of a MOSFET according to the present embodiment. In this embodiment,
As compared with the first embodiment, when a charge is injected into the floating gate, a region where the charge is injected is defined.

As shown in FIG. 13, the MOS of the present embodiment is
The FET has a gate electrode 8 and a floating gate 12
Is extended to a region distant from the surface channel layer 5, and a tunnel film 16 thinner than the silicon oxide film 7a is provided below the floating gate 12 in this region so that charges are injected into this extended portion. It has a configuration.

As described above, by providing the tunnel film 16 in which the silicon oxide film 7a is partially thinned as the writing window, the charge can be easily injected from the tunnel film 16, and the region into which the charge is injected can be formed. Can be defined. Further, by defining the place where the writing is performed, the writing amount can be easily controlled and a large writing amount can be obtained. Further, in such a configuration, since it is not necessary to provide a separate writing terminal, the device can be simplified and the size can be reduced.

The MOSFET according to the present embodiment
After forming the silicon oxide film 7a in FIG. 6A in the first embodiment, the tunnel film forming region of the silicon oxide film 7a is once removed by etching and thermally oxidized again to form the tunnel film 16. After that, it is manufactured by performing the same steps as in the first embodiment.

In this embodiment, the silicon oxide film 7
Although a is made thinner, the silicon oxide film 7b may be made thinner depending on the charge injection method.

(Sixth Embodiment) FIG. 14 shows a cross-sectional configuration of a MOSFET according to this embodiment. In this embodiment,
As compared with the first embodiment, when a charge is injected into the floating gate, a region where the charge is injected is defined.

As shown in FIG. 14, the MOS of the present embodiment is
The FET forms a write region for performing charge injection in addition to the MOS operation region. The write area is MOS
The active region is provided on another cross section. For example, when a plurality of MOSFETs are spread to form a MOS active region, they are separately provided at a position away from the spread region.

The write area is the floating gate 1
2a and a gate electrode (control gate) 8a. The p ^- type layer 3c is formed together with the base regions 3a and 3b, and the drain for writing is formed on the surface of the p ^- type layer 3c. And a two-layer structure is formed on the upper part of the p ⁺ -type layer 17. Note that p
^The drain electrode 18 is connected to the ⁺ type layer 17.

The floating gates 12 and 12a in the MOS operation region and the writing region are connected, and the gate electrodes 8 and 8a in the MOS operation region and the writing region are connected (see FIG. (See the dotted line).

In such a configuration, the gate electrode 8
And the source electrode 10 and the drain electrode 11 are grounded, and a negative potential is applied to the drain electrode 18.

Thus, charges can be injected into floating gate 12a from p ⁺ type layer 17 side. Thus, the same effects as in the fourth embodiment can be obtained by the configuration of the present embodiment.

The MOSFET according to the present embodiment has p ⁻
The mold layer 3c is formed at the same time when the base regions 3a and 3b are formed, and although not shown in the figure, the base regions 3a and 3b
When the p ⁺ -type layer 17 is formed at the same time as forming the p ⁺ -type contact layer formed on the surface layer of the base regions 3a and 3b in order to make contact with the source electrode 10, It is manufactured without increasing the number of manufacturing steps. In addition,
As in the fourth embodiment, the two-layer gate structure in the write region is formed simultaneously with the MOS operation region by changing the mask in the photolithography step shown in FIG. 6A (seventh embodiment). FIG. 15 shows a cross-sectional configuration of the MOSFET according to the present embodiment. In this embodiment,
In this embodiment, an embodiment of the present invention is applied to a lateral MOS transistor.

As shown in FIG. 15, ap ⁻ -type layer 53 is formed on the surface of an n ⁻ -type semiconductor substrate 51.
An n ⁺ -type source region 54a and a drain region 54b are formed in the surface layer of the mold layer 53 at a distance from each other.
Surface channel layer 55 is formed so as to connect between drain region 4a and drain region 54b.

Then, the first layer is formed on the surface channel layer 55.
A floating gate 60 is formed via a silicon oxide film 57a as an insulating film, and a gate electrode 58 is formed on the floating gate 60 via a silicon oxide film 57b as a second insulating film.

An interlayer insulating film 59 is formed on the entire surface of the substrate including the gate electrode 58 and the floating gate 60, and the source region 54a and the drain region 5 are formed through contact holes formed in the interlayer insulating film 59.
4b, the gate electrode 58, and the p ⁻ type layer 53 are connected to each electrode.

In the MOS transistor thus configured, the electric field on the surface of the surface channel layer 5 is changed via the floating gate 12 by injecting charges into the floating gate 60 in the same manner as in the first embodiment. As a result, on-resistance can be reduced, current capability can be improved, and high-speed operation can be performed.

(Other Embodiments) In the above embodiment, the case where the surface channel layer 5 has a higher concentration than the conventional one has been described. The same operation as in the above embodiment is performed, and the on-resistance can be similarly reduced.

In the seventh embodiment, a lateral type M
Although an example in which the same structure as that of the first embodiment is employed in the OS transistor has been described, the same structure as that of the second to sixth embodiments may be employed.

[Brief description of the drawings]

FIG. 1 is a vertical power MO according to a first embodiment of the present invention.
It is sectional drawing of SFET.

FIG. 2 is a diagram showing a relationship between a gate potential and a floating gate potential before and after charge injection into a floating gate 12.

FIG. 3 is a diagram illustrating a relationship between a gate potential, a floating gate potential, and a drain current.

FIG. 4 is a view showing a manufacturing process of the vertical power MOSFET shown in FIG. 1;

FIG. 5 is a diagram showing a manufacturing step of the vertical power MOSFET following FIG. 4;

FIG. 6 is a view illustrating a manufacturing process of the vertical power MOSFET following FIG. 5;

FIG. 7 is a diagram showing a charge injection method for the MOSFET according to the first embodiment.

FIG. 8 is a sectional view of a MOSFET according to a second embodiment of the present invention.

FIG. 9 is a sectional view of a MOSFET according to a third embodiment of the present invention.

FIG. 10 is a diagram showing a charge injection method for a MOSFET according to a third embodiment.

FIG. 11 is a MOSFET according to a fourth embodiment of the present invention.
FIG.

FIG. 12 is a diagram illustrating a charge injection method for a MOSFET according to a fourth embodiment.

FIG. 13 shows a MOSFET according to a fifth embodiment of the present invention.
FIG.

FIG. 14 is a MOSFET according to a sixth embodiment of the present invention.
FIG.

FIG. 15 shows a MOSFET according to a seventh embodiment of the present invention.
FIG.

FIG. 16 is a sectional view of a conventional MOSFET.

FIG. 17 is a diagram showing a relationship between a gate potential and a drain current of a MOSFET having a surface channel layer 5;

[Explanation of symbols]

1 ... n ⁺ type substrate, 2 ... n ^- type epitaxial layer, 3a,
3b: p ^- type base region, 4a, 4b: n ⁺ type source region, 5: surface channel layer (n ^- type SiC layer), 7: gate insulating film, 8: gate electrode, 9: insulating film, 10: source Electrode, 11 ... Drain electrode layer, 12 ... Floating gate.

 ────────────────────────────────────────────────── ─── Continued on the front page (72) Inventor Mitsuhiro Kataoka 1-1-1, Showa-cho, Kariya-shi, Aichi Prefecture Inside Denso Corporation (72) Inventor Rajesh Kumar 1-1-1, Showa-cho, Kariya-shi, Aichi Prefecture Denso Corporation F term (reference) 5F001 AA01 AB02 AB08 AD13 AD15 AD22 AD24 AF10 5F101 BA01 BB02 BB05 BD03 BD05 BD14 BD16 BF10

Claims (12)

[Claims] A semiconductor substrate of a first conductivity type having a main surface and a back surface opposite to the main surface and made of silicon carbide.
A first conductivity type semiconductor layer (2) formed on the main surface of the semiconductor substrate and made of silicon carbide having a higher resistance than the semiconductor substrate; and formed in a predetermined region of a surface layer portion of the semiconductor layer; A second conductivity type base region (3a, 3b) having a predetermined depth; and a first conductivity type source region (4) formed in a predetermined region of a surface layer of the base region and shallower than the base region.
a, 4b), a first portion made of silicon carbide formed on the surface portion of the base region and the surface portion of the semiconductor layer so as to connect the source region and the semiconductor layer and forming a channel region.
A conductive type surface channel layer (5); gate insulating films (7a, 7b) formed on the surface of the surface channel layer; and a gate electrode (8) formed on the gate insulating film.
A source electrode (10) formed to contact the base region and the source region; and a drain electrode (1) formed on the back surface of the semiconductor substrate.
1) a silicon carbide semiconductor device comprising: a mechanism capable of retaining charges between the gate electrode and the surface channel layer. 2. A semiconductor substrate having a main surface and a back surface opposite to the main surface, the semiconductor substrate being made of silicon carbide, and a semiconductor substrate formed in a predetermined region of a surface layer of the semiconductor substrate and having a predetermined depth. A two-conductivity-type well region (53); and a first-conductivity-type source region (54) formed in a predetermined region of the surface layer of the well region and shallower than the depth of the well region.
a), the drain region (54b), and the source region (5) at the surface of the well region.
4a) a first conductivity type surface channel layer (55) made of silicon carbide forming a channel region, which is formed to connect the drain region (54b) and the drain region (54b); A gate insulating film (57a, 57b), a gate electrode (58) formed on the gate insulating film, a source electrode formed on the source region (54a), and a drain electrode formed on the drain region And a substrate electrode formed in the well region, wherein the silicon carbide semiconductor device has a mechanism capable of retaining charges between the gate electrode and the surface channel layer. 3. The silicon carbide semiconductor device according to claim 1, wherein a charge is injected into the mechanism capable of holding the charge. 4. The gate insulating film is composed of a composite film of a silicon oxide film and a silicon nitride film, and the charge can be held at an interface between the silicon oxide film and the silicon nitride film. The silicon carbide semiconductor device according to claim 1, wherein: 5. The gate insulating film comprises a first gate insulating film (7a, 57a) and a second gate insulating film (7b, 57).
b), and a conductive floating gate (12, 60) is arranged between the first and second gate insulating films so that the floating gate can hold the electric charge. The silicon carbide semiconductor device according to claim 1, wherein: 6. The semiconductor substrate according to claim 1, wherein said semiconductor substrate is formed with a MOS operation region for performing a MOS operation by forming said channel region.
A write region provided at a position different from the operation region, wherein the floating gate is extended from the MOS operation region to the write region, and the charge is injected into the write region. The silicon carbide semiconductor device according to claim 5, wherein: 7. The write region includes: a gate electrode extending from the MOS operation region to a write region; and a gate electrode formed on a surface portion of the semiconductor substrate, the gate electrode and the floating gate in the write region. The writing source and the writing drain disposed on both sides, and a writing terminal connected to each of the writing source and the writing drain are provided. Silicon carbide semiconductor device. 8. A write gate formed on the floating gate in the write region and not electrically connected to the gate electrode in the MOS operation region, the write gate being connected to the write gate. A writing terminal;
The silicon carbide semiconductor device according to claim 6, further comprising: 9. The silicon carbide semiconductor device according to claim 7, wherein said write source is also used as said source region. 10. The writing region is electrically connected to the gate electrode extending from the MOS operation region to the writing region, and to the base region or the well region disposed below the floating gate. 7. The silicon carbide semiconductor device according to claim 6, further comprising: a second-conductivity-type writing drain that is not provided; and a writing terminal connected to the writing drain. 8. 11. The method according to claim 1, wherein in the writing area,
2. The gate insulating film according to claim 1, wherein said second gate insulating film is partially thinned.
0. The silicon carbide semiconductor device according to any one of 0. 12. The device according to claim 1, wherein the surface channel layer has an electric charge between the source electrode and the drain electrode even when no voltage is applied to the gate electrode in a state where the electric charge is not retained in the mechanism capable of retaining the electric charge. The silicon carbide semiconductor device according to claim 1, wherein electrical conduction is enabled.