JP2016195225A - Silicon carbide semiconductor device and processing method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To increase the gate threshold voltage without lowering the gain, in a silicon carbide semiconductor device.SOLUTION: A silicon carbide semiconductor device includes a first isolating layer 7a in contact with the front surface of a high concentration n-type semiconductor substrate 1, a second isolating layer 7b in contact with the surface of the first isolating layer 7a, having a bandgap smaller than that of the first isolating layer 7a, and having an electron trap in the bulk or in the interface with the first isolating layer 7a, a gate electrode 8 in contact with the surface of the second isolating layer 7b, a source electrode 9 in contact with the front surface of the high concentration n-type semiconductor substrate 1, and a drain electrode 10 in contact with the back surface of the high concentration n-type semiconductor substrate 1. An electron has been captured in the electron trap, and since the curve of the band of silicon carbide semiconductor device decreases because of an affection of electric charge of the electron, the gate threshold voltage increases.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a silicon carbide semiconductor device and a processing method thereof.

  Wide band gap semiconductors such as silicon carbide (SiC), gallium nitride (GaN), and diamond are expected to be applied to power devices due to their excellent characteristics such as high dielectric breakdown electric field and high thermal conductivity. In particular, SiC is attracting attention because an oxide film can be formed by thermal oxidation in the same manner as silicon (Si).

FIG. 9 is a cross-sectional view showing a main part of a conventional silicon carbide semiconductor device. In the SiC vertical power MOSFET (metal-oxide film-semiconductor field effect transistor) shown in FIG. 9, when a voltage higher than the threshold value is applied to the gate electrode 8 with respect to the source electrode 9, the p immediately below the gate electrode 8 is applied. An inversion layer is formed on the surface of the channel region 3. At this time, when a positive voltage is applied to the drain electrode 10 with respect to the source electrode 9, the n ⁺ source region 5, the surface inversion layer of the p channel region 3, the low concentration n-type drift region 2, and the high voltage are applied. An electron path reaching the drain electrode 10 through the n-type semiconductor substrate 1 is formed. Therefore, a current flows from the drain electrode 10 to the source electrode 9.

  On the other hand, when a voltage lower than the threshold value is applied to the gate electrode 8 with respect to the source electrode 9, the surface inversion layer in the p-channel region 3 immediately below the gate electrode 8 disappears, so that no current flows. Such a basic operation is the same as that of a MOSFET using Si, but a wide band gap semiconductor has a higher dielectric breakdown electric field than Si. For example, the breakdown electric fields of 4H—SiC, GaN and diamond are about 10 times, about 11 times and about 19 times that of Si, respectively. Therefore, in the silicon carbide semiconductor device, it is possible to increase the impurity concentration of the low-concentration n-type drift region 2 to reduce the thickness, and to realize a low on-resistance with a high breakdown voltage.

  Conventionally, there is a silicon carbide semiconductor device in which a silicon oxide film is laminated on the surface of silicon carbide and an aluminum oxide film is laminated thereon (see, for example, Patent Documents 1 to 4).

JP 2013-162073 A JP 2010-251589 A JP 2009-49099 A JP 2009-16530 A

  However, in the conventional silicon carbide semiconductor device, if the advantage that the concentration of the drift layer can be increased with respect to the Si device having the same breakdown voltage is taken advantage of, the capacitance between the gate and the drain increases. A current flows through the gate-drain capacitance by dV / dt. Since the gate voltage rises due to the voltage drop of the gate impedance due to this current, there is a problem that a phenomenon of erroneous ON that is turned ON is likely to occur despite being in the OFF state.

  In order to prevent erroneous ON, it is effective to apply a negative bias to the gate. However, in this case, a negative bias power supply is required, which causes a new problem that the cost of the control circuit increases. In addition, when a negative bias is applied to the gate, a conventional wide band gap semiconductor MOSFET including a silicon carbide semiconductor has a problem that a threshold value varies due to NBTI (Negative Bias Temperature Instability).

  On the other hand, it is effective to increase the threshold value in order to prevent erroneous ON without applying a negative bias to the gate. In the Si device, the threshold value can be increased by increasing the concentration of the channel region. On the other hand, in the SiC element, the channel mobility of the MOSFET is very low with respect to the bulk mobility, so that the channel resistance has a great influence on the on-resistance even in a high breakdown voltage element of 1200 V or higher. In addition, when the concentration of the channel region is increased, the channel mobility is further reduced, so that the merit of low on-resistance of the silicon carbide semiconductor device is reduced. Further, when the channel region is highly concentrated, the depletion layer capacitance on the semiconductor side increases. As a result, the voltage applied to the oxide film with respect to the applied gate voltage increases, resulting in a decrease in gain and a double deterioration in characteristics.

  The threshold can also be increased by increasing the thickness of the gate oxide film. However, even in that case, since the voltage sharing applied to the oxide film is increased, the gain is decreased even if the channel mobility is not decreased. FIG. 10 schematically shows how the characteristics change when the gate threshold voltage is increased.

  FIG. 10 is a schematic diagram for explaining the characteristic change when the gate threshold voltage is increased. In each of FIGS. 9A, 9B, and 9C, the vertical axis represents LogId (Id is the drain current), and the horizontal axis represents the gate voltage Vg. A characteristic diagram 101 in FIG. 10A shows a case where the gate threshold voltage is increased by increasing the concentration of the channel region. The original characteristic 102 changes like the characteristic 103 by increasing the concentration of the channel region. A characteristic diagram 111 in FIG. 10B shows the case where the gate threshold voltage is increased by increasing the thickness of the gate oxide film. The original characteristic 112 changes like the characteristic 113 by increasing the thickness of the gate oxide film. Whether the channel region is highly concentrated or the gate oxide film is thickened, the drain current change (mutual conductance), that is, the gain, with respect to the change in the gate voltage Vg decreases.

  A characteristic diagram 121 in FIG. 10C shows a case where the gate threshold voltage is increased without reducing the gain. When the gate threshold voltage is increased without reducing the gain, the change in the drain current with respect to the change in the gate voltage Vg becomes the same in the original characteristic 122 and the characteristic 123 in which the gate threshold voltage is increased. Such characteristics are desirable.

  An object of the present invention is to provide a silicon carbide semiconductor device capable of increasing the gate threshold voltage without reducing the gain and a method for processing the same, in order to eliminate the above-described problems caused by the prior art.

  In order to solve the above-described problems and achieve the object, a silicon carbide semiconductor device according to the present invention is in contact with a first insulating layer in contact with a front surface of a silicon carbide semiconductor, and a surface of the first insulating layer. And a second insulating layer having a band gap smaller than that of the first insulating layer and having an electron trap in the bulk or at the interface with the first insulating layer, and in contact with the surface of the second insulating layer A gate electrode, a source electrode in contact with the front surface of the silicon carbide semiconductor, and a drain electrode in contact with the back surface of the silicon carbide semiconductor are characterized in that electrons are trapped in the electron trap.

  According to the present invention, since the bending of the band of the silicon carbide semiconductor is reduced due to the influence of the charge of the electrons trapped in the electron trap, the channel region does not have to be highly concentrated and the gate oxide film does not have to be thick. However, the gate threshold voltage increases.

  The silicon carbide semiconductor device according to the present invention is characterized in that, in the above-described invention, the first insulating layer is made of silicon oxide, and the second insulating layer is made of aluminum oxide.

  According to the present invention, it is possible to form a relatively stable SiC-oxide film interface by thermally oxidizing SiC or POA (Post Oxidation Annealing) of deposited silicon oxide by using silicon oxide as the first insulating layer. In addition, when the second insulating layer is made of aluminum oxide, since the electron trap level is deep, emission of electrons from the electron trap at a high temperature can be suppressed.

The silicon carbide semiconductor device according to the present invention is characterized in that, in the above-described invention, the number of electrons trapped in the electron trap is 2 × 10 ¹² cm ⁻² or more and 2 × 10 ¹³ cm ⁻² or less. To do.

  According to this invention, since a sufficient number of electrons for increasing the gate threshold voltage are trapped in the electron trap, the gate threshold voltage can be increased.

  In addition, a silicon carbide semiconductor device according to the present invention includes a first insulating layer that is in contact with a front surface of the silicon carbide semiconductor, a surface that is in contact with the surface of the first insulating layer, and a band more than the first insulating layer. A second insulating layer having a small gap and having an electron trap in the bulk or at the interface with the first insulating layer, and in contact with the surface of the second insulating layer and having a band higher than that of the second insulating layer A third insulating layer having a large gap, a gate electrode in contact with the surface of the third insulating layer, a source electrode in contact with the front surface of the silicon carbide semiconductor, and a drain electrode in contact with the back surface of the silicon carbide semiconductor , And electrons are trapped in the electron trap.

  According to the present invention, since the bending of the band of the silicon carbide semiconductor is reduced due to the influence of the charge of the electrons trapped in the electron trap, the channel region does not have to be highly concentrated and the gate oxide film does not have to be thick. However, the gate threshold voltage increases.

  In the silicon carbide semiconductor device according to the present invention, in the above-described invention, the first insulating layer and the third insulating layer are made of silicon oxide, and the second insulating layer is aluminum oxide or silicon nitride. It is characterized by being made of.

  According to the present invention, the first insulating layer and the third insulating layer are made of silicon oxide, and the second insulating layer is made of aluminum oxide or silicon nitride, so that the band offset of the second insulator with respect to the electrons can be relatively reduced. It can be increased, and electrons can be prevented from escaping to the SiC or gate electrode side.

The silicon carbide semiconductor device according to the present invention is characterized in that, in the above-described invention, the number of electrons captured by the electron trap is 4 × 10 ¹¹ cm ⁻² or more and 4 × 10 ¹² cm ⁻² or less. To do.

  According to this invention, since a sufficient number of electrons for increasing the gate threshold voltage are trapped in the electron trap, the gate threshold voltage can be increased.

  The silicon carbide semiconductor device according to the present invention includes a first insulating layer in contact with the front surface of the silicon carbide semiconductor, a floating gate electrode in contact with the surface of the first insulating layer, and a surface of the floating gate electrode. A second insulating layer in contact with the gate electrode, a gate electrode in contact with the surface of the second insulating layer, a source electrode in contact with the front surface of the silicon carbide semiconductor, a drain electrode in contact with the back surface of the silicon carbide semiconductor, And electrons are stored in the floating gate electrode.

  According to the present invention, the bending of the band of the silicon carbide semiconductor is reduced due to the influence of the charge of the electrons accumulated in the floating gate electrode, so that the channel region does not have to be highly concentrated and the gate oxide film does not have to be thick. However, the gate threshold voltage increases.

  In the silicon carbide semiconductor device according to the present invention, in the above-described invention, the first insulating layer and the second insulating layer are made of silicon oxide, and the floating gate electrode is made of polycrystalline silicon. It is characterized by that.

  According to the present invention, the first and second insulating layers are made of silicon oxide, and the floating gate electrode is made of polycrystalline silicon, whereby the band offset of the second insulator with respect to electrons can be further increased. Electrons can be prevented from escaping to the SiC or gate electrode side. In addition, silicon oxide and polycrystalline silicon are advantageous for production because they are used for ordinary gate oxide films and gate electrodes.

In the silicon carbide semiconductor device according to the present invention as set forth in the invention described above, the number of electrons stored in the floating gate electrode is 4 × 10 ¹¹ cm ⁻² or more and 4 × 10 ¹² cm ⁻² or less. And

  According to the present invention, since a sufficient number of electrons are accumulated in the floating gate electrode to increase the gate threshold voltage, the gate threshold voltage can be increased.

  According to another aspect of the present invention, there is provided a first method for treating a silicon carbide semiconductor device comprising: a first insulating layer in contact with a front surface of a silicon carbide semiconductor; a first insulating layer in contact with a surface of the first insulating layer; A second insulating layer having a smaller band gap and having an electron trap in the bulk or at the interface with the first insulating layer, a gate electrode in contact with the surface of the second insulating layer, and the silicon carbide semiconductor For a silicon carbide semiconductor device comprising a source electrode in contact with the front surface and a drain electrode in contact with the back surface of the silicon carbide semiconductor, from the inversion layer of the silicon carbide semiconductor through the first insulating layer Electrons are injected by an electric field, and the electrons are captured by the electron trap.

  According to the present invention, since the bending of the band of the silicon carbide semiconductor is reduced due to the influence of the charge of the electrons trapped in the electron trap, the channel region does not have to be highly concentrated and the gate oxide film does not have to be thick. However, the gate threshold voltage increases.

  According to another aspect of the present invention, there is provided a first method for treating a silicon carbide semiconductor device comprising: a first insulating layer in contact with a front surface of a silicon carbide semiconductor; a first insulating layer in contact with a surface of the first insulating layer; And a second insulating layer having an electron trap in the bulk or at the interface with the first insulating layer, and in contact with the surface of the second insulating layer, and the second insulating layer A third insulating layer having a larger band gap, a gate electrode in contact with the surface of the third insulating layer, a source electrode in contact with the front surface of the silicon carbide semiconductor, and a back surface of the silicon carbide semiconductor. A silicon carbide semiconductor device comprising a drain electrode, wherein electrons are injected from an inversion layer of the silicon carbide semiconductor through the first insulating layer by an electric field, and the electrons are captured by the electron trap. And butterflies.

  According to the present invention, since the bending of the band of the silicon carbide semiconductor is reduced due to the influence of the charge of the electrons trapped in the electron trap, the channel region does not have to be highly concentrated and the gate oxide film does not have to be thick. However, the gate threshold voltage increases.

  According to another aspect of the present invention, there is provided a silicon carbide semiconductor device processing method comprising: a first insulating layer in contact with a front surface of a silicon carbide semiconductor; a floating gate electrode in contact with a surface of the first insulating layer; and the floating gate. A second insulating layer in contact with the surface of the electrode; a gate electrode in contact with the surface of the second insulating layer; a source electrode in contact with the front surface of the silicon carbide semiconductor; and a drain in contact with the back surface of the silicon carbide semiconductor. An electron is injected from an inversion layer of the silicon carbide semiconductor through the first insulating layer by an electric field, and the electrons are accumulated in the floating gate electrode. And

  According to the present invention, the bending of the band of the silicon carbide semiconductor is reduced due to the influence of the charge of the electrons accumulated in the floating gate electrode, so that the channel region does not have to be highly concentrated and the gate oxide film does not have to be thick. However, the gate threshold voltage increases.

  According to the silicon carbide semiconductor device and the processing method thereof according to the present invention, there is an effect that the gate threshold voltage can be increased without reducing the gain.

1 is a cross-sectional view showing a main part of a silicon carbide semiconductor device according to a first embodiment. It is a connection diagram which shows an example of the connection state in an electron injection process. It is a connection diagram which shows another example of the connection state in an electron injection process. FIG. 6 is a cross-sectional view showing a main part of a silicon carbide semiconductor device according to a second embodiment. FIG. 6 is a cross-sectional view showing a main part of a silicon carbide semiconductor device according to a third embodiment. It is a band figure in the A-A 'part of FIG. It is a band figure in the B-B 'part of FIG. FIG. 6 is a band diagram in a C-C ′ portion of FIG. 5. It is sectional drawing which shows the principal part of the conventional silicon carbide semiconductor device. It is a schematic diagram explaining the characteristic change at the time of increasing a gate threshold voltage.

  Exemplary embodiments of a silicon carbide semiconductor device and a processing method thereof according to the present invention will be explained below in detail with reference to the accompanying drawings. In this specification, it means that electrons or holes are majority carriers in the layers and regions with n or p, respectively. Further, + attached to n or p means that the impurity concentration is higher than that of a layer or region where it is not attached. Note that, in the following description of the embodiments and the accompanying drawings, the same reference numerals are given to the same components, and duplicate descriptions are omitted.

(Embodiment 1)
Silicon Carbide Semiconductor Device FIG. 1 is a cross-sectional view showing a main part of the silicon carbide semiconductor device according to the first embodiment. As shown in FIG. 1, the silicon carbide semiconductor device includes a high concentration n-type semiconductor substrate 1, a low concentration n-type drift region 2, a p channel region 3, a high concentration p base region 4, an n ⁺ source region 5, and a p ⁺ contact. The region 6 includes a first insulating layer 7a, a second insulating layer 7b, a gate electrode 8, a source electrode 9, and a drain electrode 10.

High-concentration n-type semiconductor substrate 1 is made of a silicon carbide semiconductor. The low concentration n-type drift region 2 is provided on the high concentration n-type semiconductor substrate 1 by, for example, an epitaxial growth method. High concentration n-type semiconductor substrate 1 and low concentration n-type drift region 2 are examples of a silicon carbide semiconductor. The p-channel region 3 is provided on a part of the surface on the front surface side of the low-concentration n-type drift region 2. The high concentration p base region 4 is provided between the p channel region 3 and the low concentration n-type drift region 2. Since the high-concentration p base region 4 is provided, the p-channel region 3 is punched even if a high reverse bias is applied to the p / n junction between the p-channel region 3 and the low-concentration n-type drift region 2. Through is prevented. The n ⁺ source region 5 is provided on a part of the front surface of the p channel region 3. The p ⁺ contact region 6 is provided on a part of the front surface side surface of the p channel region 3.

The first insulating layer 7 a is provided in contact with the front surfaces of the p-channel region 3 and the low-concentration n-type drift region 2 sandwiched between the n ⁺ source regions 5 in the adjacent p-channel region 3. The first insulating layer 7a may be, for example, silicon oxide (SiO ₂ ).

The second insulating layer 7b is provided in contact with the surface of the first insulating layer 7a. The second insulating layer 7b has a smaller band gap than the first insulating layer 7a. The second insulating layer 7b has an electron trap in its bulk or at the interface with the first insulating layer 7a. Electrons are captured in this electron trap. The second insulating layer 7b may be, for example, aluminum oxide (Al ₂ O ₃ ).

  The second insulating layer 7b is not limited to aluminum oxide, for example, and may be any material that has a band gap smaller than that of the first insulating layer 7a and a large activation energy of electron traps. Further, since the effect due to the charge of electrons is closer to the surface of silicon carbide, the second insulating layer 7b has an electron trap at the interface with the first insulating layer 7a even if there are few electron traps in the bulk. Any substance can be used. The same effect can be obtained by using a substance having a negative fixed charge in the film of the second insulating layer 7b or at the interface with the first insulating layer 7a as the second insulating layer 7b.

The gate electrode 8 is provided in contact with the surface of the second insulating layer 7b. Source electrode 9 is provided in contact with the surfaces of n ⁺ source region 5 and p ⁺ contact region 6. The drain electrode 10 is provided in contact with the back surface of the high concentration n-type semiconductor substrate 1.

FIG. 2 is a connection diagram illustrating an example of a connection state in the electron injection process. As shown in FIG. 2, for example, a gate negative bias power supply 22 is connected to the silicon carbide semiconductor device 21, and a positive voltage higher than a voltage necessary for turning on an element is usually set on the gate with respect to the source of the silicon carbide semiconductor device 21. Electrons may be injected into the second insulating layer 7b by applying a high voltage in a DC manner.

  FIG. 3 is a connection diagram illustrating another example of a connection state in the electron injection process. As shown in FIG. 3, for example, a gate negative bias pulse power supply 23 is connected to the silicon carbide semiconductor device 21, and a positive voltage higher than a voltage necessary for normally turning on the element at the gate with respect to the source of the silicon carbide semiconductor device 21. Electrons may be injected into the second insulating layer 7b by applying a high voltage in a pulsed manner. The pulse may be single or continuous.

  In the connection between the silicon carbide semiconductor device 21 and the gate negative bias power source 22 or the gate negative bias power source 23, the drain may be short-circuited with the source as shown in FIG. 2, or the drain may be connected as shown in FIG. It may be open. Electrons need only be injected into the p-channel region 3 connected to the source, and it is not always necessary to inject electrons into the low-concentration n-type drift region 2 connected to the drain. It is desirable from the viewpoint of the reliability of the oxide film.

(Embodiment 2)
Silicon Carbide Semiconductor Device FIG. 4 is a cross-sectional view showing the main part of the silicon carbide semiconductor device according to the second embodiment. As shown in FIG. 4, the silicon carbide semiconductor device has a third insulating layer 7 c between the second insulating layer 7 b and the gate electrode 8. That is, the third insulating layer 7c is provided in contact with the surface of the second insulating layer 7b. The gate electrode 8 is provided in contact with the surface of the third insulating layer 7c. Other configurations are the same as those of the first embodiment.

The third insulating layer 7c has a larger band gap than the second insulating layer 7b. The third insulating layer 7c may be, for example, silicon oxide (SiO ₂ ). As described above, the second insulating layer 7b is sandwiched between the first insulating layer 7a and the third insulating layer 7c having a larger band gap, so that the electron traps of the second insulating layer 7b are heated at a high temperature. Even when excited by the conduction band of the second insulating layer 7b, it cannot easily escape to the gate electrode 8 or the silicon carbide semiconductor side. Therefore, the silicon carbide semiconductor device can be used up to a higher temperature.

  Since the second insulating layer 7b is sandwiched between the first insulating layer 7a and the third insulating layer 7c having a band gap larger than that of the second insulating layer 7b, the second insulating layer 7b needs to be a substance having a deep electron trap. There is no. The second insulating layer 7b is an insulator having a band gap smaller than that of the first insulating layer 7a or the third insulating layer 7c, for example, a band on the conduction band side with respect to the first insulating layer 7a or the third insulating layer 7c. An insulator having a negative offset may be used. For example, when the first insulating layer 7a and the third insulating layer 7c are silicon oxide, the second insulating layer 7b may be, for example, silicon nitride.

  The first insulating layer 7a and the third insulating layer 7c are not limited to silicon oxide, for example, and may be any insulator that has a positive band offset on the conduction band side with respect to the second insulating layer 7b. Further, the first insulating layer 7a and the third insulating layer 7c may be the same material or different materials. The larger the band offset on the conduction band side of the first insulating layer 7a with respect to the silicon carbide semiconductor, the smaller the deterioration of the oxide film due to the tunnel current during normal use. Therefore, it is advantageous in terms of reliability that the first insulating layer 7a is an insulator having a large band offset on the conduction band side with respect to the silicon carbide semiconductor.

-Electron injection process to silicon carbide semiconductor device As described in the first embodiment, electrons may be injected into the second insulating layer 7b in the connection state shown in FIG. 2 or FIG.

(Embodiment 3)
Silicon Carbide Semiconductor Device FIG. 5 is a cross-sectional view showing the main parts of the silicon carbide semiconductor device according to the third embodiment. As shown in FIG. 5, the silicon carbide semiconductor device has a floating gate electrode 11 between the first insulating layer 7a and the second insulating layer 7b. That is, the floating gate electrode 11 is provided in contact with the surface of the first insulating layer 7a. The second insulating layer 7 b is provided in contact with the surface of the floating gate electrode 11. Other configurations are the same as those of the first embodiment.

  The floating gate electrode 11 may be, for example, polycrystalline silicon. For example, when the first insulating layer 7a and the second insulating layer 7b are made of silicon oxide and the floating gate electrode 11 is made of polycrystalline silicon, the band offset between the silicon carbide semiconductor and silicon oxide is changed between polycrystalline silicon and silicon oxide. Is smaller than the band offset. Accordingly, electrons are relatively easily injected and accumulated in the conductive floating gate electrode 11, but cannot escape from the floating gate electrode 11. Therefore, the silicon carbide semiconductor device can be used up to a higher temperature.

-Electron injection process to silicon carbide semiconductor device As described in the first embodiment, electrons may be injected into the second insulating layer 7b in the connection state shown in FIG. 2 or FIG.

  As described above, according to each embodiment, the band of the silicon carbide semiconductor is bent due to the influence of the charge of electrons trapped in the electron trap or the influence of the charge of electrons accumulated in the floating gate electrode. Get smaller. Therefore, the gate threshold voltage increases without increasing the concentration of the channel region and without increasing the thickness of the gate oxide film. Therefore, the gate threshold voltage can be increased without reducing the gain.

Example 1
In the silicon carbide semiconductor device described in the first embodiment, the first insulating layer 7a is thin, for example, silicon oxide having a thickness of 10 nm to 50 nm, and the second insulating layer 7b is relatively thick, for example, 50 nm to 100 nm. It is assumed that the thickness is aluminum oxide.

  FIG. 6 is a band diagram in the A-A ′ portion of FIG. 1. A-A ′ reaches the p-channel region 3 and the high-concentration p-base region 4 from the gate electrode 8 through the second insulating layer 7 b and the first insulating layer 7 a.

  A band diagram 131 in FIG. 6A shows a state without bias. A band diagram 132 in FIG. 6B shows a state in which a positive voltage Vth1 is applied to the gate electrode 8 to thereby form an inversion layer in the p-channel region 3, that is, a state in the vicinity of the gate threshold value. A band diagram 133 in FIG. 6C shows a state in which a larger positive voltage Vgi is applied to the gate electrode 8.

  As shown in the band diagram 133 of FIG. 6C, even when a larger voltage is applied to the gate electrode 8 with the inversion layer formed in the p-channel region 3, the charge of the inversion layer only increases. Therefore, the bending of the band on the silicon carbide side does not change greatly, and most of the voltage is applied to the silicon oxide that is the first insulating layer 7a and the aluminum oxide that is the second insulating layer 7b. Since the electric field strength of the aluminum oxide portion having a large dielectric constant is small, a large voltage is applied to the silicon oxide even if the silicon oxide is thin. For this reason, electrons in the inversion layer tunnel to the conduction band of silicon carbide due to the strong electric field in silicon oxide, and further flow through the conduction band of aluminum oxide, and some of the electrons are trapped in the electron trap of aluminum oxide. Is done.

  A band diagram 134 in FIG. 6D shows a state in which more electrons are tunneled and more electrons are trapped in an aluminum oxide electron trap, and the gate bias is zero in that state. The state of the band diagram 134 in FIG. 6D is smaller in the bending of the silicon carbide band due to the influence of the charge of the electrons trapped in the aluminum oxide than the state of the band diagram 131 in FIG. Become.

  In the band diagram 135 of FIG. 6E, a positive voltage Vth2 for forming an inversion layer on the surface of silicon carbide is applied to the gate electrode 8 in a state where many electrons are trapped in the electron trap of aluminum oxide. Indicates the state. As shown in the band diagram 134 of FIG. 6D, since the bending of the original silicon carbide band is small, the relationship of Vth1 <Vth2, that is, the gate threshold value increases.

  Similarly, when there is a relatively deep electron trap at the interface between the silicon carbide semiconductor and the silicon oxide, the gate threshold can be increased. However, when electrons are trapped at the interface between the silicon carbide semiconductor and silicon oxide, channel mobility is reduced due to Coulomb scattering caused by the charges. On the other hand, in Example 1, since the charge is away from the interface between the silicon carbide semiconductor and silicon oxide, the channel mobility does not decrease. It is known that charges trapped in aluminum oxide are not detrapped even at high temperatures. Therefore, it is convenient for application to a silicon carbide semiconductor device that can be used at high temperatures.

  In the process of injecting electrons, electrons may be trapped in the electron traps in the silicon oxide. However, since the electron trap of silicon oxide has many levels having relatively small activation energy, the electrons trapped in the electron trap in silicon oxide can be removed by annealing.

  The amount of increase ΔVth required for the threshold value Vth needs to be about 1 V or more, for example, about 10 V at the maximum because a sufficient effect cannot be obtained if it is 1 V or less. Assuming that charges are accumulated only in the region of the second insulating layer 7b, the amount of change ΔVth in the threshold due to the charges in the insulating film is expressed by the following equation (1). Where Qeff is the effective charge amount, t is the thickness of the second insulating layer 7b, and ε is the dielectric constant of the second insulating layer 7b.

  ΔVth = Qeff · t / ε (1)

Assuming that charges are uniformly distributed in the second insulating layer 7b, the effective charge amount Qeff is ½ of the charge amount Q in the second insulating layer 7b. If the thickness t of the second insulating layer 7b is 50 nm, that is, 5 × 10 ⁻⁶ cm, and the relative dielectric constant ε of the second insulating layer 7b is 9, the charge required to increase the threshold by 1V The quantity Q (1V) is obtained by the calculation formula (2).

Q (1V) = 2ε / t
= 2 × 9 × 8.85 × 10 ⁻¹⁴ / (5 × 10 ⁻⁶ )
≒ 3 × 10 ^-7 [C] (2)

Assuming that the elementary charge q of electrons is 1.602 × 10 ⁻¹⁹ , the number n of electrons trapped in the electron trap can be obtained by the calculation formula (3).

n = Q / q≈2 × 10 ¹² [cm ⁻² ] (3)

Therefore, the number of electrons required to increase the threshold by 10 V is about 2 × 10 ¹³ [cm ⁻² ].

(Example 2)
In the silicon carbide semiconductor device described in Embodiment 2, it is assumed that first insulating layer 7a and third insulating layer 7c are silicon oxide, and second insulating layer 7b is aluminum oxide.

  FIG. 7 is a band diagram in the B-B ′ portion of FIG. 4. B-B ′ reaches the p-channel region 3 and the high-concentration p base region 4 from the gate electrode 8 through the third insulating layer 7 c, the second insulating layer 7 b, and the first insulating layer 7 a.

  A band diagram 141 in FIG. 7A shows a state without bias. A band diagram 142 in FIG. 7B shows a state in which electrons are tunneled and trapped in an aluminum oxide electron trap, which is the second insulating layer 7b, and the gate bias is zero in this state. The state of the band diagram 142 in FIG. 7B is smaller in the bending of the silicon carbide band due to the influence of the electric charge trapped in the aluminum oxide than the state of the band diagram 141 in FIG. Become. Therefore, the gate threshold value increases as in the first embodiment.

  As in the first embodiment, it is assumed that the increase amount ΔVth required for the threshold value Vth is about 1 V or more, and about 10 V at the maximum. When the thickness of the second insulating layer 7b is ignored, the thickness of the third insulating layer 7c is t, and the relative dielectric constant of the third insulating layer 7c is ε, the above equation (1) is established. However, since the charges are concentrated on the second insulating layer 7b, the effective charge amount Qeff is equal to the charge amount Q in the second insulating layer 7b.

When the thickness t of the third insulating layer 7c is 50 nm, that is, 5 × 10 ⁻⁶ cm, and the relative dielectric constant ε of the third insulating layer 7c is 3.9, it is necessary to increase the threshold value by 1V. A sufficient charge amount Q (1 V) is obtained by the calculation formula (4).

Q (1V) = ε / t
= 3.9 × 8.85 × 10 ⁻¹⁴ / (5 × 10 ⁻⁶ )
≒ 7 × 10 ^-8 [C] (4)

Assuming that the elementary charge q of electrons is 1.602 × 10 ⁻¹⁹ , the number n of electrons trapped in the electron trap can be obtained by the formula (5).

n = Q / q≈4 × 10 ¹¹ [cm ⁻² ] (5)

Therefore, the number of electrons required to increase the threshold by 10 V is about 4 × 10 ¹² [cm ⁻² ].

Example 3
In the silicon carbide semiconductor device described in the third embodiment, it is assumed that first insulating layer 7a and second insulating layer 7b are silicon oxide, and floating gate electrode 11 is n-type polycrystalline silicon.

  FIG. 8 is a band diagram in the C-C ′ portion of FIG. 5. C-C ′ extends from the gate electrode 8 to the p-channel region 3 and the high-concentration p base region 4 through the second insulating layer 7 b, the floating gate electrode 11, and the first insulating layer 7 a.

  A band diagram 151 in FIG. 8A shows a state when there is no bias. A band diagram 152 in FIG. 8B shows a state in which electrons are tunneled to accumulate electrons in the floating gate electrode 11 and the gate bias is zero in this state. The state of the band diagram 152 in FIG. 8B is compared with the state of the band diagram 151 in FIG. 8A, and the bending of the silicon carbide band is affected by the charge of the electrons accumulated in the floating gate electrode 11. Get smaller. Therefore, the gate threshold value increases as in the first embodiment.

  As in the first embodiment, it is assumed that the increase amount ΔVth required for the threshold value Vth is about 1 V or more, and about 10 V at the maximum. If the thickness of the floating gate electrode 11 is ignored, the thickness of the second insulating layer 7b is t, and the relative dielectric constant of the second insulating layer 7b is ε, the above equation (1) holds. However, since the charges are concentrated on the floating gate electrode 11, the effective charge amount Qeff is equal to the charge amount Q in the floating gate electrode 11.

Necessary for raising the threshold value by 1 V when the thickness t of the second insulating layer 7b is 50 nm, that is, 5 × 10 ⁻⁶ cm, and the relative dielectric constant ε of the second insulating layer 7b is 3.9. A simple charge amount Q (1 V) is obtained by the calculation formula (4). The number n of electrons accumulated in the floating gate electrode 11 can be obtained by the calculation formula (5).

Therefore, the number of electrons required to increase the threshold by 10 V is about 4 × 10 ¹² [cm ⁻² ].

  As described above, the present invention is not limited to the above-described embodiment, and various modifications can be made. For example, the dimensions and concentrations described in the embodiments are examples, and the present invention is not limited to these values.

  As described above, the silicon carbide semiconductor device and the processing method thereof according to the present invention are useful for wide band gap power semiconductors used for inverters, switching power supplies, and the like, and are particularly suitable for silicon carbide semiconductor devices.

DESCRIPTION OF SYMBOLS 1 High concentration n-type semiconductor substrate 7a 1st insulating layer 7b 2nd insulating layer 7c 3rd insulating layer 8 Gate electrode 9 Source electrode 10 Drain electrode 11 Floating gate electrode

Claims (12)

A first insulating layer in contact with the front surface of the silicon carbide semiconductor;
A second insulating layer that is in contact with the surface of the first insulating layer, has a band gap smaller than that of the first insulating layer, and has an electron trap in the bulk or at the interface with the first insulating layer;
A gate electrode in contact with the surface of the second insulating layer;
A source electrode in contact with the front surface of the silicon carbide semiconductor;
A drain electrode in contact with the back surface of the silicon carbide semiconductor;
With
A silicon carbide semiconductor device, wherein electrons are trapped in the electron trap.   The silicon carbide semiconductor device according to claim 1, wherein the first insulating layer is made of silicon oxide, and the second insulating layer is made of aluminum oxide. 3. The silicon carbide semiconductor device according to claim 2, wherein the number of electrons trapped in the electron trap is 2 × 10 ¹² cm ⁻² or more and 2 × 10 ¹³ cm ⁻² or less. A first insulating layer in contact with the front surface of the silicon carbide semiconductor;
A second insulating layer that is in contact with the surface of the first insulating layer, has a band gap smaller than that of the first insulating layer, and has an electron trap in the bulk or at the interface with the first insulating layer;
A third insulating layer in contact with the surface of the second insulating layer and having a larger band gap than the second insulating layer;
A gate electrode in contact with the surface of the third insulating layer;
A source electrode in contact with the front surface of the silicon carbide semiconductor;
A drain electrode in contact with the back surface of the silicon carbide semiconductor;
With
A silicon carbide semiconductor device, wherein electrons are trapped in the electron trap.   The silicon carbide according to claim 4, wherein the first insulating layer and the third insulating layer are made of silicon oxide, and the second insulating layer is made of aluminum oxide or silicon nitride. Semiconductor device. 6. The silicon carbide semiconductor device according to claim 5, wherein the number of electrons trapped in the electron trap is 4 × 10 ¹¹ cm ⁻² or more and 4 × 10 ¹² cm ⁻² or less. A first insulating layer in contact with the front surface of the silicon carbide semiconductor;
A floating gate electrode in contact with the surface of the first insulating layer;
A second insulating layer in contact with the surface of the floating gate electrode;
A gate electrode in contact with the surface of the second insulating layer;
A source electrode in contact with the front surface of the silicon carbide semiconductor;
A drain electrode in contact with the back surface of the silicon carbide semiconductor;
With
A silicon carbide semiconductor device, wherein electrons are accumulated in the floating gate electrode.   The silicon carbide semiconductor device according to claim 7, wherein the first insulating layer and the second insulating layer are made of silicon oxide, and the floating gate electrode is made of polycrystalline silicon. 9. The silicon carbide semiconductor device according to claim 8, wherein the number of electrons accumulated in the floating gate electrode is 4 × 10 ¹¹ cm ⁻² or more and 4 × 10 ¹² cm ⁻² or less. A first insulating layer in contact with the front surface of the silicon carbide semiconductor;
A second insulating layer that is in contact with the surface of the first insulating layer, has a band gap smaller than that of the first insulating layer, and has an electron trap in the bulk or at the interface with the first insulating layer;
A gate electrode in contact with the surface of the second insulating layer;
A source electrode in contact with the front surface of the silicon carbide semiconductor;
A drain electrode in contact with the back surface of the silicon carbide semiconductor;
For silicon carbide semiconductor devices comprising
A processing method for a silicon carbide semiconductor device, wherein electrons are injected from an inversion layer of the silicon carbide semiconductor through the first insulating layer by an electric field, and the electrons are captured by the electron trap. A first insulating layer in contact with the front surface of the silicon carbide semiconductor;
A second insulating layer that is in contact with the surface of the first insulating layer, has a band gap smaller than that of the first insulating layer, and has an electron trap in the bulk or at the interface with the first insulating layer;
A third insulating layer in contact with the surface of the second insulating layer and having a larger band gap than the second insulating layer;
A gate electrode in contact with the surface of the third insulating layer;
A source electrode in contact with the front surface of the silicon carbide semiconductor;
A drain electrode in contact with the back surface of the silicon carbide semiconductor;
For silicon carbide semiconductor devices comprising
A processing method for a silicon carbide semiconductor device, wherein electrons are injected from an inversion layer of the silicon carbide semiconductor through the first insulating layer by an electric field, and the electrons are captured by the electron trap. A first insulating layer in contact with the front surface of the silicon carbide semiconductor;
A floating gate electrode in contact with the surface of the first insulating layer;
A second insulating layer in contact with the surface of the floating gate electrode;
A gate electrode in contact with the surface of the second insulating layer;
A source electrode in contact with the front surface of the silicon carbide semiconductor;
A drain electrode in contact with the back surface of the silicon carbide semiconductor;
For silicon carbide semiconductor devices comprising
A processing method for a silicon carbide semiconductor device, wherein electrons are injected from an inversion layer of the silicon carbide semiconductor through the first insulating layer by an electric field and accumulated in the floating gate electrode.

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