JPH02188967A - Semiconductor device - Google Patents

Abstract

PURPOSE:To reduce the leak current of a semiconductor device so as to improve the resistance characteristics of the device by forming a shield layer having a conductivity type which is different from that of a semiconductor substrate at the boundary section between a Schottky metal area other than a Schottky junction forming area controlled by a gate electrode and the semiconductor substrate. CONSTITUTION:This semiconductor device is provided with a semiconductor substrate 1 of the first conductivity type in which a drain area 2 is formed, Schottky metal area 3 formed in the main surface of the substrate 1 and forms a Schottky junction at part of the substrate 1 and, at the same time, functions as a source area, gate electrode 5 which is provided against the Schottky junction through an insulating film 4 and controls the tunnel current of the junction, and shield layer 6 of the second conductivity type formed at the boundary section between the Schottky metal area 3 other than the above-mentioned Schottky junction forming area controlled by the electrode 5 and the substrate 1. Therefore, the leak current at the shield section is remarkably reduced, since the leak current is produced at the p-n junction formed by the shield layer and substrate.

Description

[Detailed Description of the Invention] [Objective of the Invention] (Industrial Application Field) This invention mainly aims at controlling the tunneling phenomenon by modulating the thickness of the energy barrier of the Schottky junction by the electric field from the insulated gate electrode. The present invention relates to a semiconductor device that controls current.

(Prior Art) A semiconductor device based on the above principle will be referred to as a Schottky tunnel transistor. An example of such a conventional Schottky tunnel transistor is the one shown in FIG. 12 (Japanese Unexamined Patent Publication No. 62-274775). In the same figure (a), 101 is an n-type semiconductor substrate, and its main surface has an n+ region 10 corresponding to a drain region.
A Schottky metal 103 is formed at an appropriate distance from the n+ region 102 to form a Schottky junction with the n-type semiconductor substrate 101 and to function as a source region. And n+ region 102
semiconductor substrate 10 between and Schottky metal 103
A gate electrode 105 is formed on the substrate 1 with a gate insulating film 104 interposed therebetween.

(b) to ('e) in FIG. 12 are drain regions n
“The bias state for the region 102 and the gate electrode 105 and the corresponding band diagram of the Schottky junction are shown.

As shown in (b) and (c) of the same figure, the gate voltage VG-0
When , the Schottky barrier φ in the Schottky junction
When the thickness W of B is large and the drain voltage VD-0 or VO>O where the Schottky junction is reverse biased, no current flows. As shown in the figure (d), when VO>O, the Schottky junction is strongly bent by the electric field from the gate electrode 105 and the thickness W becomes thinner, so when VD>0, electrons are transferred to the Schottky metal 103 due to the tunnel effect. from semiconductor substrate 10
A tunnel current flows through the Schottky junction in the direction of one side from the drain region to the source region. VG-0, V
When D<0(7) ((e) in the same figure), the Schottky junction becomes forward biased, and a large number of electrons move from the semiconductor substrate 101 to the Schottky metal 10/3 side, causing a forward current to flow.

Since the magnitude of the tunnel current described above can be changed by changing the gate voltage VG, this phenomenon can be utilized as a transistor. Schottky tunnel transistors that utilize this phenomenon are similar to ordinary MOSFETs.
Compared to ET, bunch-through does not occur, so it is expected to be used as a future fine functional device.

(Problem to be Solved by the Invention) By the way, in a normal MOSFET, the pn junction barrier between the source region and the substrate region is about several thousand amperes thick, so when the gate voltage is 0 and the reverse bias is applied, the pn junction Only the diffusion current flows through, and the leakage current becomes small. On the other hand, the leakage current IL of the Schottky junction when reverse biased at VG-0 is thermionic emission exceeding the triangular potential, as shown in FIG. 12(c), so IL b exp (- φB/kT) (k: Boltzmann constant, T: absolute temperature), it increases exponentially as the temperature rises.

On the other hand, in the conventional Schottky tunnel transistor, the area of the Schottky junction where the tunnel current is controlled by the gate voltage VG is only a part near the main surface of the semiconductor substrate 101; , a semiconductor substrate 101 and a Schottky metal 103
It is formed in a relatively wide area where it touches. For this reason, when the temperature rises or when the drain voltage VO is increased, the leakage current of the Schottky junction increases, and since the drain voltage is directly applied to the Schottky junction, the curve of the triangular potential of that junction becomes steeper, resulting in an equivalent Schottky junction. This causes a decrease in the barrier φB, which also causes a problem in that leakage current increases and breakdown voltage decreases.

The present invention has been made to solve these conventional problems.The present invention has been made in order to solve these conventional problems. An object of the present invention is to provide a semiconductor device that can reduce leakage current and improve breakdown voltage characteristics by forming a shield layer.

[Structure of the Invention] (Means for Solving the Problems) In order to solve the above problems, the present invention includes a semiconductor substrate of a first conductivity type in which a drain region is formed, and a semiconductor substrate formed on the main surface of the semiconductor substrate. a Schottky metal that forms a Schottky junction in part with the semiconductor substrate and functions as a source region; a gate electrode that is provided to the Schottky junction via an insulating film and controls a tunnel current of the Schottky junction; The object of the present invention is to include a second conductivity type shield layer formed at a boundary between the Schottky metal and the semiconductor substrate in a region other than the controlled Schottky junction formation region.

(Function) A Schottky junction is formed by directly bonding the Schottky metal to the semiconductor substrate of the first conductivity type only in a required part,
The tunnel current of this Schottky junction is varied by the gate voltage to perform a transistor function.

The Schottky junction is limited only to the region controlled by the gate electrode, and the Schottky metal surface other than the region where the Schottky junction is formed is shielded by a shield layer of the second conductivity type. Therefore, leakage current in this shield portion occurs at the pn junction formed between the shield layer and the semiconductor substrate, and is significantly reduced.

In this way, the Schottky junction is limited to only the required small area, and the leak bus is almost completely cut off on the other Schottky metal surfaces due to the formation of the shield layer.
Leakage current is significantly reduced. Furthermore, this leakage current is hardly affected by temperature characteristics or drain voltage VD.

(Example) Hereinafter, a Schottky tunnel transistor which is an example of the present invention will be described based on the drawings.

1 to 4 are diagrams showing a first embodiment of the present invention.

First, the basic structure and operation of this embodiment will be explained using FIGS. 1 and 2.

In FIG. 1, 1 is an n-type semiconductor substrate, 2 is an n'' drain region, 3 is a Schottky metal that forms a Schottky junction with the semiconductor substrate 1 only in a necessary part and functions as a source region, and A gate electrode 5 is formed on the semiconductor substrate 1 between the drain region 2 and the Schottky metal 3 via a gate insulating film 4. Here, the necessary part for forming the Schottky junction is A- A
It refers to the boundary between the semiconductor substrate 1 and the Schottky metal 3 perpendicular to the line. Furthermore, in this embodiment, a shield layer is formed on the surface of the Schottky metal 3 other than in the A-A direction, that is, on the boundary between the Schottky metal 3 and the semiconductor substrate 1 other than the area where the Schottky junction controlled by the gate electrode 5 is formed. A p-type shield diffusion layer 6 is formed.

Next, the operation of the Schottky tunnel transistor constructed as described above will be explained using FIGS. 2(a) and 2(b). 2(a) shows a band diagram of the Schottky junction at the AA cross section in FIG. 1, and FIG. 2(b) shows the band diagram of the Schottky junction formed by the shield diffusion layer 6 and the semiconductor substrate 1 at the BB cross section. This shows a band diagram of a pn junction, etc.

First, at the Schottky junction on the A-A side, the gate voltage V
When the drain voltage vO>0 at G-0, that is, when the Schottky junction is reverse biased and off, a tunnel current flows as a leakage current through the triangular potential of the Schottky junction, but due to the existence of the shield diffusion layer 6, In a Schottky junction, the curvature of the depletion layer becomes large, which alleviates electric field concentration, and the Schottky junction area is small, so leakage current becomes negligible. When vO>0 and VD>O, the triangular potential becomes steeper and a larger tunnel current flows to turn on, and the magnitude of this tunnel current changes depending on the gate voltage VG.

On the other hand, in the formation part of the shield diffusion layer 6 on the B-B side, the second
As shown in Figure (b), the junction between the Schottky metal 3 and the p-type shield diffusion layer 6 forms an ohmic contact and no triangular potential is formed, so no tunnel current flows.

The leakage current flows between the shield diffusion layer 6 and the semiconductor substrate 1.
This occurs at the pn junction formed by the However, the leakage current in this portion is at a low level that causes almost no problem, as in a normal pn junction. The level of this leakage current remains the same even when the drain voltage VD is increased.

As described above, in this embodiment, by forming the shield diffusion layer 6 of a conductivity type different from that of the semiconductor substrate 1, the gate electrode 5
Since the leakage path at the boundary between the Schottky metal and the semiconductor substrate 1 other than the formation region of the Schottky junction controlled by the temperature control, that is, the leakage path other than the channel corresponding part, is cut, the leakage current is significantly reduced. There is almost no influence from characteristics or drain voltage VD.

Next, FIG. 3 shows the specific configuration of this embodiment.

The semiconductor substrate 1 is made of low concentration n-type Si, and the Schottky metal 3 is made of tungsten. Furthermore, the gate electrode 5 is made of polycrystalline S1. The Schottky metal 3 is formed so as to dig into the Si that is the semiconductor substrate 1 and wrap around under the gate electrode 5 . 7 is an insulating film, 8 is a gate sidewall insulating film, 9 is a source electrode, 10 is a drain electrode, and 11 is an interlayer insulating film. In the example shown in the figure, the Schottky metal 3 is also formed between the drain electrode 10 and the B+ drain region 2, but the Schottky metal 3 in this part is simply used as a connecting metal between the drain electrode 10 and the B+ drain region 2. It is being

The Schottky tunnel transistor of this embodiment is specifically constructed as described above, and the Schottky metal 3 functioning as a source region is formed so as to extend under the gate electrode 5. In a Schottky tunnel transistor, since the thickness of the Schottky barrier is modulated by the gate voltage, it is desirable that there be no offset between the gate electrode 5 and the Schottky junction, but in this configuration, the offset is zero. Therefore, the gate voltage is applied directly to the Schottky junction via the gate insulating film 4, and the on-resistance can be made extremely small. Moreover, the P+ shield diffusion layer 6 is
As will be described later, it is formed in a self-aligned manner using the gate sidewall insulating film 8 as a mask, and covers the Schottky metal surface other than the formation region of the Schottky junction that functions as a channel, so that leakage current can be minimized. .

Next, an example of the manufacturing process of a Schottky tunnel transistor having the above-described specific configuration is shown in FIGS. 4(a) to 4(e).
Explain using. In addition, in the following explanation, (a)
Each item symbol of - (e) corresponds to (a) - (e) of FIG. 4, respectively.

(a) On the surface of the semiconductor substrate 1 made of n-type St, a 5i02 film, which will become the gate insulating film 4, is grown to a predetermined thickness by thermal oxidation, and the areas other than the element formation region are oxidized thickly.

(b) After depositing polycrystalline Si, which will become the gate electrode 5, to a required thickness, a 5t02 film, which will become the insulating film 7, is grown, and an Si3N4 film 12, which will become a mask for oxidation and ion implantation, is deposited thereon. Thereafter, the gate electrode 5 is patterned by dry etching, and the polycrystalline Si on the side surfaces thereof is thermally oxidized again.

(C) After forming a mask of photoresist film 13, B+ drain region 2 is formed by ion implantation.

(d) After depositing a 5102 film on one surface using the CVD method, the CV'DSi02 film is etched on the other parts using the RIE (reactive ion etching) method, leaving the gate sidewall insulating film 8.
Remove the membrane. Next, gate sidewall insulating film 8 and polycrystalline S
A P+ shield diffusion layer 6 is formed by B+ ion implantation using the gate electrode 5 of i as a mask.

(e) Using the gate sidewall insulating film 8 as a mask, a part of the thin 5i02 film on the B+ drain region 2 and the P+ shield diffusion layer 6 is opened, and tungsten, which will become the Schottky metal 3, is selectively grown. At this time, by appropriately selecting the growth conditions, it is possible to make the tungsten penetrate laterally from the opening and reach the bottom of the gate electrode 5.

Since tungsten does not react with 5to2 but only with SL, it can be embedded in the shape shown in the figure.

Finally, a PSG film is deposited as an interlayer insulating film 11, and contact holes are opened to form a source electrode 9 and a drain electrode 10.
The structure shown in FIG. 3 can be obtained by connecting with an upper electrode such as .

Next, FIGS. 5 to 9 show a second embodiment of the present invention.

This embodiment is a Schottky tunnel transistor with a vertical structure that is suitable for high voltage and large current applications.

In FIGS. 5 to 9 and FIG. 10 showing the third embodiment described later, the same or equivalent parts and parts as in FIG. The explanation given will be omitted.

In FIG. 5, 14 is an n''' board, and this B+ board 14
An n-type low concentration region 1 corresponding to the n-type semiconductor substrate in the first embodiment is formed thereon, and a plurality of Schottky metals 3, P+ shield diffusion layers 6, A gate insulating film 4, a gate electrode 5, etc. are formed, and a drain electrode 15 is provided on the back surface of the n-type substrate 14, thereby forming a vertical Schottky tunnel transistor. 16 is a field insulating film, 17 is a gate electrode,
18 is a source electrode.

The p+ shield diffusion layer 6 extends over the entire bottom of the Schottky metal 3 and protrudes deeply into the n-type paper concentration region 1. The gate electrode 5 regularly surrounds the Schottky metal 3,
The surrounded unit transistors (hereinafter referred to as cells 20) are connected in parallel to each other so that a large current can be drawn.

6(a) and 6(b) respectively show examples of patterns of the cells 20, FIG. 6 @) shows an example of a mesh-like cell pattern, and FIG. 6(b) shows an example of a striped-like cell pattern. It shows. Note that the cell pattern is not limited to these, and the shape of each cell 20 may be polygonal, circular, or the like. By adopting these cell structures, channels (
The width of the Schottky junction increases, the on-resistance decreases, and a large current can be taken. Further, the outermost periphery of the cell group is surrounded by a field ring 19 to prevent electric field from concentrating on surrounding cells.

Next, the operation of the vertical structure Schottky tunnel transistor configured as described above will be explained.

First, the off state will be described using (a), (b), and (c) in FIG. When VD>01VG≦0, it is in an off state. At this time, as shown in FIG. 7(a), the 1-poor layer 21 spreads deeply into the low concentration region 1, and as shown in the potential diagram of FIG. 7(c), no electrons are emitted from the Schottky metal 3. . If the distance between the Schottky metals 3 of adjacent cells 20 is made sufficiently small (L<X/2) compared to the depletion layer width X that extends when the required withstand voltage is applied, a high voltage can be applied to the drain electrode 15. When this happens, Figure 7 (
As shown in b), the surface layer facing the channel is completely depleted and the surface electric field is relaxed. This can prevent an increase in leakage current near the channel and a decrease in breakdown voltage.

The deeper the p+ shield diffusion layer 6 is, the more the depletion layer 21 can extend into the bulk of the low concentration region 1, which is advantageous in terms of breakdown voltage. The effect of this can be obtained. The field ring 19 surrounding the outer periphery of the cell 20 is provided to terminate the depletion layer 21 with a gentle curvature, and may be provided in two or three layers depending on the required breakdown voltage.

Next, the on state will be described using (a), (b), and (c) of FIG. It is turned on when VO>01VG>0. At this time, the gate voltage VG strongly acts on the Schottky junction in the surface portion and reduces the thickness of the Schottky barrier. That is, the triangular potential is made steeper. the result,
As shown in FIG. 8(c), a tunnel current flows from the Schottky metal 3 to the low concentration region 1. In this example, n+
Since the back surface of the substrate 14, that is, the back surface of the semiconductor wafer is used as the drain, and the region corresponding to the source of the cell structure and the gate electrode 5 are arranged in high density on the front side, the number of current paths increases, and as a result, low on-resistance is achieved. be able to.

Note that in the configuration of this embodiment described above, the n+ substrate 1
4 may be replaced with a p+ substrate. When replaced in this way, minority carriers are injected into the n- low concentration region 1 when conductive (VG>O), causing conductivity modulation, so that a lower on-resistance can be realized. In particular, when trying to obtain a withstand voltage of several hundred volts or more, the resistance of the n- low concentration region 1 comes to dominate the on-resistance of the device, so replacing it with a p+ substrate effectively provides a low on-resistance.

Next, an example of the manufacturing process of the above-mentioned vertical structure Schottky tunnel transistor will be explained using FIGS. 9(a) to 9(g). Note that the numerical examples below are examples when trying to satisfy the specifications of drain-source breakdown voltage≧100V and gate breakdown voltage≧20V.

(a) n-low concentration region 1 is 1.5Ωcm, 15μm, n
Prepare n″″/n+ wafers in which the + substrate 14 uses Sl of 0.01 Ωcm and 600 μm, and the surface
After forming a 5IO2 film by thermal oxidation to a human thickness, the p+ field ring 19 was formed with a p+ surface concentration of 10''7cm3.
Selectively diffuse so that xJw is about 5gm.

(b) Photo-etch the 5102 film in the active region, and oxidize and grow a new 5io2 film, which will become the gate insulating film 4, to a thickness of about 1000 on that part.

(c) After depositing polycrystalline SL, which will become the gate electrode 5, to a thickness of 6,000 mm, a 5i02 film, which will become the insulating film 7, is deposited on top of it to a thickness of 6,000 nm.
5i3 grown to a thickness of 0.00 people and further used as a mask
Deposit N41[122 to a thickness of 500 mm. Thereafter, the gate electrode 5 is patterned by dry etching, and the polycrystalline SL on the side surface thereof is thermally oxidized again to a thickness of about 100 OA.

(d) After depositing a Si 02 film to a thickness of about 500 OA over the entire surface by CVD, sidewalls 5i02 as gate sidewall insulating films 8 are formed by RIE.

(e) Using the gate sidewall insulating film 8 and the polycrystalline Si gate electrode 5 as a mask, B+ ions are implanted to form a p+ shield diffusion layer 6 with a surface concentration of about 10''/am3 x j-3 pm.

(f) Thin 5i02 using gate sidewall insulating film 8 as a mask
The membrane is opened by etching, and S
The t-substrate is selectively isotropically etched to perform side etching to below the gate electrode 5 to form an etching hole.

(g) Tungsten, which will become Schottky metal 3, is selectively grown to fill the above-mentioned etching holes. At this time, if conditions for causing lateral erosion of tungsten are appropriately selected, etching of the St substrate in the step (f) is not necessary.

Finally, a PSG film is deposited as the interlayer insulating film 11, a contact hole is opened, a length A for wiring is deposited, this is patterned to form each electrode, and metal is deposited on the back surface of the n+ substrate 14. If a drain electrode is formed by vapor deposition, a Schottky tunnel transistor having a vertical structure as shown in FIG. 5 can be obtained.

FIG. 10 shows a third embodiment of the invention.

In this embodiment, in a Schottky tunnel transistor having a vertical structure, the gate electrode 5 is formed in the shape of a groove, and the lower part thereof is buried in the low concentration region 1. The gate insulating film 4 is formed on the side surfaces of the groove-shaped gate electrode 5.

In the first and second embodiments, the Schottky metal is formed so as to wrap around under the gate electrode, so that stress is easily applied to the gate insulating film and the Schottky junction. In contrast, in this embodiment, the stress escapes in the vertical direction, so its influence can be reduced.

FIGS. 11(a) and 11(b) show a fourth embodiment of the present invention.

First, in the example of Figure 11), the Schottky metal 3 is formed so as to wrap around under the gate electrode 5, and the A-A
The shield diffusion layer 6 is formed to a position immediately below the Schottky junction shown by the part perpendicular to the line. According to such a configuration, since there is no offset between the gate electrode 5 and the Schottky junction, the thickness of the Schottky barrier is efficiently modulated by the gate voltage, and the leak bus is more reliably cut by the shield diffusion layer 6. Leakage current can be further reduced.

Furthermore, in the example shown in FIG. 11(b), the Schottky junction is formed at a position that almost coincides with the end surface of the gate electrode 5;
The shield diffusion layer 6 is formed so as to cover the corner portions of the Schottky metal 3.

According to such a configuration, the leak bus at the corners of the Schottky metal 3 where electric field concentration tends to occur is removed from the shield diffusion layer 6.
Since the leakage current is cut, the leakage current reduction effect can be further enhanced.

[Effects of the Invention] As explained above, according to the present invention, the formation of the Schottky junction is limited to only the required region controlled by the gate electrode, and the Schottky metal surface other than the region where the Schottky junction is formed is Since it was shielded with a conductive shield layer,
The leakage current in this shield part is regulated by the pn junction formed by the shield layer and the semiconductor substrate and becomes a low level, which has the advantage that the overall leakage current can be significantly reduced and the withstand voltage characteristics can be improved. There is.

[Brief explanation of the drawing]

1 to 4 show a first diagram of a semiconductor device according to the present invention.
Fig. 1 is a block diagram showing the basic structure, Fig. 2 is a band diagram showing the energy band of a Schottky junction, etc., Fig. 3 is a vertical cross-sectional view showing the specific structure, and Fig. 4 is a diagram showing the energy band of the Schottky junction. FIG. 5 is a process diagram showing an example of the manufacturing process, FIGS. 5 to 9 show a second embodiment of the present invention, FIG. 5 is a longitudinal sectional view, and FIG. 6 is a plan view showing a cell pattern. Fig. 7 is a diagram for explaining the action in the off state, Fig. 8 is a diagram for explaining the action in the on state, Fig. 9 is a process diagram showing an example of the manufacturing process, and Fig. 10 is a diagram for explaining the action in the on state. 11 is a longitudinal sectional view showing a main part of a fourth embodiment of the invention, and FIG. 12 is a diagram for explaining a conventional Schottky tunnel transistor. . 2: N+ drain region, 3: Schottky metal, 4: Gate insulating film, 5: Gate electrode, 6: P shield diffusion layer (shield layer), 9.18: Source electrode, 10.15 Nidrain electrode . Agent Patent Attorney Hidekazu Miyoshi Figure 3 Figure 1 Figure 2 (b) Figure 6 (a) Figure 6 (b) ] Figure 4 (a) Atsushi 4 1'! '? (b) Figure 4 (C) Figure 4 (d) S4 Figure (e) 9th r1! J(d) Figure 11 (a) Figure 11 (b) Figure 12 (a) Figure 12 (C) Figure 12 (d) Figure 12 (e)

Claims (1)

[Scope of Claims] A semiconductor substrate of a first conductivity type in which a drain region is formed, and a Schottky metal formed on a main surface of the semiconductor substrate and forming a Schottky junction with the semiconductor substrate in a portion and functioning as a source region. a gate electrode that is provided to the Schottky junction via an insulating film and controls the tunnel current of the Schottky junction; and a gate electrode that is connected to the Schottky metal and the semiconductor substrate in a region other than the formation region of the Schottky junction that is controlled by the gate electrode. A semiconductor device comprising: a shield layer of a second conductivity type formed at a boundary portion.