CN212113729U

CN212113729U - Semiconductor device having trench structure

Info

Publication number: CN212113729U
Application number: CN202020513822.0U
Authority: CN
Inventors: 郑亚良; 李浩南; 陈伟钿; 周永昌; 张永杰; 孙倩; 黎沛涛
Original assignee: Alpha Power Solutions Ltd
Current assignee: Alpha Power Solutions Ltd; Versitech Ltd
Priority date: 2020-04-09
Filing date: 2020-04-09
Publication date: 2020-12-08
Anticipated expiration: 2030-04-09

Abstract

The utility model discloses a semiconductor device with slot structure. The semiconductor device includes: a substrate; a drift layer; a well region; a first contact region and a second contact region disposed on the well region; the side wall of the groove is in contact with the first contact region and the well region; a first buried region and a second buried region disposed below the bottom wall of the trench and in contact with the bottom wall; a gate region disposed in the trench; a first source metal region disposed in the trench and under the gate region; a gate oxide region; a second source metal region disposed over the first contact region and the second contact region and electrically connected to the first source metal region; and a drain metal region. According to the utility model discloses a semiconductor device has higher device density, better current capability and less switching loss.

Description

Semiconductor device having trench structure

Technical Field

The utility model relates to a semiconductor field, more specifically relates to semiconductor device with slot structure.

Background

In the field of semiconductor device manufacturing, reducing the device area and improving the integration density are important means for reducing the chip cost. On the other hand, in order to improve the performance of the device, the structure of the device itself is often required to be designed in a complex manner, and the design usually increases the area of the device itself. In addition, performance parameters such as on-resistance, on-voltage, leakage current, capacitance, internal electric field distribution, etc. are common considerations in device design. The current device performance and integration density are less than ideal, and this problem is more prominent in important applications such as the design and application of third generation semiconductor devices.

SUMMERY OF THE UTILITY MODEL

The utility model provides a semiconductor device with slot structure to solve one or more technical problem among the prior art.

According to an aspect of the present invention, a semiconductor device having a trench structure is provided. The semiconductor device includes: a substrate having a first conductivity type, the substrate having a first side and a second side; a drift layer disposed on the first side of the substrate, the drift layer having a first conductivity type; a well region disposed on the drift layer, the well region having a second conductivity type, the second conductivity type being opposite to the first conductivity type; a first contact region and a second contact region disposed on the well region, the first contact region having a first conductivity type and the second contact region having a second conductivity type; the groove extends to the inside of the drift layer from the surface of the first contact region to the direction of the substrate, and the side wall of the groove is in contact with the first contact region and the well region; first and second buried regions having a second conductivity type, the first and second buried regions being disposed below and in contact with the bottom wall of the trench; a gate region disposed in the trench; a first source metal region disposed in the trench and below the gate region, the first source metal region contacting a portion of the drift layer and forming a schottky contact at a contact interface; a gate oxide region, at least a portion of which is disposed in the trench and surrounding the gate region such that the gate region is spaced apart from the well region, the first contact region, and the first source metal region; a second source metal region disposed over and in contact with the first and second contact regions, the second source metal region being electrically connected to the first source metal region; and a drain metal region in contact with the second surface of the substrate.

Alternatively or additionally, one side of the first buried region is aligned with one sidewall of the trench and one side of the second buried region is aligned with one sidewall of the trench in a direction from the well region toward the substrate.

Alternatively or additionally, a distance between one side edge of the first buried region and one side edge of the second buried region in at least one direction parallel to the first face of the substrate is greater than a width of the bottom wall of the trench.

Alternatively or additionally, the first buried region and the second buried region are both continuous buried regions.

Alternatively or additionally, either of the first and second buried regions comprises a plurality of discontinuous buried sub-regions.

Alternatively or additionally, the semiconductor device comprises one or more of silicon carbide, silicon, and gallium nitride.

Alternatively or additionally, the first conductivity type is N-type and the second conductivity type is P-type.

Alternatively or additionally, the drift layer comprises a first drift layer and a second drift layer disposed on the first drift layer, the first buried region and the second buried region being disposed in the first drift layer.

Alternatively or additionally, at least a portion of the first buried region and at least a portion of the second buried region are in contact with the second drift layer.

Alternatively or additionally, the trench passes through the second drift layer and is in contact with the first drift layer.

Semiconductor devices having trench structures in accordance with one or more embodiments of the present invention have a number of technical advantages. For example, the semiconductor device can integrate the field effect device and the Schottky type contact by only one groove, has higher integration density, and can reduce the chip area and the manufacturing cost. For another example, the device structure according to one or more embodiments of the present invention has better current capability, and at the same time, can reduce gate leakage capacitance and reduce switching loss. With regard to further advantages of the present invention, the following detailed description will be read in connection with one or more specific embodiments.

Drawings

Fig. 1 is a schematic perspective view of a semiconductor device according to an embodiment of the present invention;

FIG. 2A shows a schematic cross-sectional view along line AA of FIG. 1;

FIG. 2B shows a schematic cross-sectional view along line BB of FIG. 1;

fig. 3 shows a modified example of the sectional structure shown in fig. 2A;

fig. 4A is a schematic plan projection structure diagram of a first source metal region, a first buried region, and a second buried region according to an embodiment of the present invention;

FIG. 4B shows a modified example of the structure shown in FIG. 4A;

fig. 5A-5M illustrate a method of manufacturing a semiconductor device according to an embodiment of the present invention.

Detailed Description

To facilitate an understanding of the present invention, a number of exemplary embodiments will be described below in conjunction with the associated drawings.

Fig. 1 is a schematic perspective view of a semiconductor device according to an embodiment of the present invention. Fig. 2A shows a schematic cross-sectional view along line AA of fig. 1, and fig. 2B shows a schematic cross-sectional view along line BB of fig. 1. For the sake of brevity, these figures do not show all elements of the semiconductor device. For example, some elements that are not essential to the inventive concept of the present invention, such as some passivation layers, etc., are omitted.

As illustrated, the semiconductor device 100 includes a substrate 110, the substrate 110 having a first conductivity type (e.g., N-type), and having a first side 112 and a second side 114 opposite the first side 112. A drift layer 120 is disposed on the first face 112, the drift layer 120 having a first conductivity type. A well region 130 of the second conductivity type is disposed on the drift layer 120. The second conductivity type is opposite to the first conductivity type, for example, P-type. A first contact region 140 and a second contact region 150 are disposed on the well region 130. The first contact region 140 has a first conductivity type and the second contact region 150 has a second conductivity type.

The semiconductor device 100 is also provided with a trench 160. The trench 160 extends from the surface of the first contact region 140 toward the substrate 110 (y direction in the present embodiment) to the inside of the drift layer 120. The channel 160 has sidewalls 162 and a bottom wall 164. Sidewalls 162 of the trench 160 contact the first contact region 140 and the well region 130. A first buried region 170a and a second buried region 170b of the second conductivity type are provided in the drift layer 120. The buried

regions

170a, 170b are disposed below the bottom wall 164 of the trench 160 and are in contact with the bottom wall 164.

A gate region 180 is disposed in the trench 160. The gate region 180 comprises, for example, polysilicon or other suitable material. A first source metal region 190 is also disposed in trench 160. The first source metal region 190 may be a suitable metal material including, but not limited to, nickel, titanium, aluminum. The first source metal region 190 is located under the gate region 180 and contacts a portion of the drift layer 120 and forms a schottky contact or schottky junction at the contact interface 121. The portion within a certain depth below the contact interface 121 may also be referred to as a schottky region.

Semiconductor device 100 includes a gate oxide region 182. Gate oxide region 182 comprises, for example, silicon dioxide. At least a portion of gate oxide region 182 is disposed in trench 160 and surrounds gate region 180 such that gate region 180 is spaced apart from well region 130, first contact region 140, and first source metal region 190.

The semiconductor device 100 further includes a second source metal region 192. The second source metal region 192 may be a suitable metal material including, but not limited to, nickel, titanium, aluminum. The metal material of the second source metal region 192 may be the same as or different from the first source metal region 190. The second source metal region 192 is disposed over the first and

second contact regions

140 and 150 and contacts the first and

second contact regions

140 and 150. The second source metal region 192 is electrically connected to the first source metal region 190 (see fig. 2B). On the second side 114 of the substrate 110, a drain metal region 196 is disposed. The drain metal region 196 forms a low resistance contact (e.g., ohmic contact) with the second face 114.

In the structure shown in this embodiment, a field effect device (in this embodiment, a metal-oxide semiconductor field effect transistor MOSFET) can be integrated with a schottky device by including only one trench. The Schottky device is buried in the drift layer and is arranged below the groove, so that the distribution characteristic of an electric field can be improved, and the current capability can be improved. And, because of the lower turn-on voltage of the schottky device, the forward turn-on characteristics of the field effect device can also be improved. The structure according to the embodiment can reduce the gate-drain capacitance, increase the switching speed of the device and reduce the conduction loss.

In addition, as shown in fig. 2A-2B, in at least one direction (x direction in the present embodiment) parallel to the first face 112 of the substrate 110, a distance between one side edge 172A of the first buried region 170a and one side edge 172B of the second buried region 170B is larger than the width of the bottom wall 164 of the trench 160. That is, a portion of the buried

regions

170a, 170b has a lateral extension relative to the bottom wall 164. This is true when the impurity concentration of the drift layer 120 is high (e.g., higher than 1E17 cm)^-3) It is advantageous to reduce the electric field strength of the oxide layer. It will be appreciated by those skilled in the art that such an extended design is not required, for example figure 3 shows a variation.

In fig. 3, the semiconductor device includes a substrate 310, a drift layer 320, a well region 330, first and

second contact regions

340 and 350, a trench 360, first and second buried

regions

370a and 370b, a gate region 380, a first source metal region 390, a second source metal region 392, a gate oxide region 382, and a drain metal region 396. The trench 360 has sidewalls 362 and a bottom wall 364. Unlike the illustration of fig. 2A, in fig. 3, in a direction (y direction in the present embodiment) from the well region 330 toward the substrate 310, one side 372A of the first buried region 370a is aligned with one sidewall 362 of the trench 360, and one side 372b of the second buried region 370b is aligned with one sidewall 362 of the trench. That is, the buried

regions

370a, 370b are located entirely below the bottom wall 364 of the trench 360. This may protect the oxide layer sufficiently when the impurity concentration of the drift layer 320 is low, so that the electric field of the oxide layer is kept below a certain strength, thereby preventing the device performance from deteriorating or failing due to the oxide layer breakdown.

Fig. 4A is a schematic plan projection structure diagram of the first source metal region, the first buried region, and the second buried region according to an embodiment of the present invention. Fig. 4A may be an example of a schematic plan projection structure of the first source metal region 190, the first buried region 170a, and the second buried region 170B in fig. 1 and 2A-2B, for example.

As shown in fig. 4A, in planar projection, first source metal region 490 is in contact with first buried region 470a and second buried region 470 b. The buried

regions

470a, 470b are each in the shape of a strip, and are each a continuous buried region.

Fig. 4B shows a variation of the structure of fig. 4A. In fig. 4B, either one of the first buried region and the second buried region includes a plurality of discontinuous buried sub-regions. The first buried region is illustrated as including five buried sub-regions 470a1, 470a2, 470a3, 470a4, 470a 5. The second buried region is illustrated as including five buried sub-regions 470b1, 470b2, 470b3, 470b4, 470b 5. Each buried sub-region is in contact with a first source metal region 490 a.

Fig. 5A-5M illustrate a method of manufacturing a semiconductor device according to an embodiment of the present invention. The illustrated method may be used, for example, to fabricate the semiconductor devices illustrated in fig. 1, 2A-2B. It will be appreciated by persons skilled in the art that the illustrated method is merely exemplary and that one or more other variations are possible.

In the following method illustrated in conjunction with fig. 5A-5M, an N-type silicon carbide substrate is taken as an example for description. In fig. 5A, an N-type silicon carbide substrate 510 is provided, and a first drift layer 522 is formed on the substrate 510. The first drift layer 522 may be formed by epitaxial growth. First and second buried

regions

570a and 570b of P-type are formed on the first drift layer 522 by ion implantation. That is, the first buried region 570a and the second buried region 570b are disposed in the first drift layer 522. In fig. 5B, a second drift layer 524 of an N type is formed by epitaxial growth. Thereby, at least a portion of the first buried region 570a and at least a portion of the second buried region 570b are in contact with the second drift layer 524. The first drift layer 522 and the second drift layer 524 may be referred to as a drift layer as a whole.

In fig. 5C, a P-type well region 530 is formed on the second drift layer 524. The well region 530 may be formed by epitaxial growth on the second drift layer 524, or may be formed by performing P-type ion implantation on a portion of the second drift layer 524. In fig. 5D, a first contact region 540 of an N-type and a second contact region 550 of a P-type are formed on the P-type well region 530, which may be formed by ion implantation under an appropriate mask. In fig. 5E, a trench 560 is formed by etching. The trench 560 passes through the second drift layer 524 and contacts the first drift layer 522.

In fig. 5F, a silicon dioxide layer is deposited on the surface formed in fig. 5E and etched to form a patterned silicon dioxide layer 582a to expose a portion of the surface of the first drift layer 522. In fig. 5G, a metal (which may be, for example, nickel, titanium, aluminum, or other suitable material) is deposited using the patterned silicon dioxide layer 582a of fig. 5F as a mask to form a first source metal region 590. In fig. 5H, the silicon dioxide layer 582a is removed and the silicon dioxide layer deposition and patterning (e.g., by etching) is again performed to provide a silicon dioxide layer 582 b. In fig. 5I, silicon dioxide 582c is deposited on the sidewalls of the trench and the

contact regions

540, 550. In some embodiments, silica 582c may also be generated by direct oxidation. In fig. 5J, polysilicon 580a is deposited. In fig. 5K, polysilicon 580a is patterned (e.g., by etching) to form gate regions 580 and silicon dioxide 582d is again deposited. In fig. 5L, the silicon dioxide 582d is patterned (e.g., etched) to obtain a gate oxide region 582. Metal is deposited to obtain second source metal regions 592, which may be obtained, for example, by depositing nickel, titanium, aluminum, or other suitable material. In fig. 5M, metal is deposited on the other side of the substrate 510 to obtain a drain metal region 596.

The above examples are only for the purpose of illustrating the inventive concept of the present invention and are in no way to be construed as limiting the invention. For example, in the above embodiments, although silicon carbide is exemplified, it will be understood by those skilled in the art that other materials are possible, for example, in some embodiments, the semiconductor device may include one or more of silicon carbide, silicon, gallium nitride, or other suitable materials. For another example, although the first conductivity type is illustrated as N-type and the second conductivity type is illustrated as P-type, in some embodiments, the first conductivity type may also be P-type and the second conductivity type may also be N-type.

Although the embodiments of the present invention use terms such as first, second, etc. to denote the respective elements, it is to be understood that these elements should not be limited by the above terms. The above terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present invention.

It will be further appreciated by those of ordinary skill in the art that for purposes of clarity of illustration, elements (e.g., regions, layers, etc.) in the figures have not necessarily been drawn to scale. For example, the thickness of the drift layer may be from a few microns to tens of microns, while the thickness of the substrate may be up to about 200 microns, which if drawn to scale would reduce the legibility of the drawing.

In addition, each element in the drawings is not necessarily the actual shape thereof. For example, the cross-sectional areas of the various regions in the figure are shown as squares, as those skilled in the art will appreciate that these are for illustrative purposes only, e.g., actual doping profiles will typically have certain transition regions or slopes or gradients, rather than profiles where the gradient is infinite at some point or boundary.

Furthermore, it will be understood by those skilled in the art that the above embodiments are intended to illustrate the invention in different respects, not in isolation; rather, those skilled in the art can combine the different embodiments appropriately according to the above examples to obtain other technical solutions.

Unless defined otherwise, technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. Embodiments of the present invention are illustrated in non-limiting examples. Variations that may occur to those skilled in the art upon consideration of the above-disclosed embodiments are intended to fall within the scope of the present invention.

Claims

1. A semiconductor device having a trench structure, comprising:

a substrate having a first conductivity type, the substrate having a first face and a second face;

a drift layer disposed on a first side of the substrate, the drift layer having a first conductivity type;

a well region disposed on the drift layer, the well region having a second conductivity type, the second conductivity type being opposite the first conductivity type;

a first contact region and a second contact region disposed on the well region, the first contact region having a first conductivity type and the second contact region having a second conductivity type;

a trench extending from a surface of the first contact region toward the substrate to an inside of the drift layer, a sidewall of the trench contacting the first contact region and the well region;

a first buried region and a second buried region having a second conductivity type, the first buried region and the second buried region being disposed below a bottom wall of the trench and in contact with the bottom wall;

a gate region disposed in the trench;

a first source metal region disposed in the trench and below the gate region, the first source metal region being in contact with a portion of the drift layer and forming a Schottky contact at a contact interface;

a gate oxide region, at least a portion of said gate oxide region being disposed in said trench and surrounding said gate region such that said gate region is spaced apart from said well region, first contact region, first source metal region;

a second source metal region disposed over and in contact with the first and second contact regions, the second source metal region being electrically connected with the first source metal region; and

a drain metal region in contact with the second side of the substrate.

2. The semiconductor device of claim 1, wherein a side of the first buried region is aligned with a side wall of the trench and a side of the second buried region is aligned with a side wall of the trench in a direction from the well region toward the substrate.

3. The semiconductor device according to claim 1, wherein a distance between one side edge of the first buried region and one side edge of the second buried region in at least one direction parallel to the first face of the substrate is larger than a width of a bottom wall of the trench.

4. The semiconductor device according to any one of claims 1 to 3, wherein the first buried region and the second buried region are each a continuous buried region.

5. The semiconductor device of any of claims 1 to 3, wherein any of the first and second buried regions comprises a plurality of discontinuous buried sub-regions.

6. A semiconductor device according to any one of claims 1 to 3, wherein the semiconductor device comprises one or more of silicon carbide, silicon, and gallium nitride.

7. A semiconductor device according to any one of claims 1 to 3, wherein the first conductivity type is N-type and the second conductivity type is P-type.

8. The semiconductor device according to any one of claims 1 to 3, wherein the drift layer includes a first drift layer and a second drift layer provided on the first drift layer, the first buried region and the second buried region being provided in the first drift layer.

9. The semiconductor device of claim 8, wherein at least a portion of the first buried region and at least a portion of the second buried region are in contact with the second drift layer.

10. The semiconductor device of claim 8, wherein the trench passes through the second drift layer and is in contact with the first drift layer.