JPS62274775A - Semiconductor device - Google Patents

Abstract

PURPOSE:To construct a high-performance basic device structure by a method wherein a Schottky junction is formed between metal and low-concentration semiconductor and electrodes are built on them through the intermediary of an insulating film. CONSTITUTION:An N<+>-layer 2 is kept at a drain voltage VD, a gate electrode 3 at a gate voltage VG, and a metal layer 5 at the ground potential. When a positive voltage (VD>O) is applied only to the drain N<+>-layer 2, no current flows although a Schottky barrier depletion layer in an N<->-layer 1 extends toward a silicon side. Next, when the gate voltage VG is also rendered positive, the Schottky barrier will be so thin that electrons will tunnel from a metal layer 6 into the N<->-layer 1 for the performance of switching actions. In this case, the N<+>-layer 2 contacts with external circuits. It becomes possible for a current flowing from the drain N<+>-layer 2 to a source metal layer 5.

Description

Detailed Description of the Invention 3. Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to a basic device suitable for future LSIs.

[Conventional technology]

MOS transistors, which have traditionally dominated as constituent elements of LSIs, are facing various problems as their miniaturization progresses. Examples include 1) a decrease in the current from the ideal value due to an increase in various parasitic effects, 2) a decrease in the reliability of the breakdown voltage reduction ring due to an increase in the internal electric field of the element, and 3) a decrease in the threshold voltage as the gate length becomes shorter. Examples include an increase in the short channel effect, which reduces the For this reason, future VLS
I.

Building ULSI depends on how to solve the above problems. At present, as a method to solve the above 2)j and 3) at the same time, the lightly doped drain structure (LightlyDoped
Drain structure (commonly known as LDD structure) is considered to be effective.

[Problem that the invention seeks to solve]

The LDDW structure in the above-mentioned prior art is certainly effective at the 1 micron level, but it comes at the cost of somewhat lowering the current in order to improve the withstand voltage. For this reason, in the submicron region, a single structure will not be sufficient as a basic device for USSI in the future.Also, lowering the power supply voltage is a way to avoid having to pay attention to reliability such as withstand voltage, but this also applies to current This results in a large decrease in Furthermore, regarding performance improvement through scaling of MOS transistors.

It has also been reported that there are limits due to various parasitic effects, such as speed saturation, and there are many problems to be solved for the basic structure of future IJLSIs.

The purpose of the present invention is to be effective even in future submicron devices,
Another object of the present invention is to provide a basic device structure with higher performance than conventional MOS transistors.

[Means for solving problems]

The above object is achieved by bringing a metal and a low concentration semiconductor into contact to form a Schottky junction, and by providing an electrode thereon with an insulating film interposed therebetween.

[Function] The device of the present invention basically controls a tunnel current flowing through a Schottky junction formed of a metal and a semiconductor by applying a voltage to a gate electrode via an insulating film. This basic operation will be explained using FIG. 3.4.5.

First, the one shown in Figure 3 is a low concentration (No<1016
(1-11) This is an energy band diagram when n-type silicon and metal are brought into contact, and a Schottky barrier is formed as shown in FIG. 3(a). Now, consider a case where the n-type silicon is set to 0 potential and a voltage V is applied to the metal. (b)
When V is negative, as shown in (c), a depletion layer simply expands in the silicon layer and no current flows.However, when V becomes positive, as shown in (c), electrons are injected from the silicon into the metal, causing a current to flow. In other words, it exhibits rectification properties.

Also, what is shown in Figure 4 is high concentration (No>10”cm).
-3) Energy band diagram (a) when n-type silicon and metal are brought into contact. When V is positive as shown in (c), the current flows as before, but when ■ is negative, as shown in (b), the depletion layer does not extend much due to the high impurity concentration, and the width of the barrier increases. Because it is extremely thin, tunnel current flows from the metal to the silicon layer. This allows the fourth
In the case shown in the figure, it exhibits ohmic properties without exhibiting rectifying properties as in Fig. 3. As described above, it is understood that in a Schottky junction, the current can be controlled by changing the impurity concentration of silicon.

Therefore, if a gate electrode 3 is provided on the Schottky junction via an insulating film as shown in FIG. 5, and the carrier concentration on the silicon surface is changed using this gate electrode, a switching element that can control the current for the above-mentioned reasons can be obtained. In other words, a low concentration of n
Bring the mold substrate into contact with the metal, and apply a negative voltage to the metal side. When the gate voltage VQ is ov, no current flows due to the Schottky barrier as shown in Figure 3(b), but as Va is applied positively, the surface of the n-type silicon becomes an accumulation layer and becomes a high concentration region. . As a result, the surface barrier becomes as shown in FIG. 4(b), and electrons tunnel through the metal, allowing current to flow. The element of the present invention performs the switching operation as described above.

Furthermore, if a negative voltage is applied to the gate electrode of the above device to form an inversion layer on the surface of the n-type substrate and the concentration of carriers in this inversion layer is sufficiently high, a tunnel current will flow based on the above principle, resulting in switching operation. do. In other words, this device is
If the gate voltage is made sufficiently large, either positive or negative, and the carrier concentration on the substrate surface is increased, current will flow due to tunnel current. Note that the above characteristics also apply when this structure is formed of metal and low concentration p-type silicon.
A switching operation is performed by applying a bias opposite to the above.

When using the device of the present invention, punch-through does not occur even when miniaturized because there is a physical Schottky barrier.
Therefore, there is no need to increase the substrate impurity concentration as a countermeasure against punch-slip, and as a result, it is possible to improve breakdown voltage and achieve high mobility 1, etc.

In addition, this switching element is enhanced by changing the impurity concentration of the silicon substrate itself (for example, impurity implantation technique #r for threshold voltage control used in conventional MOS transistors).

Can be created in either mode of depression.

Therefore, compared to conventional MOS transistors, it is highly effective as a new device for the future submicron region.

〔Example〕

Embodiment 1 An embodiment of the present invention will be described below with reference to FIG. 6, and its manufacturing method, and FIG. 7, its operation.

First, after selectively forming an element isolation region on an n-type 10Ω-1 substrate 1, an n0 layer 2 is formed by implanting arsenic (As) into a region that will become a drain in the future using a photoresist as a mask (XJ=0 .5 μm), and then photo-etched the silicon in the area that will become the source in the future to 0.5 μm.
Scrape (Figure 6(a)).

Next, tungsten (W) is placed as a metal in the silicon groove.
) 5, and a gate oxide film (20 nm) 6 and a phosphorus-doped poly-8i gate electrode 3 (400 nm) are formed by photoetching [FIG. 6(b)]. After coating a phosphosilicate glass (PSG) film 9 as an interlayer insulating film, a contact hole is opened and the aluminum 11 electrode 1
Complete by forming 0 [Fig. 6(C)].

Now, the operation of this embodiment will be explained using FIG. 7. As shown in (a), the drain voltage Vo is applied to the layer 2, the gate voltage Va is applied to the gate electrode 3, and the metal layer 5 is applied to the ground potential. Va=Vo=O on the silicon surface
The energy band diagram of V in its initial state is shown in (b).

First, when a positive voltage (Vo>O) is applied only to the n layer 2 of the drain, the depletion layer of the Schottky barrier in the n layer 1 extends toward the silicon side, as shown in (c), and no current flows. Next, when the gate voltage Va is also made positive, the Schottky barrier becomes thinner as shown in (d), and electrons tunnel from the metal 6 into the n layer. The present invention performs the switching operation as described above. In this case, the n+ layer 2 is formed to make contact with the outside.

In the present invention, from the drain n÷ layer to the source metal layer 5
It is possible to control the current flowing only to the For this reason,
When Vo<O, the Schottky junction is forward biased, and current flows in the opposite direction from the metal layer to the n-layer, making it impossible to perform switching operations in the phase direction.

Example 2 In Example 1, the high 111i1 degree diffusion layer and the substrate were of the same conductivity type, but next, a case where the conductivity types of both are different will be described with reference to FIG.

The structure is shown in FIG.
B) may be implanted at a high concentration to form a P layer 21.

Next, the operation of this embodiment will be explained. As shown in (a), a drain voltage VD is applied to the P layer 21, a gate voltage Vo is applied to the gate electrode 3, and the source metal layer 5 and the substrate 1 are applied.
is set to ground potential. First, an energy band diagram of the silicon surface at VG=VD=OV is shown in (b).

In this case, a p+n junction is formed between the drain and the substrate, and a Schottky junction is formed between the substrate and the drain. Here, if only the gate voltage Va is made negative, (c
), the substrate surface is reversed, but no current flows. Also,
Even if only the drain voltage Vo is made negative as shown in (d), no current flows due to the barrier, as shown in (e), Vo, V
Only when both o are made negative, the width of the Schottky barrier on the source side becomes narrower, a tunnel current flows through this, and this becomes the current of this transistor.

In this structure, unlike the first embodiment, the transistor operates in the same manner as described above even if the drain and source are reversely connected, so that it can be used as a phase direction switching element.

Moreover, the high breakdown voltage of this structure can be achieved by forming the known double drain structure and the above-mentioned LDD structure on the drain side.

Further, even if the drain is also made of metal, phase direction operation is possible.

Embodiment 3 The switching element of the present invention uses a gate to control the impurity concentration on the silicon side near the Schottky junction interface, so if this gate electrode also has a Schottky junction only near the junction, as shown in FIG. The operation is the same as in the example ↓.

Further, as shown in FIG. 12, it is also possible to form the transistor of the present invention vertically. In this case, a metal layer 5 is formed on the upper part of the substrate, and a high concentration diffusion layer is formed on the lower part.

Therefore, it is easy to form a Schottky junction that is close to ideal in terms of process.

Example 4 In Example 2, if the length of the gate electrode 4 becomes too short or the drain voltage becomes too large, the depletion layer of the Schottky barrier extends from the drain to the source side, increasing the threshold voltage of Mo8. I will let you do it.

For this reason, as shown in FIG. 13, a focused ion beam or the like is applied to a region 4 with higher concentration of impurity (same conductivity type as the substrate) than the substrate near the center of the channel of this device, that is, in a place not too close to the Schottky junction. It was formed to reach deep into the substrate.

As a result, the depletion layer formed by the voltage applied to the drain stops at the high concentration layer 4 and does not extend any further toward the source side.

Embodiment 5 The embodiments 1 to 4 are all application examples of the switching element 1 of the present invention, but an embodiment in which a plurality of switching elements 1 are integrated will be described.

Figure 14 shows a switching element in Example 2 in which electrons flow through the inversion layer when the gate is positively biased (this is referred to as an n-channel), and a device (p-channel) in which holes flow through the inversion layer when the gate is negatively biased. They are combined to form an inverter. In this case, the conventional complementary MO8 (CMO3
) The diagram shows that the process can be applied as is.
As shown in (a), an n-channel device was directly formed on a p-type substrate 1, and the n-channel device was formed in an n-type well 2o. Also, the potentials of the substrate and well are p+
21. I am in contact with n+ 22. The operation of this inverter can be exactly the same as that of the conventional CMO5. Note that the well may be formed of an n-type substrate and a p-type well. In this embodiment, problems such as latch-up peculiar to conventional OMO3 do not occur, and it is suitable for miniaturization.

Further, in Example 1 as well, conversion to CMO5 is possible.

〔Effect of the invention〕

According to the invention, a conventional MoS transistor.

It can overcome many problems that occur in miniaturization (e.g., evaporation, reduction in breakdown voltage, reduction in current due to various parasitic effects, etc.), and is very effective as a basic device for future LSIs and the like.

[Brief explanation of drawings]

1 and 2 are cross-sectional views of the structure showing the present invention, and FIG.
5 to 5 are diagrams showing the operating principle of the present invention, FIGS. 6 and 7 are diagrams showing the first embodiment of the present invention, and FIG. 8 is a diagram showing the second embodiment of the present invention. 9 to 11 are diagrams showing other embodiments of the present invention, and FIG. 12 is a diagram showing an example in which elements of the present invention are integrated. DESCRIPTION OF SYMBOLS 1...Low concentration semiconductor substrate, 3...Gate electrode, 5...
...Metal, 6...Gate insulating film, 9...P S G
Film, 10... Aluminum film, 1l-Si3Na film,
19-8iOz film, 20...n-type well layer, 21.2
2... High concentration diffusion layer, 30... P-type well layer, 10
1~106...A￥-J 3 Figure C (L) V=OCb) V<0 (C)
L/n θ Fig. 4 (, L) V2o (b) V<θ
('-) V/>l) Not 5 Figure 7 Figure stone qth lρ Figure % n country''-fi Figure 12 (b) (/l) 3 no

Claims (1)

[Claims] 1. In a structure in which a metal, a first conductivity type low concentration semiconductor, and a first conductivity type high concentration semiconductor are sequentially connected, the carrier concentration of the low concentration semiconductor is changed by a conductor via an insulating film. A semiconductor device characterized by controlling a tunnel current flowing through a Schottky barrier junction formed at an interface between a metal and a semiconductor. 2. In the semiconductor device according to claim 1,
A semiconductor device characterized in that the high concentration semiconductor is of a second conductivity type.