CN112614884A - Semiconductor vertical IGBT based on longitudinal Schottky tunneling emitter junction and preparation method - Google Patents
Semiconductor vertical IGBT based on longitudinal Schottky tunneling emitter junction and preparation method Download PDFInfo
- Publication number
- CN112614884A CN112614884A CN202011490832.8A CN202011490832A CN112614884A CN 112614884 A CN112614884 A CN 112614884A CN 202011490832 A CN202011490832 A CN 202011490832A CN 112614884 A CN112614884 A CN 112614884A
- Authority
- CN
- China
- Prior art keywords
- layer
- emitter
- grid
- dielectric layer
- drift layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 39
- 230000005641 tunneling Effects 0.000 title claims abstract description 38
- 238000002360 preparation method Methods 0.000 title claims abstract description 14
- 229910052751 metal Inorganic materials 0.000 claims abstract description 66
- 239000002184 metal Substances 0.000 claims abstract description 66
- 238000004519 manufacturing process Methods 0.000 claims abstract description 49
- 230000008719 thickening Effects 0.000 claims abstract description 49
- 239000000758 substrate Substances 0.000 claims abstract description 46
- 238000000034 method Methods 0.000 claims abstract description 44
- 238000002161 passivation Methods 0.000 claims abstract description 21
- 239000000463 material Substances 0.000 claims description 64
- 229910052737 gold Inorganic materials 0.000 claims description 36
- 238000005530 etching Methods 0.000 claims description 33
- 229910052759 nickel Inorganic materials 0.000 claims description 14
- 238000000151 deposition Methods 0.000 claims description 11
- 229910003460 diamond Inorganic materials 0.000 claims description 8
- 239000010432 diamond Substances 0.000 claims description 8
- 229910052763 palladium Inorganic materials 0.000 claims description 8
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 claims description 6
- 229910052681 coesite Inorganic materials 0.000 claims description 6
- 229910052593 corundum Inorganic materials 0.000 claims description 6
- 229910052906 cristobalite Inorganic materials 0.000 claims description 6
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(IV) oxide Inorganic materials O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 claims description 6
- 229910052697 platinum Inorganic materials 0.000 claims description 6
- 239000000377 silicon dioxide Substances 0.000 claims description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 6
- 229910052682 stishovite Inorganic materials 0.000 claims description 6
- 229910052905 tridymite Inorganic materials 0.000 claims description 6
- 229910001845 yogo sapphire Inorganic materials 0.000 claims description 6
- 238000007781 pre-processing Methods 0.000 claims description 3
- 230000008569 process Effects 0.000 abstract description 38
- 230000015556 catabolic process Effects 0.000 abstract description 2
- 239000010931 gold Substances 0.000 description 52
- PXHVJJICTQNCMI-UHFFFAOYSA-N nickel Substances [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 31
- 238000006243 chemical reaction Methods 0.000 description 25
- 238000001755 magnetron sputter deposition Methods 0.000 description 10
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 8
- 239000010936 titanium Substances 0.000 description 8
- 230000004888 barrier function Effects 0.000 description 7
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 6
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 4
- 229910021529 ammonia Inorganic materials 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 238000001035 drying Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 239000001257 hydrogen Substances 0.000 description 4
- 229910052739 hydrogen Inorganic materials 0.000 description 4
- 238000001883 metal evaporation Methods 0.000 description 4
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 4
- 239000013077 target material Substances 0.000 description 4
- 229910052721 tungsten Inorganic materials 0.000 description 4
- 239000002253 acid Substances 0.000 description 3
- 230000008901 benefit Effects 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 238000004140 cleaning Methods 0.000 description 3
- 239000003344 environmental pollutant Substances 0.000 description 3
- 239000007789 gas Substances 0.000 description 3
- 238000010438 heat treatment Methods 0.000 description 3
- 238000001259 photo etching Methods 0.000 description 3
- 231100000719 pollutant Toxicity 0.000 description 3
- CSCPPACGZOOCGX-UHFFFAOYSA-N Acetone Chemical compound CC(C)=O CSCPPACGZOOCGX-UHFFFAOYSA-N 0.000 description 2
- LFQSCWFLJHTTHZ-UHFFFAOYSA-N Ethanol Chemical compound CCO LFQSCWFLJHTTHZ-UHFFFAOYSA-N 0.000 description 2
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 238000000137 annealing Methods 0.000 description 2
- 238000000231 atomic layer deposition Methods 0.000 description 2
- 230000000903 blocking effect Effects 0.000 description 2
- 239000008367 deionised water Substances 0.000 description 2
- 229910021641 deionized water Inorganic materials 0.000 description 2
- 238000005265 energy consumption Methods 0.000 description 2
- 229910052733 gallium Inorganic materials 0.000 description 2
- 229910052750 molybdenum Inorganic materials 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- 230000004044 response Effects 0.000 description 2
- 238000002791 soaking Methods 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- 238000004506 ultrasonic cleaning Methods 0.000 description 2
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 2
- 229910015844 BCl3 Inorganic materials 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000004134 energy conservation Methods 0.000 description 1
- 230000007613 environmental effect Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
The invention discloses a semiconductor vertical IGBT based on a longitudinal Schottky tunneling emitter junction and a preparation method thereof, wherein the preparation method comprises the following steps: the device comprises a P + substrate layer (1), an n + buffer layer (2), an n-drift layer (3), two emitting electrodes (4), a gate dielectric layer (5), a grid electrode (6), two metal thickening layers (7), a passivation layer (8) and a collector electrode (9). The invention simplifies the process manufacturing process of the IGBT power device, enables the IGBT power device to realize the function of the device without a P-type base region, improves the breakdown voltage of the device and reduces the on-resistance of the device, thereby improving the high output power performance of the device.
Description
Technical Field
The invention belongs to the technical field of semiconductor devices, and particularly relates to a vertical semiconductor IGBT based on a longitudinal Schottky tunneling emitter junction and a preparation method thereof.
Background
An Insulated Gate Bipolar Transistor (IGBT) power semiconductor device is applied to electric energy conversion and circuit control in electronic manufacturing industry and industrial control, and with increasing demands for new power electronic devices and energy conservation in electronic information industry, it is one of effective solutions to the demands to develop a new type of semiconductor power device with a good device structure, high conversion efficiency and low energy consumption. The IGBT power Semiconductor device has the advantages of low on-state voltage drop, high input impedance, low driving power, high switching speed, low switching loss, and the like due to the fact that the IGBT power Semiconductor device has the working mechanism of a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) device and a bipolar junction Transistor.
With the continuous development of the field of power devices, the power characteristics of the devices are greatly improved by changing the material of the IGBT power device from a Si material to a GaAs material. However, the performance of power semiconductor devices made of the conventional first-generation Si materials and second-generation GaAs materials has been approaching the theoretical limit determined by the material characteristics so far. Besides high withstand voltage, high saturation electron rate and high output power, the power device represented by the third generation wide bandgap semiconductor GaN and SiC material has higher conversion efficiency and lower energy consumption, and is the power device structure with the best performance prospect.
The existing wide bandgap IGBT power device is limited by a very complicated process manufacturing process, and the power characteristics of the wide bandgap IGBT power device are very low due to an immature process, so that the wide bandgap IGBT power device is not widely researched, developed and applied. One reason for this is that in order to achieve high reliability of the high-power IGBT power device and to protect the high-power IGBT power device from environmental noise, a gate recess etching process is usually used to form the enhancement type IGBT power device, which makes the manufacturing process of the device very complicated. The second reason is that the P-type base region doping activation rate of the traditional wide bandgap IGBT power device is very low, so that the bearable withstand voltage of the wide bandgap IGBT power device is lowered and the on-resistance is increased, the output power quality factor of the corresponding IGBT power device is lowered, and the high power performance of the wide bandgap IGBT device is reduced.
Disclosure of Invention
In order to solve the problems in the prior art, the invention provides a semiconductor vertical IGBT based on a longitudinal Schottky tunneling emitter junction and a preparation method thereof. The technical problem to be solved by the invention is realized by the following technical scheme:
a vertical Schottky tunneling emitter junction-based semiconductor vertical IGBT, comprising:
a P + substrate layer;
an n + buffer layer disposed on the P + substrate layer;
the n-drift layer is arranged on the n + buffer layer, two-stage steps are arranged at two ends of the n-drift layer, a groove is further arranged between the two-stage steps, the two-stage steps comprise a first-stage step and a second-stage step, the first-stage step is positioned below the second-stage step, and the second-stage step is close to the center of the n-drift layer;
the two emitting electrodes are respectively arranged on the second-stage steps at two ends of the n-drift layer;
the gate dielectric layer is arranged on the groove of the n-drift layer and the two emitters;
the grid electrode is arranged on the grid dielectric layer positioned in the n-drift layer groove, and the lower surface of the grid electrode is lower than the lower surface of the emitter electrode;
the grid electrode is arranged on the grid dielectric layer, and a gap is reserved between the grid electrode and the metal thickening layer;
the passivation layer is arranged on the n-drift layer, the gate dielectric layer, the grid electrode and the two metal thickening layers;
and the collector is arranged on the lower surface of the P + substrate layer.
In one embodiment of the present invention, the material of the P + substrate layer, the n + buffer layer, and the n-drift layer is GaN, AlN, SiC, GaO, diamond, or BN.
In one embodiment of the present invention, the material of the gate dielectric layer and the passivation layer is SiN or SiO2Or Al2O3Or HfO2。
In one embodiment of the invention, the material of the emitter is Ti/Au, W/Au, Mo/Au, Ni/Au, Pt/Au or Pd/Au.
In one embodiment of the invention, the gate and the metal thickening layer are of the same material.
In one embodiment of the invention, the upper surface and the lower surface of the emitter have an overlapping region with the gate electrode along the extension of the emitter in the horizontal direction.
The invention also provides a preparation method of the semiconductor vertical IGBT based on the transverse Schottky tunneling emitter junction, which is used for preparing the semiconductor vertical IGBT of any one of the embodiments, and the preparation method comprises the following steps:
selecting a P + substrate layer;
growing an n + buffer layer on the P + substrate layer;
growing an n-drift layer on the n + buffer layer;
etching two first-stage steps at two ends of the n-drift layer;
manufacturing a collector on the lower surface of the P + substrate layer;
manufacturing two emitting electrodes at two ends of the upper surface of the n-drift layer without the first-stage step;
etching the n-drift layer between the two emitting electrodes to form a groove, wherein the emitting electrodes are arranged on the second-stage steps;
growing a gate dielectric layer on the groove of the n-drift layer and the two emitting electrodes;
manufacturing a grid electrode on the grid dielectric layer positioned in the groove of the n-drift layer, and simultaneously respectively preparing metal thickening layers on the emitter electrode and the grid dielectric layer positioned at two ends of the n-drift layer, wherein the lower surface of the grid electrode is lower than the lower surface of the emitter electrode;
and growing a passivation layer on the n-drift layer, the gate dielectric layer, the gate and the two metal thickening layers.
In an embodiment of the present invention, after selecting the P + substrate layer, the method further includes:
and carrying out pretreatment for eliminating dangling bonds on the surface of the P + substrate layer.
In an embodiment of the present invention, fabricating a gate in the groove of the gate dielectric layer, and simultaneously preparing metal thickening layers on the emitter and the gate dielectric layer at two ends of the n-drift layer, respectively, includes:
manufacturing a mask on the gate dielectric layer, and etching a metal thickening area window on the gate dielectric layer above the two emitting electrodes;
and depositing grid metal in the groove of the grid dielectric layer and the window of the metal thickening area to form a grid and two metal thickening layers.
The invention has the beneficial effects that:
the emitter electrodes are arranged at the two ends of the n-drift layer, so that a Schottky tunneling junction controlled by a grid electrode can be formed, and compared with the existing IGBT device with the wide forbidden band material doped with the P-type base region, the Schottky tunneling junction has the following advantages:
firstly, the Schottky tunnel junction formed can control the width of a Schottky barrier through the voltage of a grid electrode, thereby controlling the tunneling probability and generating high electron current density. And secondly, a base region made of a P-type wide bandgap material is not needed, a Schottky tunneling junction is formed by arranging an emitter on the N-drift layer, blocking capability can be provided through a Schottky barrier, and the advantage is limited to an N-channel IGBT device.
And thirdly, the base region of the IGBT device of the invention has no PN junction, so that the device has high response speed and can be used as a high-speed device. And due to the unique topological structure of the device, parasitic triode effect does not exist, and latch-up effect is eliminated.
And fourthly, because the emitter near the grid forms a Schottky tunneling junction, metal electrons can be tunneled into the semiconductor to conduct only by adding forward threshold voltage on the grid, so that the device can be in a normally-closed state when not in operation, the threshold voltage of the device is increased, and the reliability and stability of the IGBT power device and a system level are improved.
Fifthly, the IGBT power device is simple in structure, the manufacturing process of the device is simple, and the yield of the device is improved.
The present invention will be described in further detail with reference to the accompanying drawings and examples.
Drawings
Fig. 1 is a schematic structural diagram of a vertical semiconductor IGBT based on a vertical schottky tunneling emitter junction according to an embodiment of the present invention;
fig. 2 is a schematic diagram of a manufacturing process of a vertical semiconductor IGBT based on a vertical schottky tunneling emitter junction according to an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to specific examples, but the embodiments of the present invention are not limited thereto.
Example one
Referring to fig. 1, fig. 1 is a schematic structural diagram of a vertical semiconductor IGBT based on a vertical schottky tunneling emitter junction according to an embodiment of the present invention. The embodiment provides a vertical semiconductor IGBT based on a longitudinal Schottky tunneling emitter junction, which comprises a P + substrate layer 1, an n + buffer layer 2, an n-drift layer 3, two emitter electrodes 4, a gate dielectric layer 5, a gate electrode 6, two metal thickening layers 7, a passivation layer 8 and a collector electrode 9, wherein the n + buffer layer 2 is arranged on the P + substrate layer 1, the n-drift layer 3 is arranged on the n + buffer layer 2, two steps are arranged at two ends of the n-drift layer 3, a groove is also arranged between the two steps, the two steps comprise a first step 10 and a second step 11, the first step 10 is positioned below the second step 11, the second step 11 is close to the center of the n-drift layer 3, the first step 10 is positioned below the second step 11, and the second step 11 is close to the center of the n-drift layer 3, the two emitting electrodes 4 are respectively arranged on second-stage steps 11 at two ends of the n-drift layer 3, the grid dielectric layer 5 is arranged on a groove of the n-drift layer 3 and the two emitting electrodes 4, the grid electrode 6 is arranged on the grid dielectric layer 5 positioned in the groove of the n-drift layer 3, the lower surface of the grid electrode 6 is lower than the lower surface of the emitting electrode 4, one metal thickening layer 7 is arranged on the emitting electrode 4 and the grid dielectric layer 5 at one end, the other metal thickening layer 7 is arranged on the emitting electrode 4 and the grid dielectric layer 5 at the other end, a gap exists between the grid electrode 6 and the metal thickening layer 7, the passivation layer 8 is arranged on the n-drift layer 3, the grid dielectric layer 5, the grid electrode 6 and the two metal thickening layers 7, and the collector electrode 9 is arranged on.
Furthermore, the P + substrate layer 1 is made of a wide bandgap material such as GaN, AlN, SiC, GaO, diamond or BN.
Furthermore, the n + buffer layer 2 is made of wide bandgap material such as GaN, AlN, SiC, GaO, diamond or BN, the thickness of the n + buffer layer 2 is 0.1-100 μm, and the doping concentration of the n + buffer layer 2 is 1014～1020cm-3。
Furthermore, the material of the n-drift layer 3 adopts wide bandgap materials such as GaN, AlN, SiC, GaO, diamond or BN and the like, the thickness of the n-drift layer 3 is 1-1000 mu m, and the doping concentration of the n-drift layer 3 is 1014～1020cm-3。
Furthermore, an overlapping area with the length of 0.1-10 mu m exists on the vertical edge of the grid 6 and the emitter 4, the bottom of the grid 6 is lower than the bottom of the emitter 4, a Schottky tunneling junction controlled by the grid 6 is formed between the bottom of the emitter 4 and the n-drift layer 3, when voltage is applied to the grid, the Schottky tunneling junction can generate tunneling current, and the electrical isolation is realized on the boundary of the overlapping area in the vertical direction through the grid dielectric layer 5.
Furthermore, the gate dielectric layer 5 is made of SiN or SiO2Or Al2O3Or HfO2A medium.
Further, the passivation layer 8 is made of SiN or SiO2Or Al2O3Or HfO2A medium.
Furthermore, the material of the emitter 4 adopts Ti/Au or W/Au or Mo/Au or Ni/Au or Pt/Au or Pd/Au.
Further, the gate electrode 6 and the metal thickening layer 7 are made of the same material.
Preferably, the material of the gate electrode 6 is Ni/Au or Pt/Au or Pd/Au or W/Au or Ni/Au/Ni.
Further, the upper surface and the lower surface of the emitter 4 have an overlapping region with the gate 6 in the extension of the horizontal direction, the bottom of the gate 6 is lower than the bottom of the emitter 4, and the gate 6 and the emitter 4 are electrically isolated by the gate dielectric layer 4.
The grid 6 and the emitter 4 have a partial overlapping region, the grid 6 and the emitter 4 in the overlapping region are electrically isolated by the grid dielectric layer 4, the overlapping region is where the grid 6 and the emitter 4 overlap, electrons can tunnel from the emitter 4 to the n-drift layer 3 so as to conduct electricity, and then an interface above a tunneling interface is the grid overlapped with the interface, which is equivalent to that the grid can control the tunneling of electrons, so that a device is turned on or turned off.
Further, the material of the collector 9 is Ni/Au or Ni/Pt/Au or Pd/Au or Ni/Pd/Au.
The emitter of the invention adopts specific metal, the emitter metal and the n-drift layer form a Schottky junction, a grid is arranged above the overlapping region, and the width of a Schottky barrier can be modulated by grid voltage, so that the tunneling probability of electrons is changed, and the tunneling current is further controlled. When the grid voltage is lower than the threshold voltage, the Schottky barrier width is larger, the tunneling current is very small, and the device is in a turn-off state; when the gate voltage is higher than the threshold voltage, the schottky barrier width is narrowed, the tunneling current is rapidly increased, and the device is turned on.
The semiconductor vertical IGBT can be used for medium-frequency, medium-power and high-power switching circuits and conversion and control of electric energy.
The invention simplifies the process manufacturing process of the IGBT power device, enables the IGBT power device to realize the function of the device without a P-type base region, improves the breakdown voltage of the device and reduces the on-resistance of the device, thereby improving the high output power performance of the device.
The Schottky tunneling junction formed by the invention can control the Schottky barrier width through the grid voltage, thereby controlling the tunneling probability and generating high electron current density. The invention does not need the base region of the P-type wide bandgap material, and a Schottky tunneling junction is formed by arranging the emitter in the groove of the n-drift layer, and the blocking capability can be provided by the Schottky barrier.
The base region of the IGBT device of the invention does not have PN junction, so the device has high response speed and can be used as a high-speed device. And due to the unique topological structure of the device, parasitic triode effect does not exist, and latch-up effect is eliminated.
Because the emitter near the grid forms a Schottky tunneling junction, metal electrons can be tunneled into the semiconductor to conduct only by adding forward threshold voltage on the grid, so that the device can be in a normally-closed state when not in operation, the threshold voltage of the device is increased, and the reliability and stability of the IGBT power device and a system level are improved.
The IGBT power device is simple in structure, the manufacturing process of the device is simple, and the yield of the device is improved.
It should be noted that, the form of the metal material provided by the present invention is a/B, which means that the first layer is a and the second layer is B from bottom to top, for example, Ni/Au, means that the first layer is Ni and the second layer is Au from bottom to top.
Example two
Referring to fig. 2, fig. 2 is a schematic diagram of a manufacturing process of a vertical semiconductor IGBT based on a vertical schottky tunneling emitter junction according to an embodiment of the present invention. The invention further provides a preparation method of the semiconductor vertical IGBT based on the longitudinal Schottky tunneling emitter junction on the basis of the embodiment, and the preparation method comprises the following steps:
Specifically, pretreatment for removing dangling bonds is performed on the surface of the P + substrate layer 1.
Further, the surface of the P + substrate layer 1 is cleaned and pretreated to eliminate dangling bonds on the surface of the P + substrate layer 1, and is subjected to H treatment at a temperature of 900-1200 DEG C2And (3) an atmosphere reaction chamber, and removing pollutants on the surface of the P + substrate layer 1 through heat treatment.
Preferably, the P + substrate layer 1 is made of a wide bandgap material such as GaN, AlN, SiC, GaO, diamond or BN.
And 2, growing an n + buffer layer 2 on the P + substrate layer 1.
Specifically, the n + buffer layer 2 is grown on the P + substrate layer 1 using an MOCVD (Metal-organic Chemical Vapor Deposition) process.
Furthermore, the n + buffer layer 2 is made of wide bandgap material such as GaN, AlN, SiC, GaO, diamond or BN, the thickness of the n + buffer layer 2 is 0.1-100 μm, and the doping concentration of the n + buffer layer 2 is 1014～1020cm-3。
And 3, growing an n-drift layer 3 on the n + buffer layer 2.
Specifically, the n-drift layer 3 is grown on the n + buffer layer 2 using the MOCVD process.
Furthermore, the material of the n-drift layer 3 adopts wide bandgap materials such as GaN, AlN, SiC, GaO, diamond or BN and the like, the thickness of the n-drift layer 3 is 1-1000 mu m, and the doping concentration of the n-drift layer 3 is 1014～1020cm-3。
And 4, etching two first-stage steps 10 at two ends of the n-drift layer 3.
Specifically, a mask is made on the n-drift layer 3, which is placed in a RIE system in Cl2And BCl3The open area in the mask is etched in a gas atmosphere, and two first level steps 10 are etched at both ends of the n-drift layer 3, for example, to a depth of 150 nm.
And 5, manufacturing a collector electrode 9 on the lower surface of the P + substrate layer 1.
Specifically, a collector metal is deposited on the lower surface of the P + substrate layer 1 by using a metal evaporation or magnetron sputtering process to manufacture the collector 9.
Further, the material of the collector 9 is Ni/Au or Ni/Pt/Au or Pd/Au or Ni/Pd/Au.
And 6, manufacturing two emitting electrodes 4 at two ends of the upper surface of the n-drift layer 3 without the first-stage step 10.
Specifically, a mask is made on the n-drift layer 3, and emitter metal is deposited by using a metal evaporation or magnetron sputtering process.
Furthermore, the material of the emitter 4 adopts Ti/Au or W/Au or Mo/Au or Ni/Au or Pt/Au or Pd/Au.
And 7, etching the n-drift layer 3 between the two emitter electrodes 4 to form a groove, wherein the emitter electrodes 4 are arranged on the second-stage steps 11.
Specifically, an RIE, ICP or RIE-ICP slow etching process is selected, an area to be etched is etched, and a groove with the etching depth of 10 nm-100 nm is exposed.
And 8, growing a gate dielectric layer 5 on the groove of the n-drift layer 3 and the two emitters 4.
Specifically, emitter metal is deposited on the groove of the n-drift layer 3 and the two emitters 4 by adopting a metal evaporation or magnetron sputtering process to manufacture the emitters 4, and the emitters 4 and the side wall wide bandgap material of the second-stage step 11 form a gate-controlled schottky tunneling junction.
And 8, growing a gate dielectric layer 5 on the n-drift layer 3 and the two emitters 4.
Specifically, a gate dielectric layer 5 with a thickness of 5-500 nm is deposited on the groove of the n-drift layer 3 and the two emitters 4 by using a CVD (Chemical vapor deposition) or ALD (Atomic layer deposition) process.
Furthermore, the gate dielectric layer 5 is made of SiN or SiO2Or Al2O3Or HfO2A medium.
And 9, manufacturing a grid electrode 6 on the grid dielectric layer 5 positioned in the groove of the n-drift layer 3, and simultaneously respectively manufacturing metal thickening layers 7 on the emitter electrode 4 and the grid dielectric layer 5 positioned at two ends of the n-drift layer 3, wherein the lower surface of the grid electrode 6 is lower than the lower surface of the emitter electrode 4.
And 9.1, manufacturing a mask on the gate dielectric layer 5, and etching a metal thickening area window on the gate dielectric layer 5 above the two emitting electrodes 4.
Specifically, a mask is manufactured on the gate dielectric layer 5 above the emitter 4, and the gate dielectric layer 5 above the emitter 4 is etched by adopting a dry etching process or a wet etching process to form a metal thickening region window of the emitter 4.
And 9.2, depositing grid metal in the groove of the grid dielectric layer 5 and the window of the metal thickening region to form a grid 6 and two metal thickening layers 7.
Specifically, a metal evaporation or magnetron sputtering process is adopted to deposit and form a grid electrode 6 and a metal thickening layer 7 in a groove of the grid dielectric layer 5 and on a window of a metal thickening region, the metal thickening layer 7 is used for thickening the emitter electrode 4, and the length of an overlapping region of the grid electrode 6 and the emitter electrode 4 is 0.1-10 mu m.
Further, the material of the gate electrode 6 is Ni/Au or Pt/Au or Pd/Au or W/Au or Ni/Au/Ni.
And 10, growing a passivation layer 8 on the n-drift layer 3, the gate dielectric layer 5, the gate electrode 6 and the two metal thickening layers 7.
Specifically, a passivation layer 8 is deposited on the n-drift layer 3, the gate dielectric layer 5, the gate electrode 6 and the two metal thickening layers 7 by using a PECVD (Plasma Enhanced Chemical Vapor Deposition) process.
Further, the passivation layer 8 is made of SiN or SiO2Or Al2O3Or HfO2A medium.
And 11, photoetching and etching the passivation layers 8 on the emitter 4 and the grid 6 to form an emitter contact hole and a grid contact hole, and finishing the manufacture of the device.
EXAMPLE III
In this embodiment, a method for manufacturing a vertical semiconductor IGBT based on a vertical schottky tunneling emitter junction according to the present invention is described in a specific embodiment based on the above embodiments, where a P + substrate layer 1, an n + buffer layer 2, and an n-drift layer 3 are made of GaN, and a doping concentration of the n-drift layer 3 is 1016cm-3The emitter 4 is made of Ti/Au, and the collector 9 is made of Ti/AuThe preparation method of the semiconductor vertical IGBT which is a longitudinal Schottky tunneling emission junction of Ni/Au comprises the following steps:
Step 1.1, soaking the P + substrate layer 1 of the GaN material in HF acid solution for 1min, sequentially placing the HF acid solution, the anhydrous ethanol solution and deionized water in sequence, and performing ultrasonic cleaning for 10min respectively, wherein the cleaned P + substrate layer 1 of the GaN material is cleaned by N2And (5) drying.
Step 1.2, cleaning and drying the cleaned and dried GaN material P + substrate layer 1 in H2And (3) performing heat treatment at the temperature of 1000 ℃ in the atmosphere reaction chamber to remove surface pollutants.
And 2, manufacturing an n + buffer layer 2 made of the GaN material.
Putting the P + substrate layer 1 of the pretreated GaN material into an MOCVD system, and growing a doping concentration of 10 with the thickness of 5 mu m on the P + substrate layer 1 of the pretreated GaN material18cm-3The process conditions of the n + buffer layer 2 of GaN material are as follows:
setting the pressure of the chamber to be 20Torr and the temperature to be 900 ℃;
three gases were simultaneously introduced into the chamber: a gallium source at a flow rate of 20 μmol/min, hydrogen at a flow rate of 1000sccm, and ammonia at a flow rate of 2000 sccm.
And 3, manufacturing the n-drift layer 3 of the GaN material.
After the n + buffer layer 2 of the GaN material is manufactured, a gallium source with the flow rate of 40 mu mol/min, hydrogen with the flow rate of 2000sccm and ammonia with the flow rate of 4000sccm are simultaneously introduced into the reaction chamber, and the n + buffer layer 2 of the GaN material is grown to the thickness of 50 mu m and the doping concentration of 1016cm-3An n-drift layer 3 of GaN material.
And 4, etching the first step 10.
And putting the sample after the process is finished into an RIE etching cavity, simultaneously introducing CF4 with the flow rate of 20sccm and O2 with the flow rate of 2sccm, setting the process conditions of the pressure of 5mT and the power of 100W, and etching the first-stage step 10 with the depth of 150nm on the n-drift layer 3 of the GaN material.
And 5, manufacturing a collector electrode 9.
Putting the sample after the above process into a magnetron sputtering reaction chamber, and keeping the pressure of the reaction chamber at 9.0 × 10- 2Pa, using nickel and gold targets with the purity of 99.999 percent, depositing metal Ni/Au on the back side of the device to be used as a collector electrode 9, and carrying out annealing treatment at the temperature of 500 ℃ in the atmosphere to form ohmic contact with the P + substrate layer 1 of the GaN material.
And 6, manufacturing the emitter 4.
Putting the sample after the above process into a magnetron sputtering reaction chamber, and keeping the pressure of the reaction chamber at 9.0 × 10- 2Pa, depositing metal Ti/Au with the thickness of 15nm/5nm at two ends of the upper surface of the n-drift layer 3 without the first-stage step 10 as an emitter 4 by utilizing titanium and gold target materials with the purity of 99.999 percent.
And 7, etching the grid electrode groove.
Putting the sample after the above process into an RIE etching chamber, and simultaneously introducing CF with the flow rate of 20sccm4And O at a flow rate of 4sccm2Setting the process conditions of 5mT pressure and 150W power, making a mask and etching the n-drift layer 3 between the two emitting electrodes 4 to form a groove with the depth of 30 nm.
And 8, manufacturing a gate dielectric layer 5.
Putting the sample after the above process into a PEALD reaction chamber, and depositing 10nm of Al on the groove of the n-drift layer 3 and the emitter 4 at a high temperature of 400 DEG C2O3To fabricate a gate dielectric layer 5.
And 9, etching the window of the metal thickening region.
Making a mask on the gate dielectric layer 5, putting the sample after the above process into an RIE etching chamber, and simultaneously introducing CF with the flow of 20sccm4And O at a flow rate of 4sccm2Setting the process conditions of 5mT pressure and 150W power, and etching a metal thickening area window with the depth of 10nm on the gate dielectric layer 5 above the emitter 4.
And 10, manufacturing a grid electrode 6 and a metal thickening layer 7.
The sample after the above process is completedPlacing into a magnetron sputtering reaction chamber, and maintaining the pressure in the reaction chamber at 9.0 × 10- 2And Pa, depositing metal Ni/Au with the metal thickness of 50nm/150nm on the gate dielectric layer 5 and the window of the metal thickening region by using nickel and gold target materials with the purity of 99.999 percent respectively as a gate 6 and a metal thickening layer 7.
And 11, manufacturing the passivation layer 8.
The sample subjected to the above steps is placed in a PECVD reaction chamber, and 1 μm SiN is deposited at a high temperature of 400 ℃ to form a passivation layer 8.
And step 12, manufacturing an emitter contact hole and a grid contact hole.
And photoetching and etching the passivation layer 8 on the emitter 4 and the grid 6 to form an emitter contact hole and a grid contact hole, and finishing the manufacture of the whole device.
Example four
In this embodiment, a method for manufacturing a vertical semiconductor IGBT based on a vertical schottky tunneling emitter junction according to the present invention is described in a specific embodiment based on the above embodiments, where a P + substrate layer 1, an n + buffer layer 2, and an n-drift layer 3 are made of AlN, and the doping concentration of the n-drift layer 3 is 1017cm-3The emitter 4 is made of W/Au, the collector 9 is made of Ni/Au vertical Schottky tunneling emitter junction semiconductor vertical IGBT, and the preparation method comprises the following steps:
Step 1.1, soaking the P + substrate layer 1 of the AlN material in HF acid solution for 1min, sequentially placing the solution in acetone solution, absolute ethyl alcohol solution and deionized water for ultrasonic cleaning for 10min, and using N to clean the P + substrate layer 1 of the AlN material after cleaning2And (5) drying.
Step 1.2, cleaning and drying the P + substrate layer 1 of the AlN material in H2And (3) performing heat treatment at the temperature of 1000 ℃ in the atmosphere reaction chamber to remove surface pollutants.
And 2, manufacturing an n + buffer layer 2 made of the AlN material.
Putting the n + buffer layer 2 of the pretreated AlN material into an MOCVD system, and pretreatingIs grown on the n + buffer layer 2 of AlN material to a thickness of 5 μm and a doping concentration of 1018cm-3The n + buffer layer 2 of AlN material has the following process conditions:
setting the pressure of the chamber to be 20Torr and the temperature to be 900 ℃;
three gases were simultaneously introduced into the chamber: an aluminum source at a flow rate of 30 μmol/min, hydrogen at a flow rate of 1200sccm, and ammonia at a flow rate of 2000 sccm.
And 3, manufacturing an n-drift layer 3 made of the AlN material.
After the n + buffer layer 2 of AlN material was prepared, an aluminum source with a flow rate of 60. mu. mol/min, hydrogen with a flow rate of 3000sccm, and ammonia with a flow rate of 4000sccm were simultaneously introduced into the reaction chamber, and 100 μm thick and 10-doped concentration were grown on the n + buffer layer 2 of AlN material17cm-3An n-drift layer 3 of AlN material.
And 4, etching the first step 10.
And putting the sample after the process is finished into an RIE etching cavity, simultaneously introducing CF4 with the flow rate of 20sccm and O2 with the flow rate of 5sccm, setting the process conditions of the pressure of 5mT and the power of 150W, and etching the first-stage step 10 with the depth of 200nm on the n-drift layer 3 of the AlN material.
And 5, manufacturing a collector electrode 9.
Putting the sample after the above process into a magnetron sputtering reaction chamber, and keeping the pressure of the reaction chamber at 9.0 × 10- 2Pa, using nickel and gold targets with the purity of 99.999 percent, depositing metal Ni/Au on the back side of the device to be used as a collector electrode 9, and carrying out annealing treatment at the temperature of 600 ℃ in the atmosphere to form ohmic contact with the P + substrate layer 1 of the AlN material.
And 6, manufacturing the emitter 4.
Putting the sample after the above process into a magnetron sputtering reaction chamber, and keeping the pressure of the reaction chamber at 9.0 × 10- 2Pa, depositing metal W/Au with the thickness of 20nm/10nm on the second step 11 as the emitter 4 by utilizing titanium and gold target materials with the purity of 99.999 percent, wherein the total thickness of the emitter 4 is consistent with the depth of the second step 11.
And 7, etching the grid electrode groove.
Putting the sample after the above process into an RIE etching chamber, and simultaneously introducing CF with the flow rate of 20sccm4And O at a flow rate of 4sccm2Setting the process conditions of 5mT pressure and 150W power, making a mask and etching the n-drift layer 3 between the two emitting electrodes 4 to form a groove with the depth of 30 nm.
And 8, manufacturing a gate dielectric layer 5.
Putting the sample after the above process into a PEALD reaction chamber, and depositing 20nm of Al on the grooves of the n-drift layer 3 and the emitter 4 at the high temperature of 400 DEG C2O3To fabricate a gate dielectric layer 5.
And 9, etching the window of the metal thickening region.
Making a mask on the gate dielectric layer 5, putting the sample after the above process into an RIE etching chamber, and simultaneously introducing CF with the flow of 20sccm4And O at a flow rate of 4sccm2Setting the process conditions of 5mT pressure and 200W power, and etching a metal thickening area window with the depth of 20nm on the gate dielectric layer 5 above the emitter 4.
And 10, manufacturing a grid electrode 6 and a metal thickening layer 7.
Putting the sample after the above process into a magnetron sputtering reaction chamber, and keeping the pressure of the reaction chamber at 9.0 × 10- 2And Pa, depositing metal Ni/Au with the metal thickness of 50nm/150nm on the gate dielectric layer 5 and the window of the metal thickening region by using nickel and gold target materials with the purity of 99.999 percent respectively as a gate 6 and a metal thickening layer 7.
And 11, manufacturing the passivation layer 8.
The sample subjected to the above steps was placed in a PECVD reaction chamber, and 1.5 μm SiN was deposited at a high temperature of 400 c to fabricate the passivation layer 8.
And step 12, manufacturing an emitter contact hole and a grid contact hole.
And photoetching and etching the passivation layer 8 on the emitter 4 and the grid 6 to form an emitter contact hole and a grid contact hole, and finishing the manufacture of the whole device.
In the description of the present invention, the terms "first" and "second" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implying any number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present invention, "a plurality" means two or more unless specifically defined otherwise.
In the description herein, references to the description of the term "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., mean that a particular feature, structure, material, or characteristic data point described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above are not necessarily intended to refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, various embodiments or examples described in this specification can be combined and combined by those skilled in the art.
The foregoing is a more detailed description of the invention in connection with specific preferred embodiments and it is not intended that the invention be limited to these specific details. For those skilled in the art to which the invention pertains, several simple deductions or substitutions can be made without departing from the spirit of the invention, and all shall be considered as belonging to the protection scope of the invention.
Claims (9)
1. A vertical Schottky tunneling emitter junction-based semiconductor IGBT, comprising:
a P + substrate layer (1);
an n + buffer layer (2), the n + buffer layer (2) being disposed on the P + substrate layer (1);
the n-drift layer (3) is arranged on the n + buffer layer (2), two-stage steps are arranged at two ends of the n-drift layer (3), a groove is further arranged between the two-stage steps, the two-stage steps comprise a first-stage step (10) and a second-stage step (11), the first-stage step (10) is located below the second-stage step (11), and the second-stage step (11) is close to the center of the n-drift layer (3);
the two emitting electrodes (4), the two emitting electrodes (4) are respectively arranged on the second-stage steps (11) at two ends of the n-drift layer (3);
the gate dielectric layer (5) is arranged on the groove of the n-drift layer (3) and the two emitting electrodes (4);
the grid electrode (6) is arranged on the grid dielectric layer (4) in the groove of the n-drift layer (3), and the lower surface of the grid electrode (6) is lower than the lower surface of the emitter electrode (4);
two metal thickening layers (7), wherein one metal thickening layer (7) is arranged on the emitter (4) and the gate dielectric layer (5) which are positioned at one end, the other metal thickening layer (7) is arranged on the emitter (4) and the gate dielectric layer (5) which are positioned at the other end, and a gap is formed between the grid electrode (6) and the metal thickening layers (7);
the passivation layer (8), the passivation layer (8) is arranged on the n-drift layer (3), the gate dielectric layer (5), the gate electrode (6) and the two metal thickening layers (7);
and the collector electrode (9), wherein the collector electrode (9) is arranged on the lower surface of the P + substrate layer (1).
2. Semiconductor vertical IGBT according to claim 1, characterized in that the material of the P + substrate layer (1), the n + buffer layer (2) and the n-drift layer (3) is GaN, AlN, SiC, GaO, diamond or BN.
3. The semiconductor vertical IGBT according to claim 1, characterized in that the material of the gate dielectric layer (5) and the passivation layer (8) is SiN or SiO2Or Al2O3Or HfO2。
4. Semiconductor vertical IGBT according to claim 1, characterized in that the material of the emitter (4) is Ti/Au, W/Au, Mo/Au, Ni/Au, Pt/Au or Pd/Au.
5. Semiconductor vertical IGBT according to claim 1, characterized in that the gate (6) and the metal thickening layer (7) are of the same material.
6. Semiconductor vertical IGBT according to claim 5, characterized in that there is an overlap region between the extension of the upper and lower surfaces of the emitter (4) in the horizontal direction and the gate (6).
7. A preparation method of a vertical semiconductor IGBT based on a vertical Schottky tunneling emitter junction is used for preparing the vertical semiconductor IGBT according to any one of claims 1 to 6, and the preparation method comprises the following steps:
selecting a P + substrate layer (1);
growing an n + buffer layer (2) on the P + substrate layer (1);
growing an n-drift layer (3) on the n + buffer layer (2);
etching two first-stage steps (10) at two ends of the n-drift layer (3);
manufacturing a collector electrode (9) on the lower surface of the P + substrate layer (1);
manufacturing two emitting electrodes (4) at two ends of the upper surface of the n-drift layer (3) without the first-level steps (10);
etching the n-drift layer (3) between the two emitter electrodes (4) to form a groove, wherein the emitter electrodes (4) are arranged on the second-level steps (11);
growing a gate dielectric layer (5) on the groove of the n-drift layer (3) and the two emitters (4);
manufacturing a grid electrode (6) on the grid dielectric layer (5) in the groove of the n-drift layer (3), simultaneously respectively manufacturing metal thickening layers (7) on the emitter electrode (4) and the grid dielectric layer (5) which are positioned at two ends of the n-drift layer (3), wherein the lower surface of the grid electrode (6) is lower than the lower surface of the emitter electrode (4);
and growing a passivation layer (8) on the n-drift layer (3), the gate dielectric layer (5), the grid electrode (6) and the two metal thickening layers (7).
8. The method for preparing a semiconductor vertical IGBT according to claim 7, characterized in that after the P + substrate layer (1) is selected, the method further comprises the following steps:
and (3) preprocessing the surface of the P + substrate layer (1) to eliminate dangling bonds.
9. The method for manufacturing a semiconductor vertical IGBT according to claim 7, wherein the step of manufacturing a gate electrode (6) in a groove of the gate dielectric layer (5) and simultaneously manufacturing metal thickening layers (7) on the emitter (4) and the gate dielectric layer (5) at two ends of the n-drift layer (3) respectively comprises the following steps:
manufacturing a mask on the gate dielectric layer (5), and etching a metal thickening area window on the gate dielectric layer (5) above the two emitting electrodes (4);
and depositing grid metal in the groove of the grid dielectric layer (5) and the metal thickening region window to form a grid (6) and two metal thickening layers (7).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011490832.8A CN112614884A (en) | 2020-12-16 | 2020-12-16 | Semiconductor vertical IGBT based on longitudinal Schottky tunneling emitter junction and preparation method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011490832.8A CN112614884A (en) | 2020-12-16 | 2020-12-16 | Semiconductor vertical IGBT based on longitudinal Schottky tunneling emitter junction and preparation method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN112614884A true CN112614884A (en) | 2021-04-06 |
Family
ID=75239935
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202011490832.8A Pending CN112614884A (en) | 2020-12-16 | 2020-12-16 | Semiconductor vertical IGBT based on longitudinal Schottky tunneling emitter junction and preparation method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN112614884A (en) |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5049953A (en) * | 1989-01-18 | 1991-09-17 | Nissan Motor Co., Ltd. | Schottky tunnel transistor device |
| US5962893A (en) * | 1995-04-20 | 1999-10-05 | Kabushiki Kaisha Toshiba | Schottky tunneling device |
| CN103026491A (en) * | 2010-07-06 | 2013-04-03 | 香港科技大学 | Normally-off III-nitride metal-2DEG tunnel junction field-effect transistors |
| EP3255676A1 (en) * | 2016-06-09 | 2017-12-13 | ABB Schweiz AG | Vertical power semiconductor device and method for operating such a device |
| CN112038408A (en) * | 2020-09-04 | 2020-12-04 | 西安电子科技大学 | Vertical aluminum nitride metal oxide semiconductor field effect transistor based on silicon carbide substrate and preparation method |
-
2020
- 2020-12-16 CN CN202011490832.8A patent/CN112614884A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5049953A (en) * | 1989-01-18 | 1991-09-17 | Nissan Motor Co., Ltd. | Schottky tunnel transistor device |
| US5962893A (en) * | 1995-04-20 | 1999-10-05 | Kabushiki Kaisha Toshiba | Schottky tunneling device |
| CN103026491A (en) * | 2010-07-06 | 2013-04-03 | 香港科技大学 | Normally-off III-nitride metal-2DEG tunnel junction field-effect transistors |
| EP3255676A1 (en) * | 2016-06-09 | 2017-12-13 | ABB Schweiz AG | Vertical power semiconductor device and method for operating such a device |
| CN112038408A (en) * | 2020-09-04 | 2020-12-04 | 西安电子科技大学 | Vertical aluminum nitride metal oxide semiconductor field effect transistor based on silicon carbide substrate and preparation method |
Non-Patent Citations (1)
| Title |
|---|
| 汤晓燕 等: "SiC肖特基接触的直接隧穿效应", 《半导体学报》 * |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN208861993U (en) | Normally-off high electron mobility transistor | |
| CN101414633B (en) | Groove insulated gate type composite gate field plate device with high electron mobility | |
| CN102569378A (en) | Compound semiconductor device and method of manufacturing the same | |
| CN105336789A (en) | GaN-based field effect transistor with high quality MIS structure and preparation method of GaN-based field effect transistor | |
| CN101414623B (en) | Groove gate type source-leakage composite field plate heterojunction field effect transistor and preparation method thereof | |
| CN102082176A (en) | Gallium nitride (GaN) enhancement type metal insulator semiconductor field effect transistor (MISFET) device and manufacturing method thereof | |
| CN110581068A (en) | Method for realizing low-on-resistance enhanced gallium nitride transistor by using gate dielectric | |
| CN107706241A (en) | A kind of normally-off GaNMOSFET structures at high quality MOS interfaces and preparation method thereof | |
| CN109873034A (en) | Normally-off HEMT power device of deposit polycrystalline AlN and preparation method thereof | |
| CN115472689A (en) | High-electron-mobility transistor with super junction structure and preparation method thereof | |
| CN101414634B (en) | Heterojunction field effect transistor for groove insulated gate type multiple source field plate | |
| CN112599603A (en) | Quasi-vertical field effect transistor based on longitudinal Schottky source tunneling junction and method | |
| CN101414622B (en) | Composite field plate heterojunction field effect transistor based on source field plate and leakage field plate | |
| CN113903802A (en) | Array strip-based enhancement type switch transistor and manufacturing method thereof | |
| CN103745990B (en) | Depletion-mode AlGaN/GaN MISHEMT high tension apparatus and preparation method thereof | |
| CN210897283U (en) | Semiconductor device with a plurality of transistors | |
| CN101419982B (en) | High electron mobility device for trench gate type source field board and manufacturing method therefor | |
| CN112614889A (en) | All-vertical field effect transistor based on longitudinal Schottky source tunneling junction and method | |
| CN101414636B (en) | Groove insulated gate type source-leakage composite field plate transistor with high electron mobility | |
| CN112614890A (en) | All-vertical field effect transistor based on transverse Schottky source tunneling junction and method | |
| CN103762234B (en) | Based on the AlGaN/GaN MISHEMT high tension apparatus and preparation method thereof of super junction leakage field plate | |
| CN207664049U (en) | A kind of normally-off GaNMOSFET structures at the interfaces high quality MOS | |
| CN112614888A (en) | Quasi-vertical field effect transistor based on transverse Schottky source tunneling junction and method | |
| CN112614884A (en) | Semiconductor vertical IGBT based on longitudinal Schottky tunneling emitter junction and preparation method | |
| CN112614883A (en) | Semiconductor vertical IGBT based on transverse Schottky tunneling emitter junction and preparation method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |