CN112614890A - All-vertical field effect transistor based on transverse Schottky source tunneling junction and method - Google Patents
All-vertical field effect transistor based on transverse Schottky source tunneling junction and method Download PDFInfo
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Abstract
The invention discloses a full-vertical field effect transistor based on a transverse Schottky source tunneling junction and a method, wherein the method comprises the following steps: the transistor comprises a substrate layer (1), an n + buffer layer (2), an n-drift layer (3), a gate dielectric layer (4), a drain electrode (5), a grid electrode (6), two source electrodes (7) and two metal thickening layers (8). The device is enhanced, so that the noise suppression of the device and the safety of a circuit are improved, and the enhanced device has good compatibility with the conventional gate drive circuit. The invention can successfully avoid the problems of low activation rate of the P-type dopant, difficulty in realizing ohmic contact of the P-type material layer and the like in the wide bandgap semiconductor material. The invention controls the tunneling current of the Schottky source electrode by using the gate voltage, and can realize high current density.
Description
Technical Field
The invention belongs to the technical field of semiconductor devices, and particularly relates to a full-vertical field effect transistor based on a transverse Schottky source tunneling junction and a method.
Background
With the decreasing of the available environmental resources, the performance requirements of high power semiconductor devices applied to power electronic equipment for power conversion and under high voltage and high current density are higher and higher, and the development of novel power devices with excellent performance and high conversion efficiency is one of the effective solutions for solving the conflict between energy and environment. For a high-power semiconductor device, the power quality factor of the high-power semiconductor device mainly depends on the breakdown voltage and the specific on-resistance of the device, but both of the devices often need to be optimized and designed comprehensively to effectively improve the performance of the power device. With the continuous development of the field of semiconductor power devices, the performance of the power devices is fundamentally changed from the first generation of Si materials to the second generation of GaAs materials.
However, so far, the performance of semiconductor power devices made of traditional two-generation materials has approached the theoretical limit determined by the material properties. The third generation semiconductor broadband materials represented by GaN have the characteristics of high frequency, high power, radiation resistance, high saturated electron mobility and the like, and have excellent potential in the aspect of power electronics. At present, GaN devices are mainly divided into lateral devices and vertical devices, the lateral devices represented by high-electron mobility transistors (HEMTs) have great advantages in the radio frequency field, and the vertical devices are more suitable for the power electronic field. Compared with a transverse device, the vertical device can improve the breakdown characteristic of the device only by increasing the thickness of the drift region of the device without sacrificing the transverse size of a chip, so that the vertical device has higher power density. In addition, the conducting channel of the vertical device is wide, the current density is high, and the conducting channel of the vertical device is located inside the device, so that the device is not easily influenced by a surface state and has good dynamic characteristics. The advantages mentioned above make the vertical device have the advantage of being extremely thick in the power electronics field. At present, the GaN vertical device mainly comprises three structures, namely, a CAVET (current aperture vertical electronic transistor), a trench MOSFET (trench metal oxide semiconductor field effect transistor) and a Fin.
For the CAVET structure, the device is a depletion mode device, the manufacturing process of the device is complex, the leakage under high-voltage bias is large, and the reliability is poor; although the trench MOSFET can easily realize enhancement, the process of the device is complicated, especially the ohmic contact of P-type GaN is difficult to realize, and in addition, the material damage caused by the etching process can also cause the degradation of the electron mobility of the channel, which affects the on-resistance of the device; although the Fin structure can also realize enhancement, the Fin structure has narrow conductive channel and small current density, and cannot meet the application requirement of high power.
Disclosure of Invention
In order to solve the problems in the prior art, the invention provides a full-vertical field effect transistor based on a transverse Schottky source tunneling junction and a preparation method thereof. The technical problem to be solved by the invention is realized by the following technical scheme:
an all-vertical field effect transistor based on a lateral schottky source tunneling junction, comprising:
a substrate layer;
an n + buffer layer disposed on the substrate layer;
the n-drift layer is arranged on the n + buffer layer, two-stage steps are arranged at two ends of the n-drift layer, the two-stage steps comprise a first-stage step and a second-stage step, the first-stage step is positioned below the second-stage step, and the second-stage step is close to the center of the n-drift layer;
the two source electrodes are respectively arranged on the second-stage steps at two ends of the n-drift layer, and the upper surface of each source electrode is flush with the upper surface of the n-drift layer;
the gate dielectric layer is arranged on the n-drift layer and the two source electrodes;
the grid electrode is arranged on the grid dielectric layer;
the gate electrode is arranged between the two metal thickening layers, and a gap is formed between the gate electrode and the metal thickening layers;
the drain electrode is arranged on the lower surface of the substrate layer;
the substrate layer, the n + buffer layer and the n-drift layer are made of the same material.
In one embodiment of the invention, the substrate layer, the n + buffer layer and the n-drift layer are made of GaN, AlN, SiC, GaO, diamond or BN material.
In one embodiment of the present invention, the n + buffer layer has a doping concentration of 1018cm-3～1020cm-3The doping concentration of the n-drift layer is 1015cm-3～1017cm-3。
In one embodiment of the invention, the source electrode is made of Ti/Au, W/Au, Mo/Au, Ni/Au, Pt/Au or Pd/Au, and the drain electrode is made of Ti/Al/Ni/Au, Ti/Al/Ti/Au, Ti/Al/Mo/Au, Ta/Al/Ta, Ni/Au, Pt/Au, Pd/Au, W/Au or Ni/Au/Ni.
In one embodiment of the invention, the gate and the metal thickening layer are of the same material.
In one embodiment of the invention, the material of the grid electrode is Ni/Au, Pt/Au, Pd/Au, W/Au or Ni/Au/Ni.
In one embodiment of the invention, an extension line of a side of the gate close to the source intersects with the inside of the source.
The invention also provides a preparation method of the all-vertical field effect transistor based on the transverse Schottky source tunneling junction, which is used for preparing the all-vertical field effect transistor in any one of the embodiments, and the preparation method comprises the following steps:
selecting a substrate layer;
growing an n + buffer layer on the substrate layer;
growing an n-drift layer on the n + buffer layer;
etching two first-stage steps at two ends of the n-drift layer;
manufacturing a drain electrode on the lower surface of the substrate layer;
etching two second steps at two ends of the n-drift layer, wherein the first step is positioned below the second step, and the second step is close to the center of the n-drift layer;
manufacturing two source electrodes on the two second-stage steps at two ends of the n-drift layer, wherein the upper surfaces of the source electrodes are flush with the upper surface of the n-drift layer;
growing a gate dielectric layer on the n-drift layer and the two source electrodes;
and manufacturing a grid electrode on the grid dielectric layer, and simultaneously preparing two metal thickening layers on the source electrode and the grid dielectric layer which are positioned at two ends of the n-drift layer respectively.
In an embodiment of the present invention, fabricating a gate on the gate dielectric layer, and simultaneously preparing two metal thickening layers on the source electrode and the gate dielectric layer at two ends of the n-drift layer, respectively, includes:
manufacturing a mask on the gate dielectric layer, and etching a metal thickening area window on the gate dielectric layer above the two source electrodes;
and depositing grid metal on the grid dielectric layer and the metal thickening area window to form a grid and two metal thickening layers.
The invention has the beneficial effects that:
1. the device is enhanced, so that the noise suppression of the device and the safety of a circuit are improved, and the enhanced device has good compatibility with the conventional gate drive circuit.
2. According to the invention, a P-type material layer is not required, the material layer can be AlN, SiC, GaO, diamond and BN, wherein the SiC material does not have P-type dopant and has low activation rate, so that the problems of low activation rate of P-type dopant, difficulty in realizing P-type ohmic contact and the like existing in other P-type material layers except the SiC material can be successfully avoided.
3. The invention controls the tunneling current of the Schottky source electrode by using the gate voltage, and can realize high current density.
4. The device has simple structure, does not need complex process flow, saves cost and improves the yield.
5. The device in the invention does not need PN junction, has high response speed and can be used as a high-speed device.
6. Due to the unique topological structure of the device, the parasitic triode effect does not exist, and the latch-up effect is eliminated.
The present invention will be described in further detail with reference to the accompanying drawings and examples.
Drawings
Fig. 1 is a schematic structural diagram of an all-vertical field effect transistor based on a lateral schottky source tunneling junction according to an embodiment of the present invention;
fig. 2 is a schematic view of a manufacturing process of an all-vertical field effect transistor based on a lateral schottky source tunneling junction according to an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to specific examples, but the embodiments of the present invention are not limited thereto.
Example one
Referring to fig. 1, fig. 1 is a schematic structural diagram of an all-vertical field effect transistor based on a lateral schottky source tunneling junction according to an embodiment of the present invention. The embodiment provides a full-vertical field effect transistor based on a transverse Schottky source tunneling junction, which comprises a substrate layer 1, an n + buffer layer 2, an n-drift layer 3, a gate dielectric layer 4, a drain electrode 5, a gate electrode 6, a source electrode 7 and two metal thickening layers 8, wherein the n + buffer layer 2 is arranged on the substrate layer 1, the n-drift layer 3 is arranged on the n + buffer layer 2, two steps are arranged at two ends of the n-drift layer 3, the two steps comprise a first step 9 and a second step 10, the first step 9 is positioned below the second step 10, the second step 10 is close to the center of the n-drift layer 3, the two source electrodes 7 are respectively arranged on the second step 10 at two ends of the n-drift layer 3, and the upper surface of the source electrode 7 is flush with the upper surface of the n-drift layer 3, the gate dielectric layer 4 is arranged on the n-drift layer 3 and the two source electrodes 7, the gate electrode 6 is arranged on the gate dielectric layer 4, one metal thickening layer 8 is arranged on the source electrode 7 and the gate dielectric layer 4 which are positioned at one end, the other metal thickening layer 8 is arranged on the source electrode 7 and the gate dielectric layer 4 which are positioned at the other end, the gate electrode 6 is arranged between the two metal thickening layers 8, a gap exists between the gate electrode 6 and the metal thickening layers 8, the drain electrode 5 is arranged on the lower surface of the substrate layer 1, and the substrate layer 1, the n + buffer layer 2 and the n-drift layer (3) are made of the same material.
Further, the substrate layer 1, the n + buffer layer 2 and the n-drift layer 3 are made of GaN, AlN, SiC, GaO, diamond or BN materials.
Further, the n + buffer layer 2 has a doping concentration of 1018cm-3～1020cm-3。
Further, the doping concentration of the n-drift layer 3 is 1015cm-3～1017cm-3。
Furthermore, the gate dielectric layer 4 is made of SiN or SiO2Or Al2O3Or HfO2A medium.
Further, the drain electrode 5 is made of Ti/Al/Ni/Au, Ti/Al/Ti/Au, Ti/Al/Mo/Au, Ta/Al/Ta, Ni/Au, Pt/Au, Pd/Au, W/Au or Ni/Au/Ni.
Further, the gate electrode 6 and the metal thickening layer 8 are made of the same material.
Furthermore, the extension line of the side of the gate 6 close to the source 7 intersects with the inside of the source 7, so that an overlapping region exists between the gate 6 and the source 7, the gate 6 and the source 7 corresponding to the overlapping region are electrically isolated by the gate dielectric layer 4, the overlapping region is the place where the gate and the source are overlapped, electrons can tunnel from the source 7 to the n-drift layer 3, so that the n-drift layer is conductive, then an interface above the tunneling interface is the interface overlapping the gate, which is equivalent to that the gate can control the tunneling of electrons, so as to turn on or off the device.
Further, the material of the gate electrode 6 is Ni/Au, Pt/Au, Pd/Au, W/Au or Ni/Au/Ni.
Further, the source electrode 7 is made of Ti/Au, W/Au, Mo/Au, Ni/Au, Pt/Au or Pd/Au.
The source electrode of the invention adopts specific metal, the source electrode metal and the n-drift layer form a Schottky junction, a grid electrode is arranged above the overlapping region, and the width of a Schottky barrier can be modulated by grid electrode voltage, so that the tunneling probability of electrons is changed, and the size of tunneling current is further controlled. When the grid voltage is lower than the threshold voltage, the Schottky barrier width is larger, the tunneling current is very small, and the device is in a turn-off state; when the gate voltage is higher than the threshold voltage, the schottky barrier width is narrowed, the tunneling current is rapidly increased, and the device is turned on.
1. The device is enhanced, so that the noise suppression of the device and the safety of a circuit are improved, and the enhanced device has good compatibility with the conventional gate drive circuit.
2. According to the invention, a P-type material layer is not required, the material layer can be AlN, SiC, GaO, diamond and BN, wherein the SiC material does not have P-type dopant and has low activation rate, so that the problems of low activation rate of P-type dopant, difficulty in realizing P-type ohmic contact and the like existing in other P-type material layers except the SiC material can be successfully avoided.
3. The invention controls the tunneling current of the Schottky source electrode by using the gate voltage, and can realize high current density.
4. The device has simple structure, does not need complex process flow, saves cost and improves the yield.
5. The device in the invention does not need PN junction, has high response speed and can be used as a high-speed device.
6. Due to the unique topological structure of the device, the parasitic triode effect does not exist, and the latch-up effect is eliminated.
It should be noted that, the form of the metal material provided by the present invention is a/B, which means that the first layer is a and the second layer is B from bottom to top, for example, Ni/Au, means that the first layer is Ni and the second layer is Au from bottom to top.
Example two
Referring to fig. 2, fig. 2 is a schematic view illustrating a manufacturing process of a lateral schottky source tunneling junction-based all-vertical field effect transistor according to an embodiment of the present invention. The invention further provides a full-vertical field effect transistor based on the transverse Schottky source tunneling junction on the basis of the above embodiment, and the preparation method comprises the following steps:
Specifically, the surface of the substrate layer 1 is subjected to pretreatment for removing dangling bonds.
Further, the surface of the substrate layer 1 is cleaned and pretreated to eliminate dangling bonds on the surface of the substrate layer 1, and is subjected to H at a temperature of 900-1200 DEG C2And (3) an atmosphere reaction chamber for removing pollutants on the surface of the substrate layer 1 through heat treatment.
Preferably, the material of the substrate layer 1 is GaN, AlN, SiC, GaO, diamond or BN material.
And 2, growing an n + buffer layer 2 on the substrate layer 1.
Specifically, the n + buffer layer 2 is grown on the substrate layer 1 using an MOCVD (Metal-organic Chemical Vapor Deposition) process.
Further, the n + buffer layer 2 is made of GaN, AlN, SiC, GaO, diamond or BN material, and the doping concentration of the n + buffer layer 2 is 018cm-3～1020cm-3。
And 3, growing an n-drift layer 3 on the n + buffer layer 2.
Specifically, the n-drift layer 3 is grown on the n + buffer layer 2 using the MOCVD process.
Further, the material of the n-drift layer 3 adopts GaN, AlN, SiC, GaO, diamond or BN material, and the doping concentration of the n-drift layer 3 is 1015cm-3～1017cm-3。
And 4, etching two first-stage steps 9 at two ends of the n-drift layer 3.
Specifically, a mask is made on the n-drift layer 3, the opening region is etched by RIE or ICP, and two first-level steps 9 are etched at both ends of the n-drift layer 3.
And 5, manufacturing a drain electrode 5 on the lower surface of the substrate layer 1.
Specifically, a drain metal is deposited on the lower surface of the substrate layer 1 by using a metal evaporation or magnetron sputtering process to manufacture the drain electrode 5.
Further, the drain electrode 5 is made of Ti/Al/Ni/Au, Ti/Al/Ti/Au, Ti/Al/Mo/Au, Ta/Al/Ta, Ni/Au, Pt/Au, Pd/Au, W/Au or Ni/Au/Ni.
And 6, etching two second steps 10 at two ends of the n-drift layer 3, wherein the first step 9 is positioned below the second step 10, and the second step 10 is close to the center of the n-drift layer 3.
Specifically, a mask is manufactured on the n-drift layer 3 to perform selective etching, an RIE (reactive ion etching) or ICP (inductively coupled plasma) etching process is selected to etch the region to be etched and expose the second-stage step 10 with the etching depth of 20 nm-100 nm, and slow etching is adopted in the etching process to reduce etching damage.
And 7, manufacturing two source electrodes 7 on the two second-stage steps 10 at the two ends of the n-drift layer 3, wherein the upper surfaces of the source electrodes 7 are flush with the upper surface of the n-drift layer 3.
Specifically, a metal evaporation or magnetron sputtering process is adopted to deposit source metal on two second-stage steps 10 at two ends of the n-drift layer 3 to manufacture the source electrode 7, and the source electrode 7 and GaN, AlN, SiC, GaO, diamond or BN material on the side wall of the second-stage step 10 form a gate-controlled Schottky tunneling junction.
Further, the source electrode 7 is made of Ti/Au, W/Au, Mo/Au, Ni/Au, Pt/Au or Pd/Au.
And 8, growing a gate dielectric layer 4 on the n-drift layer 3 and the two source electrodes 7.
Specifically, a PEALD (Plasma Enhanced Atomic Layer Deposition) process is adopted to deposit the gate dielectric Layer 4 with the thickness of 10-30 nm on the n-drift Layer 3 and the two source electrodes 7.
Further, the material of the gate dielectric layer 4 adopts SiN or SiO2Or Al2O3Or HfO2A medium.
And 9, manufacturing a grid electrode 6 on the grid dielectric layer 4, and simultaneously preparing metal thickening layers 8 on the source electrode 7 and the grid dielectric layer 4 which are positioned at two ends of the n-drift layer 3 respectively.
And 9.1, manufacturing a mask on the gate dielectric layer 4, and etching a metal thickening area window on the gate dielectric layer 4 above the two source electrodes 7.
Specifically, a mask is manufactured on the gate dielectric layer 4 above the source electrode 7, and the gate dielectric layer 4 above the source electrode 7 is etched by adopting a dry etching process or a wet etching process to form a metal thickening region window of the source electrode 7.
And 9.2, depositing grid metal on the grid dielectric layer 4 and the metal thickening region window to form a grid 6 and two metal thickening layers 8.
Specifically, a metal evaporation or magnetron sputtering process is adopted to deposit grid metal on the grid dielectric layer 4 and the metal thickening region window to form a grid 6 and a metal thickening layer 8, and the metal thickening layer 8 is used for thickening the source 7.
Further, there is a partial overlap region between the edges of the gate 6 and the source 7.
Further, the material of the gate electrode 6 is Ni/Au, Pt/Au, Pd/Au, W/Au or Ni/Au/Ni.
EXAMPLE III
In this embodiment, a method for manufacturing the lateral schottky source tunneling junction-based all-vertical field effect transistor according to the present invention is described in a specific embodiment based on the above embodiments, where the material manufactured in this embodiment is GaN, and the doping concentration is 1017cm-3The n-drift layer 3 is made of Al2O3The gate dielectric layer 4, the source electrode 7 made of Ti/Au, the drain electrode 5 made of Ti/Al/Ni/Au, and the transverse Schottky source tunneling junction full-vertical field effect transistor with the depth of the second-stage step 10 being 20nm are prepared by the following steps:
Step 1.1, placing the substrate layer 1 of the GaN material into HF acid solution to be soaked for 1min, and then sequentially placing acetoneUltrasonic cleaning in solution, absolute ethyl alcohol solution and deionized water for 10min, and cleaning the substrate layer 1 of the GaN material with N2And (5) drying.
Step 1.2, cleaning and drying the substrate layer 1 of the GaN material in a blowing mode in H2And (3) performing heat treatment at the temperature of 1000 ℃ in the atmosphere reaction chamber to remove surface pollutants.
And 2, manufacturing an n + buffer layer 2 made of the GaN material.
Putting the substrate layer 1 of the pretreated GaN material into an MOCVD system, introducing a Ga source, hydrogen and ammonia gas into a reaction chamber at the same time, and growing a doped concentration of 10 on the substrate layer 1 of the pretreated GaN material18cm-3An n + buffer layer 2 of GaN material.
And 3, manufacturing the n-drift layer 3 of the GaN material.
After the n + buffer layer 2 of the GaN material is manufactured, a Ga source, hydrogen and ammonia gas are simultaneously introduced into the reaction chamber, and the doping concentration of 10 grows on the n + buffer layer 2 of the GaN material17cm-3An n-drift layer 3 of GaN material.
And 4, etching the first step 9.
Making a mask on the n-drift layer 3 of the GaN material, putting the sample after the above process into an RIE etching chamber, and using Cl2And BCl3And etching the opening area in the mask by using gas to form a first-stage step 9 with the etching depth of 150 nm.
And 5, manufacturing the drain electrode 5.
And putting the sample subjected to the process into a magnetron sputtering reaction chamber, depositing metal Ti/Al/Ni/Au on the lower surface of the substrate layer 1 of the GaN material to be used as a drain electrode 5 by utilizing aluminum, titanium, nickel and gold targets with the purity of 99.999%, and annealing for 30s at the high temperature of 850 ℃ to form ohmic contact.
And 6, etching the second step 10.
Making a mask on the n-drift layer 3, putting the sample after the above process into an RIE etching chamber, and using Cl2And BCl3And etching the opening area in the mask by using the gas to form a second-stage step 10, wherein the etching depth is 20 nm.
And 7, manufacturing a source electrode 7.
And putting the sample subjected to the process into a magnetron sputtering reaction chamber, depositing metal Ti/Au on the second step 10 by using titanium and gold targets with the purity of 99.999% as a source electrode 7 by adopting a self-alignment process, wherein the thickness of the source electrode 7 is equal to the depth of the second step 10.
And 8, depositing a gate dielectric layer 4.
Putting the sample after the above process into a PEALD reaction chamber, and depositing 10nm of Al on the n-drift layer 3 and the two source electrodes 7 at a high temperature of 300 DEG C2O3To fabricate the gate dielectric layer 4.
And 9, manufacturing a source contact hole.
And manufacturing a mask on the gate dielectric layer 4, placing the sample in an RIE system, and etching the gate dielectric layer 4 above the source electrode 7 to form a source electrode contact hole.
And 10, manufacturing a grid electrode 6 and thickening source metal.
And manufacturing a mask on the gate dielectric layer 4 again, then placing the sample wafer in a magnetron sputtering reaction chamber, depositing metal Ni/Au on the gate dielectric layer 4 by using nickel and gold targets with the purity of 99.999 percent as a gate, thickening the source electrode 7 at the same time, forming a metal thickening layer 8, and finishing the manufacture of the whole device.
In the description of the present invention, the terms "first" and "second" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implying any number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present invention, "a plurality" means two or more unless specifically defined otherwise.
In the description herein, references to the description of the term "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., mean that a particular feature, structure, material, or characteristic data point described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above are not necessarily intended to refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, various embodiments or examples described in this specification can be combined and combined by those skilled in the art.
The foregoing is a more detailed description of the invention in connection with specific preferred embodiments and it is not intended that the invention be limited to these specific details. For those skilled in the art to which the invention pertains, several simple deductions or substitutions can be made without departing from the spirit of the invention, and all shall be considered as belonging to the protection scope of the invention.
Claims (9)
1. An all-vertical field effect transistor based on a lateral Schottky source tunneling junction, comprising:
a substrate layer (1);
an n + buffer layer (2), the n + buffer layer (2) being disposed on the substrate layer (1);
the n-drift layer (3) is arranged on the n + buffer layer (2), two-stage steps are arranged at two ends of the n-drift layer (3), the two-stage steps comprise a first-stage step (9) and a second-stage step (10), the first-stage step (9) is located below the second-stage step (10), and the second-stage step (10) is close to the center of the n-drift layer (3);
the two source electrodes (7) are respectively arranged on the second-stage steps (10) at two ends of the n-drift layer (3), and the upper surface of each source electrode (7) is flush with the upper surface of the n-drift layer (3);
the gate dielectric layer (4), the gate dielectric layer (4) is arranged on the n-drift layer (3) and the two source electrodes (7);
the grid electrode (6) is arranged on the grid dielectric layer (4);
the gate structure comprises two metal thickening layers (8), wherein one metal thickening layer (8) is arranged on the source electrode (7) and the gate dielectric layer (4) which are positioned at one end, the other metal thickening layer (8) is arranged on the source electrode (7) and the gate dielectric layer (4) which are positioned at the other end, the gate (6) is arranged between the two metal thickening layers (8), and a gap is formed between the gate (6) and the metal thickening layer (8);
the drain electrode (5) is arranged on the lower surface of the substrate layer (1);
the substrate layer (1), the n + buffer layer (2) and the n-drift layer (3) are made of the same material.
2. The all-vertical field effect transistor according to claim 1, characterized in that the substrate layer (1), the n + buffer layer (2) and the n-drift layer (3) all use GaN, AlN, SiC, GaO, diamond or BN materials.
3. The all-vertical field effect transistor according to claim 2, characterized in that the n + buffer layer (2) has a doping concentration of 1018cm-3～1020cm-3The doping concentration of the n-drift layer (3) is 1015cm-3～1017cm-3。
4. The all-vertical field effect transistor according to claim 1, wherein the source (7) is made of Ti/Au, W/Au, Mo/Au, Ni/Au, Pt/Au or Pd/Au, and the drain (5) is made of Ti/Al/Ni/Au, Ti/Al/Ti/Au, Ti/Al/Mo/Au, Ta/Al/Ta, Ni/Au, Pt/Au, Pd/Au, W/Au or Ni/Au/Ni.
5. The all-vertical field effect transistor according to claim 1, characterized in that the gate (6) and the metal thickening layer (8) are of the same material.
6. The all-vertical field effect transistor according to claim 5, characterised in that the material of the gate (6) is Ni/Au, Pt/Au, Pd/Au, W/Au or Ni/Au/Ni.
7. The all-vertical field effect transistor according to claim 1, characterized in that an extension of a side of the gate (6) close to the source (7) intersects an inner portion of the source (7).
8. A method for preparing an all-vertical field effect transistor based on a lateral schottky source tunneling junction, which is used for preparing the all-vertical field effect transistor of any one of claims 1 to 7, and the preparation method comprises the following steps:
selecting a substrate layer (1);
growing an n + buffer layer (2) on the substrate layer (1);
growing an n-drift layer (3) on the n + buffer layer (2);
etching two first-stage steps (9) at two ends of the n-drift layer (3);
manufacturing a drain electrode (5) on the lower surface of the substrate layer (1);
two second steps (10) are etched at two ends of the n-drift layer (3), the first step (9) is positioned below the second step (10), and the second step (10) is close to the center of the n-drift layer (3);
manufacturing two source electrodes (7) on the two second-stage steps (10) at two ends of the n-drift layer (3), wherein the upper surfaces of the source electrodes (7) are flush with the upper surface of the n-drift layer (3);
growing a gate dielectric layer (4) on the n-drift layer (3) and the two source electrodes (7);
and manufacturing a grid electrode (6) on the grid dielectric layer (4), and simultaneously preparing two metal thickening layers (8) on the source electrode (7) and the grid dielectric layer (4) which are positioned at two ends of the n-drift layer (3) respectively.
9. Method for manufacturing an all-vertical field effect transistor according to claim 8, wherein the step of manufacturing a gate electrode (6) on the gate dielectric layer (4) and simultaneously manufacturing two metal thickening layers (8) on the source electrode (7) and the gate dielectric layer (4) on both ends of the n-drift layer (3) comprises:
manufacturing a mask on the gate dielectric layer (4), and etching a metal thickening area window on the gate dielectric layer (4) above the two source electrodes (7);
and depositing grid metal on the grid dielectric layer (4) and the metal thickening region window to form a grid (6) and two metal thickening layers (8).
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