CN101414634B - Heterojunction field effect transistor for groove insulated gate type multiple source field plate - Google Patents
Heterojunction field effect transistor for groove insulated gate type multiple source field plate Download PDFInfo
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- CN101414634B CN101414634B CN2008102325214A CN200810232521A CN101414634B CN 101414634 B CN101414634 B CN 101414634B CN 2008102325214 A CN2008102325214 A CN 2008102325214A CN 200810232521 A CN200810232521 A CN 200810232521A CN 101414634 B CN101414634 B CN 101414634B
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Abstract
The invention discloses a heterojunction field effect transistor of a groove-insulated gate type composite source field plate. The transistor comprises a substrate, a transition layer, a barrier layer, a source electrode, a drain electrode, an insulation medium layer, an insulated groove gate, a passivation layer, a source field plate and a protection layer from bottom to top; a groove is opened on the barrier layer, the insulated groove gate is arranged on the insulation medium layer at the upper part of the groove, the source field plate is arranged on the passivation layer, and the source electrode is electrically connected with the source field plate, wherein, n floating field plates are deposited on the passivation layer arranged between the source field plate and the drain field plate. The floating field plates have the same size and are mutually independent, and the spacing between two adjacent floating field plates increases based on the number of the floating field plates arranged along the direction from the source field plate to the drain electrode. The n floating field plates are in floating state and completed together with the source field plate on the passivation layer by one-time process. The heterojunction field effect transistor has the advantages of simple process, good reliability, strong stability, good frequency characteristic and high output power, and can be used for fabricating microwave power devices based on III-V group compound semiconductor heterojunction structure.
Description
Technical field
The invention belongs to microelectronics technology, relate to semiconductor device, particularly, can be used as the basic device of microwave, millimeter wave communication system and radar system based on the HFET of the groove insulated gate type multiple source field plate of III-V group iii v compound semiconductor material heterojunction.
Background technology
Known in the industry, the semi-conducting material of forming by III family element and V group element, it is the III-V group iii v compound semiconductor material, as semi-conducting materials such as gallium nitride (GaN) base, GaAs (GaAs) base, indium phosphide (InP) bases, their energy gap often differs greatly, so people utilize these III-V group iii v compound semiconductor materials to form various heterojunction structures usually.Because there is bigger difference in the energy gap of the III-V group iii v compound semiconductor material of heterojunction boundary both sides in heterojunction, makes these heterojunction structures have a common feature: near heterojunction boundary, produce a quantum potential well.For the heterojunction of being formed by the III-V group iii v compound semiconductor material, people are by mixing to material, perhaps utilize the characteristics such as polarity effect of material, can produce the two-dimensional electron gas of high concentration in the quantum potential well, this two-dimensional electron gas is made of a large amount of electric charge carriers.Be bound in the quantum potential well owing to this two-dimensional electron gas in addition, realized charge carrier and ionized impurity separating spatially, reduced the Coulomb force effect of ionized impurity, eliminated the influence of ionization scattering center, thereby improved the mobility of charge carrier rate greatly charge carrier.This high concentration two-dimensional electron gas and high carrier mobility make III-V group iii v compound semiconductor material heterojunction have good electrical characteristics.
The HFET that is made based on III-V group iii v compound semiconductor material heterojunction, inherited the advantage of III-V group iii v compound semiconductor material heterojunction, as high carrier concentration, high carrier mobility, high workload frequency, characteristic such as high-power and high temperature resistant, can be widely used in fields such as microwave, millimeter wave communication system and radar system, so such device just becomes the focus that numerous researchers study from being born.1980, people such as Takashi Mimura reported and have successfully developed first AlGaAs/GaAs HFET, referring to A new field-effecttransistor with selectively doped GaAs/n-Al
XGa
1-XAs heterostructures, Japanese Journal ofApplied Physics, Vol.19, No.5, pp.L225-L227, May 1980.1993, people such as Khan reported and have successfully developed first AlGaN/GaN heterojunction High Electron Mobility Transistor, also are a kind of HFET, referring to High electron mobility transistor based on a GaN-Al
XGa
1-XN heterojunction, AppliedPhysics Letters, Vol.63, No.9, pp.1214-1215, August 1993.Along with to the going deep into of device research, people constantly obtain new breakthrough to the research based on the HFET of III-V group iii v compound semiconductor material heterojunction.Yet the distribution of the electric field line during HFET work in the barrier layer depletion region is also inhomogeneous, often collects most electric field line near the gate edge of drain electrode one side, and therefore the electric field that should locate is quite high.High electric field herein can make gate leakage current increase, and causes device generation avalanche breakdown easily, makes its actual breakdown voltage less than normal, thereby causes the high-breakdown-voltage of such device and advantage such as high-power not to give full play to.In addition, the gate leakage currents increase of device can cause its reliability variation.
In order to improve the puncture voltage of HFET, give full play to the high advantage of its power output, the reliability of enhance device has the researcher to adopt field plate structure that it is improved simultaneously, and its structure is as shown in Figure 1.The basic principle of this structure is: utilize field plate to increase the area of depletion region, improved the drain-source voltage that depletion region can be born, thereby increased the puncture voltage of device; Simultaneously, utilize field plate that the distribution of electric field line in the barrier layer depletion region is modulated, reduced gate leakage currents.In HFET, adopt field plate structure, can be below field plate form new depletion region, i.e. high resistance area, the area of depletion region in the barrier layer between having increased grid and having drained, make depletion region can bear bigger drain-source voltage, thereby increased the puncture voltage of device.In HFET, adopt field plate structure, part can be collected in grid originally collects on the field plate near the electric field line at the edge of drain electrode one side, especially field plate is near the edge of drain electrode one side, the result occurs a peak electric field at grid respectively near the edge of drain electrode one side and the edge of the close drain electrode of field plate one side, thereby reduced the edge collected electric field line of grid near drain electrode one side, reduce the electric field at this place, reduced gate leakage currents.1998, people such as K.Asano have reported the HFET that adopts the grid field plate, higher device electric breakdown strength and power-performance have preferably been obtained, referring to Novel high powerAlGaAs-GaAs HFET with a field-modulating plate operated at 35V drain voltage, International Electron Devices Meeting Technical Digest, pp.59-62, December 1998.Yet, in the HFET that adopts the grid field plate, the additional capacitor that produces between grid field plate and the two-dimensional electron gas raceway groove can superpose in the grid leak feedback capacity of device into, make the grid leak feedback capacity increase, cause the power characteristic and the frequency characteristic decay of device, cause the unsteadiness of device to increase greatly simultaneously, device adopts the advantage of field plate structure not find full expression, so some researchers propose to adopt the source field plate structure to improve the performance of device.2004, people such as Y.-F.Wu have reported the High Electron Mobility Transistor that adopts the source field plate, it also is a kind of HFET that adopts the source field plate, eliminated the additional capacitor that field plate is introduced by the output tuning network, under higher frequency, obtained very high power gain, power output and power added efficiency, referring to High-gain microwave GaN HEMTs withsource-terminated field-plates, IEEE International Electron Devices Meeting Technical Digest, pp.1078-1079, December 2004.Because the ability of the puncture voltage of individual layer field plate structure raising HFET is very limited, therefore in order further to improve the puncture voltage and the power output of device, take into account the frequency characteristic of device simultaneously, some researchers have adopted the field plate structure of various complexity in HFET, and heap layer field plate structure is the most frequently used and the most effective a kind of structure at present, and this structure can increase the puncture voltage of device constantly by the number that increases heap layer field plate.2005, people such as Yuji Ando have reported the field-effect transistor that adopts grid field plate and the double-deck field plate of source field plate, reduced the grid leak feedback capacity of device effectively, very high puncture voltage, power output and linear gain have been obtained, referring to Novel AlGaN/GaN dual-field-plate FET with high gain, increased linearityand stability, IEEE International Electron Devices Meeting Technical Digest, pp.576-579, December 2005.But adopt the manufacture craft more complicated of the HFET of heap layer field plate structure, processing steps such as every increase one deck field plate all needs to add photoetching, depositing metal, deposit dielectric material, peels off, cleaning, and to make that the dielectric material of institute's deposit has suitable thickness below each layer field plate, must carry out loaded down with trivial details process debugging, therefore increase the difficulty that device is made greatly, reduced the rate of finished products of device.
Summary of the invention
The objective of the invention is to overcome the deficiency of above-mentioned prior art, provide that a kind of manufacturing process is simple, good reliability, stability is strong and the HFET of the groove insulated gate type multiple source field plate that puncture voltage is high, to realize high-output power and high finished product rate.
For achieving the above object; the heterojunction structure that device architecture provided by the invention adopts any III-V group iii v compound semiconductor material to constitute; this structure comprises from bottom to top: substrate; transition zone; barrier layer; source electrode; drain electrode; insulating medium layer; the insulation tank grid; passivation layer; source field plate and protective layer; have groove on the barrier layer; the insulation tank grid are positioned on the insulating medium layer on groove top; the source field plate be positioned at passivation layer above; source electrode and source field plate are electrically connected; wherein; be deposited with n floating barnyard plate on the passivation layer between source field plate and the drain electrode; n 〉=1, these floating barnyard plates and source field plate constitute the multiple source field plate structure, improve puncture voltage.
Described each floating barnyard plate size is identical, separate, and the number to drain directions increases progressively the spacing between the adjacent two floating barnyard plates successively from the source field plate according to floating barnyard plate arrangement.
Distance between described source field plate and its most contiguous floating barnyard plate is 0.06～2.8 μ m.
The depth D of described groove is less than the thickness of barrier layer, and the spacing at insulation tank grid and groove two ends is respectively R1 and R2, and R1 length is 0～1.5 μ m, and R2 length is 0～3 μ m, and R1≤R2.
For achieving the above object, the method for the HFET of making groove insulated gate type multiple source field plate provided by the invention comprises following process:
The transition zone of extension III-V group iii v compound semiconductor material is as the service area of device on substrate;
The barrier layer of deposit III-V group iii v compound semiconductor material on transition zone;
On barrier layer, make mask for the first time, and the two ends depositing metal on barrier layer, again at N
2Carry out rapid thermal annealing in the atmosphere, make source electrode and drain electrode respectively;
On barrier layer, make mask for the second time, utilize the barrier layer of this mask between source electrode and drain electrode to etch groove;
On the top of source electrode and drain electrode, and deposit insulating medium layer on the barrier layer between source electrode and the drain electrode;
On insulating medium layer, make mask, utilize this mask depositing metal on the insulating medium layer on groove top, make the insulation tank grid, the spacing at these insulation tank grid and groove two ends is respectively R1 and R2, R1 length is 0～1.5 μ m, and R2 length is 0～3 μ m, and R1≤R2;
The deposit passivation layer promptly uses the dielectric material to cover the zone of insulation tank grid periphery;
On passivation layer, make mask, utilize this mask depositing metal on the passivation layer between source electrode and the drain electrode, make thickness simultaneously and be the source field plate of 0.2～9 μ m and n floating barnyard plate, n 〉=1, and source field plate and source electrode be electrically connected;
The deposit protective layer promptly uses the dielectric material to cover the outer peripheral areas of source field plate and each floating barnyard plate.
Device of the present invention relatively has the following advantages with the HFET that adopts the conventional source field plate:
1. further improved the puncture voltage of device.
The present invention is owing to adopt floating barnyard plate structure, make device in running order when especially being in the operating state of OFF state, between source field plate and its most contiguous floating barnyard plate, and all there is the capacitive coupling effect each other at each floating barnyard plate, so the floating barnyard plate of electromotive force from the source field plate to the most close drain electrode one side raises gradually, thereby increased the depletion region in the barrier layer between insulation tank grid and the drain electrode greatly, it is the area of high resistance area, make this depletion region can bear bigger drain-source voltage, so improved the puncture voltage of device greatly.
2. further reduce gate leakage current, strengthened the reliability of device.
The present invention is owing to adopt floating barnyard plate structure, make the distribution of electric field line in the device barrier layer depletion region obtain stronger modulation, the insulation tank grid are near the edge of drain electrode one side in the device, between source field plate and its most contiguous floating barnyard plate, each floating barnyard plate each other and the edge near drain electrode one side of the floating barnyard plate of the most close drain electrode all can produce a peak electric field, and by the distance between adjustment source field plate and its most contiguous floating barnyard plate and each floating barnyard plate distance each other, can be so that above-mentioned each peak electric field equates and less than the breakdown electric field of III-V group iii v compound semiconductor material, thereby greatly reduced the edge collected electric field line of insulation tank grid near drain electrode one side, reduced the electric field at this place effectively, reduce gate leakage currents greatly, significantly strengthened the reliability of device.
3. further increase the saturated output current of device, can obtain stable high-output power.
The present invention is owing to adopted the groove insulated gate structure, further improve the biasing of device grids, increased the saturated output current of device, improved the linearity of device simultaneously, improved the large-signal and the small-signal microwave power performance of device, made device can obtain stable high-output power.
4. technology is simple, is easy to realize the rate of finished products height.
In the device architecture of the present invention since source field plate and each floating barnyard plate be positioned at on one deck passivation layer, and has only one deck, therefore only need a step process just can realize the making of source field plate and each floating barnyard plate simultaneously, the process complications problem of having avoided traditional heap layer field plate structure to be brought has improved the rate of finished products of device greatly.
Simulation result shows that the puncture voltage of device of the present invention is far longer than the puncture voltage of the HFET that adopts the conventional source field plate.
Further specify technology contents of the present invention and effect below in conjunction with drawings and Examples.
Description of drawings
Fig. 1 is the structure chart that adopts the HFET of traditional grid field plate;
Fig. 2 is the structure chart of the HFET of groove insulated gate type multiple source field plate of the present invention;
Fig. 3 is that the HFET of groove insulated gate type multiple source field plate of the present invention is made flow chart;
Fig. 4 is to electric field curve figure in the barrier layer of traditional devices and device simulation gained of the present invention;
Fig. 5 is the puncture curve chart to traditional devices and device simulation gained of the present invention.
Embodiment
With reference to Fig. 2; the HFET of groove insulated gate type multiple source field plate of the present invention is based on III-V compound semiconductor heterojunction structure, and its structure is from bottom to top: substrate 1, transition zone 2, barrier layer 3, insulating medium layer 7, passivation layer 9 and protective layer 12.Wherein, the two ends on the barrier layer 3 are respectively source electrode 4 and drain electrode 5, source electrode 4 and drain and be etched with groove 6 between 5, and the depth D of this groove is less than the thickness of barrier layer.Insulating medium layer 7 is positioned at the top of source electrode 4 and drain electrode 5, and on the barrier layer 3 between source electrode and the drain electrode.Insulation tank grid 8 be positioned at groove 6 tops insulating medium layer 7 above, and be respectively R1 and R2 with the spacing at groove 6 two ends, R1 length is 0～1.5 μ m, R2 length is 0～3 μ m, and R1≤R2.Passivation layer 9 is positioned at the outer peripheral areas of insulation tank grid 8.Make active field plate 10 and n floating barnyard plate 11 on passivation layer 9, n 〉=1 constitutes the multiple source field plate structure.These floating barnyard plates and source field plate are positioned at on one deck passivation layer, between first floating barnyard plate and the source field plate is 0.06 μ m～2.8 μ m apart from S1, spacing difference between the adjacent two floating barnyard plates, promptly increase gradually to drain directions from the source field plate, and the spacing between the adjacent two floating barnyard plates is all greater than S1 according to floating barnyard plate number.Each floating barnyard plate 11 big or small identical placed along the direction that is parallel to source field plate width, not with any electrode or Metal Contact, is in separate floating dummy status.The effective length L0 of source field plate is 0.25 μ m～6 μ m, and the length L 1 of each floating barnyard plate is 0.25 μ m～6 μ m, and the length of each floating barnyard plate is identical with the effective length of source field plate.Protective layer 12 is positioned at the outer peripheral areas of source field plate 10 and n floating barnyard plate 11.Source field plate 10 is electrically connected with source electrode 4.
The substrate 1 of above-mentioned device can be sapphire, carborundum, silicon or other epitaxial substrate material; Transition zone 2 is made up of the identical or different III-V group iii v compound semiconductor material of several layers, and its thickness is 1～5 μ m; Barrier layer 3 is made up of the identical or different III-V group iii v compound semiconductor material of several layers, and its thickness is 10～50nm; Insulating medium layer 7 can be SiO
2, SiN, Al
2O
3, Sc
2O
3, HfO
2, TiO
2Or other dielectric material, its thickness is 1～100nm; Passivation layer 9 can be SiO
2, SiN, Al
2O
3, Sc
2O
3, HfO
2, TiO
2Or other dielectric material, its thickness is 0.04～0.7 μ m; Protective layer 12 can be SiO
2, SiN, Al
2O
3, Sc
2O
3, HfO
2, TiO
2Or other dielectric material, its thickness is 0.25～9.2 μ m; Source field plate 10 and n floating barnyard plate 11, the combination of two-layer or three layers metal level is adopted in n 〉=1, and its thickness is 0.2～9 μ m.
With reference to Fig. 3, the process of HFET that the present invention makes groove insulated gate type multiple source field plate is as follows:
Select a substrate 1, this backing material can be sapphire, carborundum, silicon or other epitaxial substrate material, and epitaxial thickness is the service area of the III-V group iii v compound semiconductor material transition zone 2 of 1～5 μ m as device thereon, this buffer layer material is made up of the identical or different III-V group iii v compound semiconductor material of several layers, as only forming by the GaN material, or form by AlN and GaN two layers of material, or only form from bottom to top by the GaAs material.The method employing metal organic chemical vapor deposition technology of extension transition zone or molecular beam epitaxy technique or hydride gas-phase epitaxy technology or other can be used for the technology of extension transition zone.
Deposition thickness is the barrier layer 3 of 10～50nm on transition zone 2, and this barrier layer material is made up of the identical or different III-V group iii v compound semiconductor material of several layers, as only by Al
XGa
1-XThe N material is formed, or from bottom to top by Al
XGa
1-XN and GaN two layers of material are formed, or only by Al
XGa
1-XThe As material is formed, 0＜X＜1, and X represents the Al components contents.The method employing metal organic chemical vapor deposition technology of deposit barrier layer or molecular beam epitaxy technique or hydride gas-phase epitaxy technology or other can be used for the technology of deposit barrier layer.
Step 3 is made source electrode 4 and drain electrode 5 respectively, as Fig. 3 c on barrier layer 3.
On barrier layer 3, make mask for the first time, respectively at its two ends depositing metal, again at N
2Carry out rapid thermal annealing in the atmosphere, make source electrode 4 and drain electrode 5, wherein institute's metals deposited adopts the Ti/Al/Ni/Au combination, or to adopt other metallic combination, metal thickness be 0.01～0.04 μ m/0.03～0.16 μ m/0.02～0.12 μ m/0.06～0.15 μ m.The method of depositing metal adopts electron beam evaporation technique or sputtering technology or other can be used for the technology of depositing metal.
Make for the second time mask on barrier layer 3, etch groove 6 on the barrier layer between source electrode and the drain electrode, this depth of groove D is less than the thickness of barrier layer.The method employing reactive ion etching technology of etched recesses or inductively coupled plasma technology or reactive ion etching-inductively coupled plasma technology or other can be used for the technology of etched recesses.
Step 5, deposit insulating medium layer 7 is as Fig. 3 e.
On the top of source electrode 4 and drain electrode 5, and deposit insulating medium layer 7 on the barrier layer 3 between source electrode and the drain electrode, this dielectric layer material can adopt SiO
2, SiN, Al
2O
3, Sc
2O
3, HfO
2, TiO
2Or other dielectric material, its thickness is 1～100nm.The method employing chemical vapor deposition techniques of deposit insulating medium layer or evaporation technique or atomic layer deposition technology or sputtering technology or molecular beam epitaxy technique or other can be used for the technology of deposit insulating medium layer.
On insulating medium layer 7, make mask, and on the insulating medium layer on groove 6 tops depositing metal, make insulation tank grid 8, wherein institute's metals deposited adopts the Ni/Au metallic combination, or to adopt other metallic combination, metal thickness be 0.01～0.04 μ m/0.08～0.4 μ m, these insulation tank grid 8 are respectively R1 and R2 with the spacing at groove 6 two ends, R1 length is 0～1.5 μ m, and R2 length is 0～3 μ m, and R1≤R2.The method of depositing metal adopts electron beam evaporation technique or sputtering technology or other can be used for the technology of depositing metal.
Step 7, deposit passivation layer 9 is as Fig. 3 g.
At the outer peripheral areas deposit passivation layer 9 of insulation tank grid 8, this passivation material can adopt SiO
2, SiN, Al
2O
3, Sc
2O
3, HfO
2, TiO
2Or other dielectric material, its thickness is 0.04～0.7 μ m.The method employing chemical vapor deposition techniques of deposit passivation layer or evaporation technique or atomic layer deposition technology or sputtering technology or molecular beam epitaxy technique or other can be used for the technology of deposit passivation layer.
On passivation layer 9, make mask, this mask is to be 0.06 μ m～2.8 μ m according to the distance between source field plate 10 and its most contiguous floating barnyard plate, and the spacings between the adjacent two floating barnyard plates are arranged the position relation setting that the number to drain directions increases progressively successively from the source field plate according to floating barnyard plate.Utilize this mask deposited metal thickness on passivation layer to be the source field plate 10 of 0.2～9 μ m and n floating barnyard plate 11, n 〉=1.Combination two-layer or the three-layer metal layer is all adopted in the deposit of this source field plate and each floating barnyard plate, and lower metal thickness is less than the upper strata metal thickness.Ti/Au or Ni/Au or Pt/Au are adopted in combination for double layer of metal, and thickness is 0.05～1.6 μ m/0.15～7.4 μ m; Ti/Mo/Au or Ti/Ni/Au or Ti/Pt/Au are adopted in combination for three-layer metal, and thickness is 0.04～0.5 μ m/0.07～1.5 μ m/0.09～7 μ m.The effective length L0 of source field plate is 0.25～6 μ m, and the length L 1 of each floating barnyard plate is 0.25～6 μ m, and the length of each floating barnyard plate is identical with the effective length of source field plate.The method of depositing metal adopts electron beam evaporation technique or sputtering technology or other can be used for the technology of depositing metal.
After finishing the making of source field plate and n floating barnyard plate, source field plate 10 and source electrode 4 are electrically connected.
Step 9, deposit protective layer 12 is as Fig. 3 i.
At the outer peripheral areas deposit protective layer 12 of source field plate 10 and n floating barnyard plate 11, wherein protective layer material can adopt SiO
2, SiN, Al
2O
3, Sc
2O
3, HfO
2, TiO
2Or other dielectric material, its thickness is 0.25～9.2 μ m.The method employing chemical vapor deposition techniques of deposit protective layer or evaporation technique or atomic layer deposition technology or sputtering technology or molecular beam epitaxy technique or other can be used for the technology of deposit protective layer.
According to above-described device architecture and manufacture method, the present invention provides following six kinds of embodiment, but is not limited to these embodiment.
Embodiment one
The making substrate is a sapphire, and insulating medium layer is SiO
2, passivation layer is SiN, protective layer is SiN, and the HFET of the multiple source field plate that source field plate and each floating barnyard plate are the Ti/Au metallic combination, its process is:
1. using metal organic chemical vapor deposition technology epitaxial thickness on Sapphire Substrate 1 is the not doping transition zone 2 of 1 μ m, and this transition zone is that the AlN material of 26nm and GaN material that thickness is 0.974 μ m constitute by thickness from bottom to top.The process conditions that the AlN of extension lower floor material adopts are: temperature is 575 ℃, and pressure is 82Torr, and hydrogen flowing quantity is 4400sccm, and ammonia flow is 4400sccm, and the aluminium source flux is 26 μ mol/min; The process conditions that extension upper strata GaN material adopts are: temperature is 1000 ℃, and pressure is 82Torr, and hydrogen flowing quantity is 4400sccm, and ammonia flow is 4400sccm, and the gallium source flux is 130 μ mol/min.
2. use metal organic chemical vapor deposition technology deposition thickness on GaN transition zone 2 to be the not doping potential barrier layer 3 of 50nm, this barrier layer is that 47nm, al composition are 0.15 Al by thickness from bottom to top
0.15Ga
0.85N material and thickness are that the GaN material of 3nm constitutes.The Al of deposit lower floor
0.15Ga
0.85The process conditions that the N material adopts are: temperature is 1030 ℃, and pressure is 82Torr, and hydrogen flowing quantity is 4400sccm, and ammonia flow is 4400sccm, and the gallium source flux is 11 μ mol/min, and the aluminium source flux is 2 μ mol/min; The process conditions that deposit upper strata GaN material adopts are: temperature is 1030 ℃, and pressure is 82Torr, and hydrogen flowing quantity is 4400sccm, and ammonia flow is 4400sccm, and the gallium source flux is 7 μ mol/min.
3. on barrier layer 3, make mask, and use electron beam evaporation technique at its two ends depositing metal, again at N
2Carry out rapid thermal annealing in the atmosphere, make source electrode 4 and drain electrode 5, wherein institute's metals deposited is the Ti/Al/Ni/Au metallic combination, and metal layer thickness is 0.01 μ m/0.03 μ m/0.02 μ m/0.06 μ m.The process conditions that depositing metal adopts are: vacuum degree is less than 1.8 * 10
-3Pa, power bracket is 200～1000W, evaporation rate less than
The process conditions that rapid thermal annealing adopts are: temperature is 840 ℃, and the time is 50s.
4. make mask on barrier layer 3, use reactive ion etching technology to etch groove 6 on the barrier layer between source electrode and the drain electrode, this depth of groove D is 30nm.The process conditions that etched recesses adopts are: reacting gas Cl
2Flow be 5sccm, pressure is 10mT, power is 100W.
5. use electron beam evaporation technique respectively on the top of source electrode 4 and drain electrode 5, and deposit SiO on the barrier layer 3 between source electrode and the drain electrode
2As insulating medium layer 7, this dielectric layer thickness is 1nm.The process conditions that the deposit insulating medium layer adopts are: vacuum degree is less than 1.2 * 10
-3Pa, power be less than 50W, evaporation rate less than
6. at SiO
2Make mask on the insulating medium layer 7, and use electron beam evaporation technique depositing metal on the insulating medium layer on groove 6 tops, make insulation tank grid 8, wherein institute's metals deposited adopts the Ni/Au metallic combination, metal thickness is 0.01 μ m/0.08 μ m, these insulation tank grid 8 are respectively R1 and R2 with the spacing at groove 6 two ends, and the length of R1 and R2 is 0.0 μ m.The process conditions that depositing metal adopts are: vacuum degree is less than 1.2 * 10
-3Pa, power bracket is 200～700W, evaporation rate less than
7. as passivation layer 9, this Tunization layer thickness is 0.04 μ m to use plasma enhanced CVD technology at the regional deposit SiN of insulation tank grid 8 peripheries.The process conditions that the deposit passivation layer adopts are: gas is NH
3, N
2And SiH
4, gas flow is respectively 2.5sccm, 900sccm and 200sccm, and temperature, RF power and pressure are respectively 300 ℃, 25W and 900mT.
8. on SiN passivation layer 9, make mask, using electron beam evaporation technique deposition thickness on the passivation layer between source electrode and the drain electrode is the Ti/Au metallic combination of 0.05 μ m/0.15 μ m, to make source field plate 10 and a floating barnyard plate 11, the length L 1 of the effective length L0 of this source field plate and floating barnyard plate is 0.25 μ m, and between source field plate and the floating barnyard plate is 0.06 μ m apart from S1.The process conditions that depositing metal adopts are: vacuum degree is less than 1.8 * 10
-3Pa, power bracket is 200～700W, evaporation rate less than
Source field plate 10 and source electrode 4 are electrically connected.
9. using the plasma enhanced CVD technology is that the SiN of 0.22 μ m is as protective layer 12 at the outer peripheral areas deposition thickness of source field plate 10 and floating barnyard plate 11 respectively.The process conditions that the deposit protective layer adopts are: gas is NH
3, N
2And SiH
4, gas flow is respectively 2.5sccm, 900sccm and 200sccm, and temperature, RF power and pressure are respectively 300 ℃, 25W and 900mT.
Embodiment two
The making substrate is a carborundum, and insulating medium layer is SiN, and passivation layer is SiO
2, protective layer is SiO
2, the HFET of the multiple source field plate that source field plate and each floating barnyard plate are the Ni/Au metallic combination, its process is:
1. using metal organic chemical vapor deposition technology epitaxial thickness on silicon carbide substrates 1 is the not doping transition zone 2 of 2.6 μ m, and this transition zone is that the AlN material of 70nm and GaN material that thickness is 2.53 μ m constitute by thickness from bottom to top.The process conditions that the AlN of extension lower floor material adopts are: temperature is 1040 ℃, and pressure is 85Torr, and hydrogen flowing quantity is 5000sccm, and ammonia flow is 5000sccm, and the aluminium source flux is 16 μ mol/min; The process conditions that extension upper strata GaN material adopts are: temperature is 1040 ℃, and pressure is 85Torr, and hydrogen flowing quantity is 5000sccm, and ammonia flow is 5000sccm, and the gallium source flux is 180 μ mol/min.
2. use metal organic chemical vapor deposition technology deposition thickness on GaN transition zone 2 to be 28nm, and al composition is 0.3 not doped with Al
0.3Ga
0.7N barrier layer 3.The process conditions that adopt are: temperature is 1020 ℃, and pressure is 85Torr, and hydrogen flowing quantity is 5000sccm, and ammonia flow is 5000sccm, and the gallium source flux is 11 μ mol/min, and the aluminium source flux is 5 μ mol/min.
3. at Al
0.3Ga
0.7Make mask on the N barrier layer 3, and use electron beam evaporation technique at its two ends depositing metal, again at N
2Carry out rapid thermal annealing in the atmosphere, make source electrode 4 and drain electrode 5, wherein institute's metals deposited is the Ti/Al/Ni/Au metallic combination, and metal layer thickness is 0.02 μ m/0.12 μ m/0.07 μ m/0.07 μ m.The process conditions that depositing metal adopts are: vacuum degree is less than 1.8 * 10
-3Pa, power bracket is 200～1000W, evaporation rate less than
The process conditions that rapid thermal annealing adopts are: temperature is 850 ℃, and the time is 40s.
4. at Al
0.3Ga
0.7Make mask on the N barrier layer 3, use reactive ion etching technology to etch groove 6 on the barrier layer between source electrode and the drain electrode, this depth of groove D is 10nm.The process conditions that etched recesses adopts are: reacting gas Cl
2Flow be 5sccm, pressure is 10mT, power is 100W.
5. use the plasma enhanced CVD technology respectively on the top of source electrode 4 and drain electrode 5, and deposit SiN is as insulating medium layer 7 on the barrier layer 3 between source electrode and the drain electrode, this dielectric layer thickness is 10nm.The process conditions that the deposit insulating medium layer adopts are: gas is NH
3, N
2And SiH
4, gas flow is respectively 2.5sccm, 900sccm and 200sccm, and temperature, RF power and pressure are respectively 300 ℃, 25W and 900mT.
6. on SiN insulating medium layer 7, make mask, and use electron beam evaporation technique depositing metal on the insulating medium layer on groove 6 tops, make insulation tank grid 8, wherein institute's metals deposited adopts the Ni/Au metallic combination, metal thickness is 0.02 μ m/0.3 μ m, these insulation tank grid (8) are respectively R1 and R2 with the spacing at groove (6) two ends, and R1 length is 0.5 μ m, and R2 length is 1.5 μ m.The process conditions that depositing metal adopts are: vacuum degree is less than 1.2 * 10
-3Pa, power bracket is 200～700W, evaporation rate less than
7. use the regional deposit SiO of electron beam evaporation technique in insulation tank grid periphery
2As passivation layer 9, this passivation layer thickness is 0.3 μ m.The process conditions that the deposit passivation layer adopts are: vacuum degree is less than 1.2 * 10
-3Pa, power be less than 50W, evaporation rate less than
8. at SiO
2Make mask on the passivation layer 9, using electron beam evaporation technique deposition thickness on the passivation layer between source electrode and the drain electrode is the Ni/Au metallic combination of 0.5 μ m/1 μ m, to make source field plate 10 and two floating barnyard plates 11, the length L 1 of the effective length L0 of this source field plate and each floating barnyard plate is 1 μ m, between source field plate and first the floating barnyard plate is 0.46 μ m apart from S1, and between source field plate and second the floating barnyard plate is 2.4 μ m apart from S2.The process conditions that depositing metal adopts are: vacuum degree is less than 1.8 * 10
-3Pa, power bracket is 200～700W, evaporation rate less than
Source field plate 10 and source electrode 4 are electrically connected.
9. using the plasma enhanced CVD technology is the SiO of 1.7 μ m at the outer peripheral areas deposition thickness of source field plate 10 and two floating barnyard plates 11 respectively
2As protective layer 12.The process conditions that the deposit protective layer adopts are: gas is N
2O and SiH
4, gas flow is respectively 800sccm and 150sccm, and temperature, RF power and pressure are respectively 250 ℃, 25W and 1000mT.
Embodiment three
The making substrate is a silicon, and insulating medium layer is Al
2O
3, passivation layer is SiN, protective layer is SiN, and the HFET of the multiple source field plate that source field plate and each floating barnyard plate are the Pt/Au metallic combination, its process is:
1. using metal organic chemical vapor deposition technology epitaxial thickness on silicon substrate 1 is the not doping transition zone 2 of 5 μ m, and this transition zone is that the AlN material of 135nm and GaN material that thickness is 4.865 μ m constitute by thickness from bottom to top.The process conditions that the AlN of extension lower floor material adopts are: temperature is 880 ℃, and pressure is 90Torr, and hydrogen flowing quantity is 5100sccm, and ammonia flow is 5100sccm, and the aluminium source flux is 41 μ mol/min; The process conditions that extension upper strata GaN material adopts are: temperature is 1070 ℃, and pressure is 90Torr, and hydrogen flowing quantity is 5100sccm, and ammonia flow is 5100sccm, and the gallium source flux is 180 μ mol/min.
2. use metal organic chemical vapor deposition technology deposition thickness on GaN transition zone 2 to be 10nm, and al composition is 0.5 not doped with Al
0.5Ga
0.5N barrier layer 3.The process conditions that adopt are: temperature is 1020 ℃, and pressure is 90Torr, and hydrogen flowing quantity is 5100sccm, and ammonia flow is 5100sccm, and the gallium source flux is 10 μ mol/min, and the aluminium source flux is 10 μ mol/min.
3. at Al
0.5Ga
0.5Make mask on the N barrier layer 3, and use electron beam evaporation technique at its two ends depositing metal, again at N
2Carry out rapid thermal annealing in the atmosphere, make source electrode 4 and drain electrode 5, wherein institute's metals deposited is the Ti/Al/Ni/Au metallic combination, and metal layer thickness is 0.04 μ m/0.16 μ m/0.12 μ m/0.15 μ m.The process conditions that depositing metal adopts are: vacuum degree is less than 1.8 * 10
-3Pa, power bracket is 200～1000W, evaporation rate less than
The process conditions that rapid thermal annealing adopts are: temperature is 870 ℃, and the time is 30s.
4. at Al
0.5Ga
0.5Make mask on the N barrier layer 3, use reactive ion etching technology to etch groove 6 on the barrier layer between source electrode and the drain electrode, this depth of groove D is 2nm.The process conditions that etched recesses adopts are: reacting gas Cl
2Flow be 5sccm, pressure is 10mT, power is 100W.
5. use the atomic layer deposition technology respectively on the top of source electrode 4 and drain electrode 5, and deposit Al on the barrier layer 3 between source electrode and the drain electrode
2O
3As insulating medium layer 7, this dielectric layer thickness is 100nm.The process conditions that the deposit insulating medium layer adopts are: with TMA and H
2O is a reaction source, and carrier gas is N
2, carrier gas flux is 200sccm, and underlayer temperature is 300 ℃, and air pressure is 700Pa.
6. at Al
2O
3Make mask on the insulating medium layer 7, and use electron beam evaporation technique depositing metal on the insulating medium layer on groove 6 tops, make insulation tank grid 8, wherein institute's metals deposited adopts the Ni/Au metallic combination, metal thickness is 0.04 μ m/0.4 μ m, these insulation tank grid 8 are respectively R1 and R2 with the spacing at groove 6 two ends, and R1 length is 1.5 μ m, and R2 length is 3.0 μ m.The process conditions that depositing metal adopts are: vacuum degree is less than 1.2 * 10
-3Pa, power bracket is 200～700W, evaporation rate less than
7. as passivation layer 9, this passivation layer thickness is 0.7 μ m to use plasma enhanced CVD technology at the regional deposit SiN of insulation tank grid periphery.The process conditions that the deposit passivation layer adopts are: gas is NH
3, N
2And SiH
4, gas flow is respectively 2.5sccm, 900sccm and 200sccm, and temperature, RF power and pressure are respectively 300 ℃, 25W and 900mT.
8. on SiN passivation layer 9, make mask, using electron beam evaporation technique deposition thickness on the passivation layer between source electrode and the drain electrode is the Pt/Au metallic combination of 1.6 μ m/7.4 μ m, to make source field plate 10 and three floating barnyard plates 11, the length L 1 of the effective length L0 of this source field plate and each floating barnyard plate is 6 μ m, between source field plate and first the floating barnyard plate is 2.8 μ m apart from S1, between source field plate and second the floating barnyard plate is 14.5 μ m apart from S2, and between source field plate and the 3rd the floating barnyard plate is 32 μ m apart from S3.The process conditions that depositing metal adopts are: vacuum degree is less than 1.8 * 10
-3Pa, power bracket is 200～1000W, evaporation rate less than
Source field plate 10 and source electrode 4 are electrically connected.
9. using the plasma enhanced CVD technology is that the SiN of 9.2 μ m is as protective layer 12 at the outer peripheral areas deposition thickness of source field plate 10 and three floating barnyard plates 11 respectively.The process conditions that the deposit protective layer adopts are: gas is NH
3, N
2And SiH
4, gas flow is respectively 2.5sccm, 900sccm and 200sccm, and temperature, RF power and pressure are respectively 300 ℃, 25W and 900mT.
Embodiment four
The making substrate is a sapphire, and insulating medium layer is SiO
2, passivation layer is SiN, protective layer is Al
2O
3, the HFET of the multiple source field plate that source field plate and each floating barnyard plate are the Ti/Mo/Au metallic combination, its process is:
1. the process 1 with embodiment one is identical;
2. the process 2 with embodiment one is identical;
3. the process 3 with embodiment one is identical;
4. the process 4 with embodiment one is identical;
5. the process 5 with embodiment one is identical;
6. the process 6 with embodiment one is identical;
7. the process 7 with embodiment one is identical;
8. on SiN passivation layer 9, make mask, using electron beam evaporation technique deposition thickness on the passivation layer between source electrode and the drain electrode is the Ti/Mo/Au metallic combination of 0.04 μ m/0.07 μ m/0.09 μ m, to make source field plate 10 and four floating barnyard plates 11, the length L 1 of the effective length L0 of this source field plate and each floating barnyard plate is 0.25 μ m, between source field plate and first the floating barnyard plate is 0.06 μ m apart from S1, between source field plate and second the floating barnyard plate is 0.45 μ m apart from S2, between source field plate and the 3rd the floating barnyard plate is 0.96 μ m apart from S3, and between source field plate and the 4th the floating barnyard plate is 1.7 μ m apart from S4.The process conditions that depositing metal adopts are: vacuum degree is less than 1.8 * 10
-3Pa, power bracket is 200～1800W, evaporation rate less than
Source field plate 10 and source electrode 4 are electrically connected.
9. using the atomic layer deposition technology is the Al of 0.22 μ m at the outer peripheral areas deposition thickness of source field plate 10 and four floating barnyard plates 11 respectively
2O
3As protective layer 12.The process conditions that the deposit protective layer adopts are: with TMA and H
2O is a reaction source, and carrier gas is N
2, carrier gas flux is 200sccm, and underlayer temperature is 300 ℃, and air pressure is 700Pa.
Embodiment five
The making substrate is a carborundum, and insulating medium layer is SiN, and passivation layer is SiO
2, protective layer is SiN, the HFET of the multiple source field plate that source field plate and each floating barnyard plate are the Ti/Ni/Au metallic combination, and its process is:
1. the process 1 with embodiment two is identical;
2. the process 2 with embodiment two is identical;
3. the process 3 with embodiment two is identical;
4. the process 4 with embodiment two is identical;
5. the process 5 with embodiment two is identical;
6. the process 6 with embodiment two is identical;
7. the process 7 with embodiment two is identical;
8. at SiO
2Make mask on the passivation layer 9, using electron beam evaporation technique deposition thickness on the passivation layer between source electrode and the drain electrode is the Ti/Ni/Au metallic combination of 0.3 μ m/0.9 μ m/2.8 μ m, to make source field plate 10 and two floating barnyard plates 11, the length L 1 of the effective length L0 of this source field plate and each floating barnyard plate is 0.8 μ m, between the source field plate and the first floating barnyard plate is 1.2 μ m apart from S1, and between the source field plate and the second floating barnyard plate is 4.5 μ m apart from S2.The process conditions that depositing metal adopts are: vacuum degree is less than 1.8 * 10
-3Pa, power bracket is 200～700W, evaporation rate less than
Source field plate 10 and source electrode 4 are electrically connected.
9. using the plasma enhanced CVD technology is that the SiN of 4.5 μ m is as protective layer 12 at the outer peripheral areas deposition thickness of source field plate 10 and two floating barnyard plates 11 respectively.The process conditions that the deposit protective layer adopts are: gas is NH
3, N
2And SiH
4, gas flow is respectively 2.5sccm, 900sccm and 200sccm, and temperature, RF power and pressure are respectively 300 ℃, 25W and 900mT.
Embodiment six
The making substrate is a silicon, and insulating medium layer is Al
2O
3, passivation layer is SiN, protective layer is SiO
2, the HFET of the multiple source field plate that source field plate and each floating barnyard plate are the Ti/Pt/Au metallic combination, its process is:
1. the process 1 with embodiment three is identical;
2. the process 2 with embodiment three is identical;
3 is identical with the process 3 of embodiment three;
4. the process 4 with embodiment three is identical;
5. the process 5 with embodiment three is identical;
6. the process 6 with embodiment three is identical;
7. the process 7 with embodiment three is identical;
8. on SiN passivation layer 9, make mask, using electron beam evaporation technique deposition thickness on the passivation layer between source electrode and the drain electrode is the Ti/Pt/Au metallic combination of 0.5 μ m/1.5 μ m/7 μ m, to make source field plate 10 and three floating barnyard plates 11, the length L 1 of the effective length L0 of this source field plate and each floating barnyard plate is 6 μ m, between source field plate and first the floating barnyard plate is 2.8 μ m apart from S1, between source field plate and second the floating barnyard plate is 15 μ m apart from S2, and between source field plate and the 3rd the floating barnyard plate is 32 μ m apart from S3.The process conditions that depositing metal adopts are: vacuum degree is less than 1.8 * 10
-3Pa, power bracket is 200～1000W, evaporation rate less than
Source field plate 10 and source electrode 4 are electrically connected.
9. using the plasma enhanced CVD technology is the SiO of 9.2 μ m at the outer peripheral areas deposition thickness of source field plate 10 and three floating barnyard plates 11 respectively
2As protective layer 12.The process conditions that the deposit protective layer adopts are: gas is N
2O and SiH
4, gas flow is respectively 800sccm and 150sccm, and temperature, RF power and pressure are respectively 250 ℃, 25W and 1000mT.
Effect of the present invention can further specify by Fig. 4 and Fig. 5.
Fig. 4 has provided employing Al
0.32Ga
0.68During the N/GaN heterojunction structure, adopt HFET and the present invention of conventional source field plate to adopt the device of two floating barnyard plates at Al
0.32Ga
0.68Electric field analogous diagram in the N barrier layer, by this figure as can be seen, adopt the electric field curve of HFET in barrier layer of conventional source field plate only to form 2 approximately equalised peak electric field, the area that its electric field curve covered is very little, and the electric field curve of device of the present invention in barrier layer formed 4 approximately equalised peak electric field, make the area that electric field curve covered of device of the present invention increase greatly, because the area approximation that electric field curve covered in barrier layer equals the puncture voltage of device, illustrate that the puncture voltage of device of the present invention is far longer than the puncture voltage of the HFET that adopts the conventional source field plate.
Fig. 5 has provided employing Al
0.32Ga
0.68During the N/GaN heterojunction structure, adopt the HFET of conventional source field plate and the puncture analogous diagram of the device that the present invention adopts two floating barnyard plates, by this figure as can be seen, puncture in the puncture curve of the HFET of employing conventional source field plate, be that the drain-source voltage of drain current when increasing sharply is greatly about 610V, and the drain-source voltage when take place puncturing in the puncture curve of device of the present invention is greatly about 1550V, the puncture voltage of proof device of the present invention is far longer than the puncture voltage of the HFET that adopts the conventional source field plate, and the conclusion of this Fig. 5 is consistent with the conclusion among Fig. 4.
For those skilled in the art; after having understood content of the present invention and principle; can be under the situation that does not deviate from the principle and scope of the present invention; the method according to this invention is carried out various corrections and the change on form and the details, but these are based on correction of the present invention with change still within claim protection range of the present invention.
Claims (6)
1. the HFET of a groove insulated gate type multiple source field plate; comprise substrate (1); transition zone (2); barrier layer (3); source electrode (4); drain electrode (5); insulating medium layer (7); insulation tank grid (8); passivation layer (9); source field plate (10) and protective layer (12); have groove (6) on the barrier layer (3); insulation tank grid (8) are positioned on the insulating medium layer (7) on groove (6) top; source field plate (10) be positioned at passivation layer (9) above; source electrode (4) is electrically connected with source field plate (10); it is characterized in that; be deposited with n floating barnyard plate (11) on the passivation layer between source field plate (10) and the drain electrode; n 〉=1; each floating barnyard plate size is identical; separate; number to drain directions increases progressively spacing between the adjacent two floating barnyard plates successively from the source field plate according to floating barnyard plate arrangement; these floating barnyard plates and source field plate constitute the multiple source field plate structure, improve puncture voltage.
2. the HFET of multiple source field plate according to claim 1, it is characterized in that the thickness of the depth D of groove (6) less than barrier layer, insulation tank grid (8) are respectively R1 and R2 with the spacing at groove (6) two ends, R1 length is 0～1.5 μ m, R2 length is 0～3 μ m, and R1≤R2.
3. method of making the HFET of groove insulated gate type multiple source field plate comprises following process:
Go up the service area of the transition zone (2) of extension III-V group iii v compound semiconductor material at substrate (1) as device;
Go up the barrier layer (3) of deposit III-V group iii v compound semiconductor material at transition zone (2);
Go up the first time at barrier layer (3) and make mask, and the two ends depositing metal on barrier layer (3), again at N
2Carry out rapid thermal annealing in the atmosphere, make source electrode (4) and drain electrode (5) respectively;
Go up the second time at barrier layer (3) and make mask, utilize the barrier layer of this mask between source electrode and drain electrode to etch groove (6);
On the top of source electrode (4) and drain electrode (5), and the barrier layer (3) between source electrode and the drain electrode is gone up deposit insulating medium layer (7);
Go up the making mask at insulating medium layer (7), utilize this mask depositing metal on the insulating medium layer on groove (6) top, make insulation tank grid (8), the spacing at these insulation tank grid and groove (6) two ends is respectively R1 and R2, R1 length is 0～1.5 μ m, R2 length is 0～3 μ m, and R1≤R2;
Deposit passivation layer (9) promptly uses the dielectric material to cover the zone of insulation tank grid periphery;
Go up the making mask at passivation layer (9), utilize this mask depositing metal on the passivation layer between source electrode and the drain electrode, make source field plate (10) and n floating barnyard plate (11) that thickness is 0.2～9 μ m simultaneously, n 〉=1, each floating barnyard plate size is identical, separate, the number to drain directions increases progressively the spacing between the adjacent two floating barnyard plates successively from the source field plate according to floating barnyard plate arrangement, and source field plate (10) and source electrode (4) are electrically connected;
Deposit protective layer (12) promptly uses the dielectric material to cover the outer peripheral areas of source field plate (10) and each floating barnyard plate (11).
4. method according to claim 3, it is characterized in that depositing metal is made source field plate and each the floating barnyard plate that thickness is 0.2～9 μ m on the passivation layer between source electrode and the drain electrode, adopt the combination of two-layer or three-layer metal layer, and lower metal thickness is less than the upper strata metal thickness.
5. method according to claim 4 is characterized in that three-layer metal combination employing Ti/Mo/Au or Ti/Ni/Au or Ti/Pt/Au, and its thickness is 0.04～0.5 μ m/0.07～1.5 μ m/0.09～7 μ m.
6. method according to claim 4 is characterized in that double layer of metal combination employing Ti/Au or Ni/Au or Pt/Au, and its thickness is 0.05～1.6 μ m/0.15～7.4 μ m.
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| CN105355659A (en) * | 2015-11-06 | 2016-02-24 | 西安电子科技大学 | Trench-gate AlGaN/GaN HEMT device structure and manufacturing method |
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| US9722063B1 (en) | 2016-04-11 | 2017-08-01 | Power Integrations, Inc. | Protective insulator for HFET devices |
| CN107146812B (en) * | 2017-03-29 | 2019-12-03 | 西安电子科技大学 | Enhanced grid field plate GaN base current apertures hetero junction field effect device and preparation method thereof |
| CN110120346B (en) * | 2018-02-06 | 2022-04-22 | 中芯国际集成电路制造(上海)有限公司 | LDMOS transistor and manufacturing method thereof |
| CN110676316B (en) * | 2019-09-20 | 2023-04-11 | 中国电子科技集团公司第十三研究所 | Enhancement mode field effect transistor |
| CN113707713B (en) * | 2021-08-31 | 2023-06-30 | 西安电子科技大学 | Multi-stage petal-shaped body region metal oxide semiconductor power device and manufacturing method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| EP0360036A2 (en) * | 1988-09-20 | 1990-03-28 | Siemens Aktiengesellschaft | Planar pn-junction having a high withstand voltage |
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| EP0360036A2 (en) * | 1988-09-20 | 1990-03-28 | Siemens Aktiengesellschaft | Planar pn-junction having a high withstand voltage |
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| CN105355659A (en) * | 2015-11-06 | 2016-02-24 | 西安电子科技大学 | Trench-gate AlGaN/GaN HEMT device structure and manufacturing method |
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