CN111834439A - High-electron-mobility transistor, preparation method thereof and electronic device - Google Patents

High-electron-mobility transistor, preparation method thereof and electronic device Download PDF

Info

Publication number
CN111834439A
CN111834439A CN201910323441.8A CN201910323441A CN111834439A CN 111834439 A CN111834439 A CN 111834439A CN 201910323441 A CN201910323441 A CN 201910323441A CN 111834439 A CN111834439 A CN 111834439A
Authority
CN
China
Prior art keywords
algan
barrier layer
gate
layer
forming
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201910323441.8A
Other languages
Chinese (zh)
Inventor
陈道坤
史波
曾丹
陈兆同
何昌
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Gree Electric Appliances Inc of Zhuhai
Original Assignee
Gree Electric Appliances Inc of Zhuhai
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Gree Electric Appliances Inc of Zhuhai filed Critical Gree Electric Appliances Inc of Zhuhai
Priority to CN201910323441.8A priority Critical patent/CN111834439A/en
Publication of CN111834439A publication Critical patent/CN111834439A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/778Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7786Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
    • H01L29/7787Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT with wide bandgap charge-carrier supplying layer, e.g. direct single heterostructure MODFET
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66446Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
    • H01L29/66462Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Junction Field-Effect Transistors (AREA)

Abstract

The invention relates to the technical field of electrons, and discloses a high electron mobility transistor, a preparation method thereof and an electronic device, wherein the high electron mobility transistor comprises: the GaN-based light-emitting diode comprises a substrate, a buffer layer and a GaN channel layer which are sequentially arranged, wherein the GaN channel layer comprises a gate region and a non-gate region which is positioned around the gate region; the AlGaN gate lower barrier layer is formed on one side, away from the buffer layer, of the gate region of the GaN channel layer; the gate electrode is formed on the side face, away from the GaN channel layer, of the AlGaN gate lower barrier layer; the AlGaN barrier layer is formed in a non-gate region of the GaN channel layer, and a source electrode and a drain electrode are formed on the surface of the AlGaN barrier layer; the aluminum content of the AlGaN gate lower barrier layer is lower than that of the AlGaN barrier layer, and/or the thickness of the AlGaN gate lower barrier layer is smaller than that of the AlGaN barrier layer. The high electron mobility transistor can be used for relieving the technical problems that the threshold voltage is low and the transistor is easy to be turned on by mistake.

Description

High-electron-mobility transistor, preparation method thereof and electronic device
Technical Field
The present invention relates to the field of electronic technologies, and in particular, to a high electron mobility transistor, a method for manufacturing the same, and an electronic device.
Background
GaN (gallium nitride) is one of the third generation wide bandgap semiconductors, and has excellent physical properties such as a wide bandgap and a high breakdown field. Due to the spontaneous polarization and piezoelectric polarization characteristics of the GaN-based semiconductor, the AlGaN (gallium aluminum nitride)/GaN heterojunction interface can generate high confinement and high-concentration 2DEG (two-dimensional electron gas) under the condition of unintentional doping, and the two-dimensional electron gas has the characteristics of high electron mobility and high saturated electron drift velocity.
Therefore, an AlGaN/GaN heterostructure can be used for constructing a HEMT (high electron mobility transistor), and the HEMT can be suitable for high-temperature, high-voltage, high-frequency and high-power density applications and has good application prospects in the fields of microwave radio frequency, power electronics and the like.
However, since two-dimensional electron gas is easily formed at the AlGaN/GaN heterojunction interface, the HEMT is a normally-open depletion mode device, which has a technical problem of easy open by mistake in application, and thus, the popularization and application of the HEMT device are hindered.
Disclosure of Invention
The invention discloses a high electron mobility transistor which is used for relieving the technical problems of low HEMT threshold voltage and easy error switching-on.
In order to achieve the purpose, the invention provides the following technical scheme:
a high electron mobility transistor comprising:
a substrate;
a buffer layer formed on one side of the substrate;
the GaN channel layer is formed on the side, away from the substrate, of the buffer layer, wherein the GaN channel layer comprises a gate region and a non-gate region located around the gate region;
the AlGaN gate lower barrier layer is formed on one side, away from the buffer layer, of the gate region of the GaN channel layer;
the gate electrode is formed on the side face, away from the GaN channel layer, of the AlGaN gate lower barrier layer;
the AlGaN barrier layer is formed on one side, away from the buffer layer, of the non-gate region of the GaN channel layer, wherein a source electrode and a drain electrode which are in ohmic contact with the AlGaN barrier layer are formed on the surface of the AlGaN barrier layer;
the passivation layer covers the source electrode, the drain electrode, the gate electrode and the surface of the AlGaN barrier layer;
the AlGaN gate lower barrier layer has aluminum content lower than that of the AlGaN barrier layer, and/or the thickness of the AlGaN gate lower barrier layer is smaller than that of the AlGaN barrier layer.
In the high electron mobility transistor, the GaN channel layer and the AlGaN barrier layer form a heterojunction, and conductive two-dimensional electron gas is formed on the lower surface of the interface of the GaN channel layer and the AlGaN barrier layer due to the polarization characteristics of the GaN channel layer and the AlGaN barrier layer; the aluminum content of the AlGaN gate lower barrier layer is lower than that of the AlGaN barrier layer, and/or the thickness of the AlGaN gate lower barrier layer is smaller than that of the AlGaN barrier layer, so that the polarization characteristic of the AlGaN gate lower barrier layer is greatly attenuated, and two-dimensional electron gas formed at the heterojunction interface of the AlGaN gate lower barrier layer and the GaN channel layer is greatly reduced, so that the two-dimensional electron gas is cut off at the AlGaN gate lower barrier layer under the condition that a gate electrode is not electrified with positive voltage, the source electrode and the drain electrode are not easily conducted through the two-dimensional electron gas, the two-dimensional electron gas under the gate electrode is reformed only when the gate electrode is electrified with positive voltage, the two-dimensional electron gas is communicated at the AlGaN gate; in summary, in the case that the gate electrode is not applied with a positive voltage, the high electron mobility transistor can alleviate the technical problems of low threshold voltage and easy false turn-on of the HEMT, and realize normally-off operation.
Preferably, the thickness of the AlGaN gate lower barrier layer is 1nm-10 nm;
the AlGaN barrier layer has a thickness of 10nm to 40 nm.
Preferably, the aluminum content of the AlGaN gate lower barrier layer is 0-20%;
the AlGaN barrier layer has an aluminum content of 10% to 30%.
Preferably, the high electron mobility transistor further comprises a p-type semiconductor film layer disposed between the gate electrode and the AlGaN gate lower barrier layer.
Preferably, the p-type semiconductor film layer comprises p-type GaN, p-type AlGaN or p-type NiO.
Preferably, a GaN repair layer is further arranged between the AlGaN barrier layer and the GaN channel layer.
The invention discloses a preparation method of a high electron mobility transistor, which is used for relieving the technical problem that HEMTs are easy to be turned on by mistake.
In order to achieve the purpose, the invention provides the following technical scheme:
a preparation method of a high electron mobility transistor at least comprises the following steps:
sequentially forming a buffer layer and a GaN channel layer on one side of a substrate, wherein the GaN channel layer comprises a gate region and a non-gate region positioned around the gate region;
forming an AlGaN gate lower barrier layer and a gate electrode which are sequentially arranged on a gate region, and forming an AlGaN barrier layer on a non-gate region, wherein the aluminum content of the AlGaN gate lower barrier layer is lower than that of the AlGaN barrier layer, and/or the thickness of the AlGaN gate lower barrier layer is smaller than that of the AlGaN barrier layer;
forming a source electrode and a drain electrode on the surface of the AlGaN barrier layer, and annealing the AlGaN barrier layer, the source electrode and the drain electrode to enable the AlGaN barrier layer to form ohmic contact with the source electrode and the drain electrode respectively;
and forming a passivation layer covering the source electrode, the drain electrode, the gate electrode and the AlGaN barrier layer surface.
The preparation method of the high electron mobility transistor has the same advantages as the high electron mobility transistor compared with the prior art, and is not repeated herein.
Preferably, the forming of the AlGaN gate lower barrier layer and the gate electrode in the gate region and the forming of the AlGaN barrier layer in the non-gate region in sequence include:
forming an AlGaN gate lower barrier layer and a mask layer which are sequentially stacked on a gate region by a patterning process;
forming AlGaN barrier layers on the surfaces of the non-gate area and the mask layer, and removing the AlGaN barrier layers on the surfaces of the mask layer and the mask layer;
and forming a gate electrode on the surface of the AlGaN gate lower barrier layer, which is deviated from the GaN channel layer.
Preferably, the forming of the AlGaN gate lower barrier layer and the gate electrode in the gate region and the forming of the AlGaN barrier layer in the non-gate region in sequence include:
forming an AlGaN gate lower barrier layer, a gate electrode and a mask layer which are sequentially stacked on a gate region through a composition process;
and forming an AlGaN barrier layer on the non-gate area and the surface of the mask layer, and removing the AlGaN barrier layer on the surface of the mask layer and the surface of the mask layer.
Preferably, a GaN repair layer is formed in a non-gate region of the GaN channel layer before the AlGaN gate lower barrier layer is formed.
Preferably, the forming of the AlGaN gate lower barrier layer and the gate electrode in the gate region and the forming of the AlGaN barrier layer in the non-gate region in sequence include:
and forming an AlGaN barrier layer on the side of the GaN channel layer, which is far away from the buffer layer, forming a hollow structure at the part of the AlGaN barrier layer, which corresponds to the gate region, and sequentially forming an AlGaN gate lower barrier layer and a gate electrode in the hollow structure.
Preferably, the thickness of the AlGaN gate lower barrier layer is 1nm-10 nm;
the AlGaN barrier layer has a thickness of 10nm to 40 nm.
Preferably, the aluminum content of the AlGaN gate lower barrier layer is 0-20%;
the AlGaN barrier layer has an aluminum content of 10% to 30%.
Preferably, before forming the gate electrode on the AlGaN gate lower barrier layer, a p-type semiconductor film layer is formed on the AlGaN gate lower barrier layer.
Preferably, the p-type semiconductor film layer comprises p-type GaN, p-type AlGaN or p-type NiO.
The invention discloses an electronic device which is used for relieving the technical problem that HEMTs are easy to be turned on by mistake.
In order to achieve the purpose, the invention provides the following technical scheme:
an electronic device comprises the high electron mobility transistor according to the above technical solution.
The advantages of the electronic device and the high electron mobility transistor are the same as those of the prior art, and are not described herein again.
Drawings
Fig. 1 is a schematic structural diagram of a first intermediate process in a method for manufacturing a high electron mobility transistor according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of an intermediate process two in the method for manufacturing a high electron mobility transistor according to the embodiment of the present invention;
fig. 3 is a schematic structural diagram of an intermediate process three in the method for manufacturing a high electron mobility transistor according to the embodiment of the present invention;
fig. 4 is a schematic structural diagram of an intermediate process four in the method for manufacturing a high electron mobility transistor according to the embodiment of the present invention;
fig. 5 is a schematic structural diagram of a high electron mobility transistor according to an embodiment of the present invention.
Icon: 1-a substrate; 2-a buffer layer; 3-a GaN channel layer; a 4-AlGaN gate lower barrier layer; a 5-p type semiconductor film layer; 6a-GaN repair layer; 6 b-a GaN repair layer; 7a-AlGaN barrier layer; 7b-AlGaN barrier layer; an 8-source electrode; 9-a drain electrode; 10-a gate electrode; 11-a passivation layer; mask layer 12.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Example one
As shown in fig. 5, the high electron mobility transistor according to the embodiment of the present invention includes:
a substrate 1 of a material including, but not limited to, Si, SiC, sapphire, AlN or GaN;
a buffer layer 2 formed on one side of the substrate 1, the buffer layer 2 including, but not limited to, GaN, AlGaN, AlN or a laminated structure of at least two thereof, and as a specific example, the buffer layer 2 has a thickness in a range of 100nm to 6 μm, such as 100nm, 250nm, 380nm, 500nm, 750nm, 800nm, 2 μm, 3 μm, 3.5 μm, 5 μm and 6 μm;
the GaN channel layer 3 is formed on the side surface of the buffer layer 2, which is far away from the substrate 1, wherein the GaN channel layer 3 comprises a gate region and a non-gate region which is positioned around the gate region;
the AlGaN gate lower barrier layer 4 is formed on one side, away from the buffer layer 2, of the gate region of the GaN channel layer 3;
a gate electrode 10 formed on a side surface of the AlGaN gate lower barrier layer 4 facing away from the GaN channel layer 3;
and the AlGaN barrier layer 7a is formed on one side of the non-gate region of the GaN channel layer 3, which faces away from the buffer layer 2, wherein the AlGaN barrier layer 7a is provided with a source electrode 8 and a drain electrode 9 on the surface, which are in ohmic contact with the AlGaN barrier layer 7a, the source electrode 8 is made of materials including but not limited to Ti/Al/Ni/Au, Ti/Al/TiN/W, Ti/Al/Ti/W and Ti/TiN/W, and the drain electrode 9 is made of materials including but not limited to Ti/Al/Ni/Au, Ti/Al/TiN/W, Ti/Al/Ti/W and Ti/TiN/W.
A passivation layer 11 covering the surfaces of the source electrode 8, the drain electrode 9, the gate electrode 10 and the AlGaN barrier layer 7a, wherein the material of the passivation layer 11 includes but is not limited to SiO, SiO2、SiN、SiON、ZrO2、HfO2、Al2O3Or a combination of any at least two thereof;
wherein, the aluminum content of the AlGaN gate lower barrier layer 4 is lower than that of the AlGaN barrier layer 7a, and/or the thickness of the AlGaN gate lower barrier layer 4 is smaller than that of the AlGaN barrier layer 7a, for example, the thickness of the AlGaN gate lower barrier layer 4 is smaller than that of the AlGaN barrier layer 7a, and the aluminum content of the AlGaN gate lower barrier layer 4 is equal to that of the AlGaN barrier layer 7 a; or the thickness of the AlGaN gate lower barrier layer 4 is equal to that of the AlGaN barrier layer 7a, and the aluminum content of the AlGaN gate lower barrier layer 4 is lower than that of the AlGaN barrier layer 7 a; or the aluminum content of the AlGaN gate lower barrier layer 4 is lower than that of the AlGaN barrier layer 7a, and the thickness of the AlGaN gate lower barrier layer 4 is smaller than that of the AlGaN barrier layer 7 a;
in the above high electron mobility transistor, the GaN channel layer 3 and the AlGaN barrier layer 7a form a heterojunction, and a conductive two-dimensional electron gas is formed at the lower surface of the interface between the GaN channel layer 3 and the AlGaN barrier layer 7a due to the polarization characteristics of the two layers; the aluminum content of the AlGaN gate lower barrier layer 4 is lower than that of the AlGaN barrier layer 7a, and/or the thickness of the AlGaN gate lower barrier layer 4 is smaller than that of the AlGaN barrier layer 7a, so that the polarization characteristic of the AlGaN gate lower barrier layer 4 is greatly attenuated, and the two-dimensional electron gas formed at the heterojunction interface of the AlGaN gate lower barrier layer 4 and the GaN channel layer 3 is greatly reduced, so that the two-dimensional electron gas is cut off at the AlGaN gate lower barrier layer 4 under the condition that the gate electrode 10 is not electrified with positive voltage, the source electrode 8 and the drain electrode 9 are not easily conducted through the two-dimensional electron gas, and the two-dimensional electron gas under the AlGaN gate lower barrier layer 4 is regenerated only when the gate electrode 10 is electrified with positive voltage, the two-dimensional electron gas is communicated at the AlGaN gate; in summary, the gate electrode 10 of the high electron mobility transistor can alleviate the problem that the HEMT is prone to being turned on by mistake, and realize normally-off operation.
As the grid region of the GaN channel layer 3 is provided with the p-type semiconductor film layer 5 and the AlGaN grid lower barrier layer 4, the p-type semiconductor film layer 5 lifts the conduction band of the heterojunction of the grid region, and thus two-dimensional electron gas under the AlGaN grid lower barrier layer 4 is exhausted.
Preferably, the AlGaN sub-gate barrier layer 4 has a thickness of 1nm to 10nm, for example, 1nm, 3nm, 5nm, 6nm, 8nm, and 10 nm;
the AlGaN barrier layer 7a has a thickness of 10nm to 40nm, for example, 10nm, 15nm, 20nm, 30nm, 35nm, and 40 nm.
Preferably, the aluminum content of the AlGaN gate lower barrier layer 4 is 0 to 20%, for example, 0, 3%, 6%, 9%, 15%, 17%, and 20%;
the AlGaN barrier layer 7a has an aluminum content of 10% to 30%, for example, 10%, 15%, 20%, 23%, 27%, and 30%.
In order to further deplete the two-dimensional electron gas under the AlGaN gate lower barrier layer 4, the high electron mobility transistor further includes a p-type semiconductor film layer 5, the p-type semiconductor film layer 5 is disposed between the gate electrode 10 and the AlGaN gate lower barrier layer 4, and the p-type semiconductor raises a conduction band of the gate region heterojunction, so that the two-dimensional electron gas under the AlGaN gate lower barrier layer 4 is further depleted.
As a specific example, the p-type semiconductor film layer 5 includes, but is not limited to, p-type GaN, p-type AlGaN, or p-type NiO.
In addition, a GaN repair layer 6a may also be disposed between the AlGaN barrier layer 7a and the GaN channel layer 3, and when the high electron mobility transistor in the first embodiment is manufactured by using the method for manufacturing a high electron mobility transistor provided in the second embodiment, when the AlGaN gate lower barrier layer 4 and the mask layer 12 are formed by a patterning process, a non-gate region of the GaN channel layer 3 is easily damaged during etching, which affects the performance of the high electron mobility transistor.
Example two
The preparation method of the high electron mobility transistor provided by the embodiment of the invention is used for forming the high electron mobility transistor provided by the first embodiment, and at least comprises the following steps:
as shown in fig. 1, a buffer layer 2 and a GaN channel layer 3 are sequentially formed on one side of a substrate 1, wherein the GaN channel layer 3 includes a gate region and a non-gate region around the gate region;
as shown in fig. 2 to 5, an AlGaN gate lower barrier layer 4 and a gate electrode 10 are formed in this order in the gate region, and an AlGaN barrier layer 7a is formed in the non-gate region, wherein the aluminum content of the AlGaN gate lower barrier layer 4 is lower than that of the AlGaN barrier layer 7a, and/or the thickness of the AlGaN gate lower barrier layer 4 is smaller than that of the AlGaN barrier layer 7a, for example, the thickness of the AlGaN gate lower barrier layer 4 is smaller than that of the AlGaN barrier layer 7a, and the aluminum content of the AlGaN gate lower barrier layer 4 is equal to that of the AlGaN barrier layer 7 a; or the thickness of the AlGaN gate lower barrier layer 4 is equal to that of the AlGaN barrier layer 7a, and the aluminum content of the AlGaN gate lower barrier layer 4 is lower than that of the AlGaN barrier layer 7 a; or the aluminum content of the AlGaN gate lower barrier layer 4 is lower than that of the AlGaN barrier layer 7a, and the thickness of the AlGaN gate lower barrier layer 4 is smaller than that of the AlGaN barrier layer 7 a;
as shown in fig. 4, a source electrode 8 and a drain electrode 9 are formed on the surface of the AlGaN barrier layer 7a, and the AlGaN barrier layer 7a, the source electrode 8, and the drain electrode 9 are annealed, for example, by rapid thermal annealing or laser annealing, so that the AlGaN barrier layer 7a is in ohmic contact with the source electrode 8 and the drain electrode 9, respectively;
as shown in fig. 5, a passivation layer 11 is formed to cover the source 8, drain 9, gate electrode 10, and AlGaN barrier layer 7 a.
The high electron mobility transistor formed by the preparation method of the high electron mobility transistor at least has the following advantages: the GaN channel layer 3 and the AlGaN barrier layer 7a form a heterojunction, and conductive two-dimensional electron gas is formed on the lower surface of the interface of the GaN channel layer 3 and the AlGaN barrier layer 7a due to the polarization characteristics of the two layers; the aluminum content of the AlGaN gate lower barrier layer 4 is lower than that of the AlGaN barrier layer 7a, and/or the thickness of the AlGaN gate lower barrier layer 4 is smaller than that of the AlGaN barrier layer 7a, so that the polarization characteristic of the AlGaN gate lower barrier layer 4 is greatly attenuated, and the two-dimensional electron gas formed at the heterojunction interface of the AlGaN gate lower barrier layer 4 and the GaN channel layer 3 is greatly reduced, so that the two-dimensional electron gas is cut off at the AlGaN gate lower barrier layer 4 under the condition that the gate electrode 10 is not electrified with positive voltage, the source electrode 8 and the drain electrode 9 are not easily conducted through the two-dimensional electron gas, and the two-dimensional electron gas under the AlGaN gate lower barrier layer 4 is regenerated only when the gate electrode 10 is electrified with positive voltage, the two-dimensional electron gas is communicated at the AlGaN gate; in summary, the high electron mobility transistor can alleviate the technical problems of low HEMT threshold voltage and easy false turn-on, and realize normally-off operation.
The source electrode 8 and the drain electrode 9 may be prepared in the following manner: depositing on the surface of the AlGaN barrier layer 7a by electron beam evaporation, thermal evaporation or magnetron sputtering, and forming a final structure by etching or stripping; the gate electrode 10 material includes but is not limited to Ni/Au, and may be prepared by depositing on the surface of the AlGaN gate lower barrier layer 4 by electron beam evaporation, thermal evaporation or magnetron sputtering, and then forming the final structure by etching or lift-off process.
The AlGaN gate lower barrier layer 4 and the gate electrode 10 are formed in the gate region, and the AlGaN barrier layer 7a is formed in the non-gate region, which may be formed in various ways, for example:
in the first form, as shown in fig. 1, an AlGaN gate lower barrier layer 4 and a mask layer 12 are sequentially stacked and formed on a gate region by a patterning process;
as shown in fig. 2, an AlGaN barrier layer 7a is formed on the surface of the non-gate region, an AlGaN barrier layer 7b is formed on the surface of the mask layer 12, and as shown in fig. 3, the AlGaN barrier layer 7b on the surfaces of the mask layer 12 and the mask layer 12 is removed;
a gate electrode 10 is formed on the surface of the AlGaN gate lower barrier layer 4 facing away from the GaN channel layer 3.
In the second form, an AlGaN gate lower barrier layer 4, a gate electrode 10 and a mask layer 12 which are sequentially stacked are formed on a gate region through a patterning process;
an AlGaN barrier layer 7a is formed on the surface of the non-gate region, an AlGaN barrier layer 7b is formed on the surface of the mask layer 12, and the AlGaN barrier layer 7b on the surfaces of the mask layer 12 and the mask layer 12 is removed.
In order to repair damage to the non-gate region of the GaN channel layer 3 when the AlGaN gate lower barrier layer 4 and the mask layer 12, which are sequentially stacked, are formed on the gate region through a patterning process, as shown in fig. 2, before the AlGaN gate lower barrier layer 4 is formed, a GaN repair layer 6a is formed on the non-gate region of the GaN channel layer 3, while a GaN repair layer 6b is simultaneously formed on the surface of the mask layer 12 due to a deposition process, and the GaN repair layer 6b is simultaneously removed when the AlGaN barrier layer 7b and the mask layer 12 are removed.
In the third form, an AlGaN barrier layer 7a is formed on the side of the GaN channel layer 3 away from the buffer layer 2, a hollow structure is formed in the portion of the AlGaN barrier layer 7a corresponding to the gate region, and an AlGaN gate lower barrier layer 4 and a gate electrode 10 are sequentially formed in the hollow structure.
Preferably, the AlGaN sub-gate barrier layer 4 has a thickness of 1nm to 10nm, for example, 1nm, 3nm, 5nm, 6nm, 8nm, and 10 nm;
the AlGaN barrier layer 7a has a thickness of 10nm to 40nm, for example, 10nm, 15nm, 20nm, 30nm, 35nm, and 40 nm.
Preferably, the aluminum content of the AlGaN gate lower barrier layer 4 is 0 to 20%, for example, 0, 3%, 6%, 9%, 15%, 17%, and 20%;
the AlGaN barrier layer 7a has an aluminum content of 10% to 30%, for example, 10%, 15%, 20%, 23%, 27%, and 30%.
In order to further deplete the two-dimensional electron gas under the AlGaN gate lower barrier layer 4, before the gate electrode 10 is formed on the AlGaN gate lower barrier layer 4, the p-type semiconductor film layer 5 is formed on the AlGaN gate lower barrier layer 4, and the p-type semiconductor raises the conduction band of the heterojunction of the gate region, so that the two-dimensional electron gas under the AlGaN gate lower barrier layer 4 is further depleted.
As a specific example, the p-type semiconductor film layer 5 includes, but is not limited to, p-type GaN, p-type AlGaN, or p-type NiO.
EXAMPLE III
The electronic device provided by the embodiment of the invention comprises the high electron mobility transistor provided by the first embodiment.
The electronic devices include, but are not limited to, a power supply (e.g., an uninterruptible power supply), a frequency converter, and a charger (e.g., a mobile phone charger, a wireless charger, etc.).
In the above-described electronic device, in which the high electron mobility transistor, the GaN channel layer 3 and the AlGaN barrier layer 7a form a heterojunction, a two-dimensional electron gas that can conduct electricity is formed at the lower surface of the interface between the GaN channel layer 3 and the AlGaN barrier layer 7a due to the polarization characteristics of the two layers; the aluminum content of the AlGaN gate lower barrier layer 4 is lower than that of the AlGaN barrier layer 7a, and/or the thickness of the AlGaN gate lower barrier layer 4 is smaller than that of the AlGaN barrier layer 7a, so that the polarization characteristic of the AlGaN gate lower barrier layer 4 is greatly attenuated, and the two-dimensional electron gas formed at the heterojunction interface of the AlGaN gate lower barrier layer 4 and the GaN channel layer 3 is greatly reduced, so that the two-dimensional electron gas is cut off at the AlGaN gate lower barrier layer 4 under the condition that the gate electrode 10 is not electrified with positive voltage, the source electrode 8 and the drain electrode 9 are not easily conducted through the two-dimensional electron gas, and the two-dimensional electron gas under the AlGaN gate lower barrier layer 4 is regenerated only when the gate electrode 10 is electrified with positive voltage, the two-dimensional electron gas is communicated at the AlGaN gate; in summary, the high electron mobility transistor can alleviate the technical problem that the HEMT is prone to being turned on by mistake, and normally-off operation is achieved.
It will be apparent to those skilled in the art that various changes and modifications may be made in the embodiments of the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.

Claims (16)

1. A high electron mobility transistor, comprising:
a substrate;
a buffer layer formed on one side of the substrate;
the GaN channel layer is formed on the side, away from the substrate, of the buffer layer, wherein the GaN channel layer comprises a gate region and a non-gate region located around the gate region;
the AlGaN gate lower barrier layer is formed on one side, away from the buffer layer, of the gate region of the GaN channel layer;
the gate electrode is formed on the side face, away from the GaN channel layer, of the AlGaN gate lower barrier layer;
the AlGaN barrier layer is formed on one side, away from the buffer layer, of the non-gate region of the GaN channel layer, wherein a source electrode and a drain electrode which are in ohmic contact with the AlGaN barrier layer are formed on the surface of the AlGaN barrier layer;
the passivation layer covers the source electrode, the drain electrode, the gate electrode and the surface of the AlGaN barrier layer;
the AlGaN gate lower barrier layer has aluminum content lower than that of the AlGaN barrier layer, and/or the thickness of the AlGaN gate lower barrier layer is smaller than that of the AlGaN barrier layer.
2. The hemt of claim 1, wherein the AlGaN sub-gate barrier layer has a thickness of 1nm to 10 nm;
the AlGaN barrier layer has a thickness of 10nm to 40 nm.
3. The hemt of claim 1, wherein the AlGaN gate lower barrier layer has an al content of 0 to 20%;
the AlGaN barrier layer has an aluminum content of 10% to 30%.
4. The hemt of claim 1, further comprising a p-type semiconductor film layer disposed between said gate electrode and said AlGaN gate lower barrier layer.
5. The HEMT of claim 4, wherein the p-type semiconductor film layer comprises p-type GaN, p-type AlGaN, or p-type NiO.
6. The hemt of claim 1, wherein a GaN repair layer is further disposed between said AlGaN barrier layer and said GaN channel layer.
7. A preparation method of a high electron mobility transistor is characterized by at least comprising the following steps:
sequentially forming a buffer layer and a GaN channel layer on one side of a substrate, wherein the GaN channel layer comprises a gate region and a non-gate region positioned around the gate region;
forming an AlGaN gate lower barrier layer and a gate electrode which are sequentially arranged on a gate region, and forming an AlGaN barrier layer on a non-gate region, wherein the aluminum content of the AlGaN gate lower barrier layer is lower than that of the AlGaN barrier layer, and/or the thickness of the AlGaN gate lower barrier layer is smaller than that of the AlGaN barrier layer;
forming a source electrode and a drain electrode on the surface of the AlGaN barrier layer, and annealing the AlGaN barrier layer, the source electrode and the drain electrode to enable the AlGaN barrier layer to form ohmic contact with the source electrode and the drain electrode respectively;
and forming a passivation layer covering the source electrode, the drain electrode, the gate electrode and the AlGaN barrier layer surface.
8. The method for preparing a high electron mobility transistor according to claim 7, wherein the forming of the AlGaN gate lower barrier layer and the gate electrode in the gate region and the forming of the AlGaN barrier layer in the non-gate region sequentially comprise:
forming an AlGaN gate lower barrier layer and a mask layer which are sequentially stacked on a gate region by a patterning process;
forming AlGaN barrier layers on the surfaces of the non-gate area and the mask layer, and removing the AlGaN barrier layers on the surfaces of the mask layer and the mask layer;
and forming a gate electrode on the surface of the AlGaN gate lower barrier layer, which is deviated from the GaN channel layer.
9. The method for preparing a high electron mobility transistor according to claim 7, wherein the forming of the AlGaN gate lower barrier layer and the gate electrode in the gate region and the forming of the AlGaN barrier layer in the non-gate region sequentially comprise:
forming an AlGaN gate lower barrier layer, a gate electrode and a mask layer which are sequentially stacked on a gate region through a composition process;
and forming an AlGaN barrier layer on the non-gate area and the surface of the mask layer, and removing the AlGaN barrier layer on the surface of the mask layer and the surface of the mask layer.
10. The method of manufacturing a high electron mobility transistor according to claim 8 or 9, wherein a GaN repair layer is formed in a non-gate region of the GaN channel layer before the AlGaN barrier layer is formed.
11. The method for preparing a high electron mobility transistor according to claim 7, wherein forming an AlGaN gate lower barrier layer and a gate electrode in sequence on the gate region, and forming an AlGaN barrier layer on the non-gate region comprises:
and forming an AlGaN barrier layer on the side of the GaN channel layer, which is far away from the buffer layer, forming a hollow structure at the part of the AlGaN barrier layer, which corresponds to the gate region, and sequentially forming an AlGaN gate lower barrier layer and a gate electrode in the hollow structure.
12. The method of manufacturing a high electron mobility transistor according to claim 7, wherein the thickness of the AlGaN gate lower barrier layer is 1nm to 10 nm;
the AlGaN barrier layer has a thickness of 10nm to 40 nm.
13. The method of claim 7, wherein the AlGaN under-gate barrier layer has an Al content of 0-20%;
the AlGaN barrier layer has an aluminum content of 10% to 30%.
14. The method of claim 7, wherein a p-type semiconductor film is formed on the AlGaN gate lower barrier layer before the gate electrode is formed on the AlGaN gate lower barrier layer.
15. The method for preparing a high electron mobility transistor according to claim 14, wherein the p-type semiconductor film layer comprises p-type GaN, p-type AlGaN or p-type NiO.
16. An electronic device comprising the high electron mobility transistor according to any one of claims 1 to 6.
CN201910323441.8A 2019-04-22 2019-04-22 High-electron-mobility transistor, preparation method thereof and electronic device Pending CN111834439A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201910323441.8A CN111834439A (en) 2019-04-22 2019-04-22 High-electron-mobility transistor, preparation method thereof and electronic device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201910323441.8A CN111834439A (en) 2019-04-22 2019-04-22 High-electron-mobility transistor, preparation method thereof and electronic device

Publications (1)

Publication Number Publication Date
CN111834439A true CN111834439A (en) 2020-10-27

Family

ID=72911783

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201910323441.8A Pending CN111834439A (en) 2019-04-22 2019-04-22 High-electron-mobility transistor, preparation method thereof and electronic device

Country Status (1)

Country Link
CN (1) CN111834439A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112582470A (en) * 2020-12-30 2021-03-30 江苏大学 Normally-off high electron mobility transistor and manufacturing method thereof
CN112786686A (en) * 2021-02-08 2021-05-11 西安电子科技大学 AlGaN/GaN high electron mobility transistor with P-type doping on surface of barrier layer
CN113937155A (en) * 2021-09-29 2022-01-14 西安电子科技大学 HEMT (high electron mobility transistor) device with gradually-changed components and composite barrier layer and preparation method thereof

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112582470A (en) * 2020-12-30 2021-03-30 江苏大学 Normally-off high electron mobility transistor and manufacturing method thereof
CN112786686A (en) * 2021-02-08 2021-05-11 西安电子科技大学 AlGaN/GaN high electron mobility transistor with P-type doping on surface of barrier layer
CN113937155A (en) * 2021-09-29 2022-01-14 西安电子科技大学 HEMT (high electron mobility transistor) device with gradually-changed components and composite barrier layer and preparation method thereof
CN113937155B (en) * 2021-09-29 2024-01-19 西安电子科技大学 Component gradient composite barrier layer HEMT device and preparation method thereof

Similar Documents

Publication Publication Date Title
US10121885B2 (en) Protective insulator for HFET devices
Lee et al. 245-GHz InAlN/GaN HEMTs with oxygen plasma treatment
CN101211969B (en) High speed high power nitride semiconductor device and manufacturing method thereof
JP4845872B2 (en) Semiconductor device having MIS structure and manufacturing method thereof
CN104377239A (en) Semiconductor device and manufacturing method thereof
WO2010064362A1 (en) Field effect transistor
JP2014116401A (en) Semiconductor device and method of manufacturing the same
US10283631B2 (en) Semiconductor device and method of fabricating the same
JP2017073499A (en) Nitride semiconductor device and method for manufacturing the same
CN109524460B (en) High hole mobility transistor
CN211578757U (en) High electron mobility transistor
US20150021671A1 (en) Field-effect transistor and method of manufacturing thereof
CN111834439A (en) High-electron-mobility transistor, preparation method thereof and electronic device
JP2007537580A (en) Field effect transistor with enhanced insulator structure
CN107706241A (en) A kind of normally-off GaNMOSFET structures at high quality MOS interfaces and preparation method thereof
WO2019176434A1 (en) Semiconductor device, semiconductor device production method, and electronic device
CN109659355A (en) Normally-off gallium oxide field-effect transistor structure and preparation method
CN101414627A (en) Insulated gate type source-leakage composite field plate transistor with high electron mobility and preparing method thereof
CN111584628B (en) Enhanced GaN HEMT device and preparation method thereof
CN111599857B (en) Heterogeneous integrated structure of two-dimensional material device and GaN device and preparation method
JP2021120966A (en) Switching transistor and semiconductor module
KR20120124101A (en) Nitride based heterostructure field effect transistor having high efficiency
JP2019114581A (en) Compound semiconductor device and manufacturing method thereof
WO2021106236A1 (en) Diode, method for producing diode, and electronic device
Peng et al. Effects of the Fe-doped GaN buffer in AlGaN/GaN HEMTs on SiC substrate

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination