CN111613671A - GaN-based MIS-HEMT device with symmetrical structure and preparation method thereof - Google Patents
GaN-based MIS-HEMT device with symmetrical structure and preparation method thereof Download PDFInfo
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- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7782—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET
- H01L29/7783—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET using III-V semiconductor material
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Abstract
The invention relates to a symmetrical structure GaN-based MIS-HEMT device and a preparation method thereof, the device comprises a laminated structure consisting of an AlGaN buffer layer, an AlGaN back barrier layer, a GaN channel layer, an AlN insert layer, an AlGaN barrier layer and a GaN cap layer which are laminated on a substrate, the laminated structure is provided with an arc-shaped end face, a drain electrode which is in an inverted U-shaped structure is encircled along the edge of the laminated structure, a source electrode which is arranged along the symmetrical line of the inverted U-shaped structure is provided with an arc-shaped end face, a passivation layer pattern which is positioned on the source electrode and the drain electrode, a grid dielectric layer which is positioned on the GaN cap layer and the passivation layer pattern, and a grid which is positioned on the grid. The device has high average breakdown electric field intensity and breakdown voltage, and has great application prospect in the aspects of high-temperature high-frequency high-power devices, high-power switches and the like.
Description
Technical Field
The invention relates to the technical field of microelectronics, in particular to a GaN-based MIS-HEMT device with a symmetrical structure.
Background
The GaN-based material has wide application potential and good market prospect in the fields of high-brightness blue, green, purple and white light diodes, blue and purple lasers, radiation-resistant and high-temperature high-power microwave devices and the like. Gallium nitride, as a representative of third generation wide bandgap semiconductors, has the characteristics of wide bandgap, high saturation electron velocity and high breakdown electric field, and the device power density is more than 10 times of that of Si and GaAs, and has been widely used in radio frequency devices and high power switching devices.
However, poor electron confinement of conventional single heterostructure high electron mobility transistors (SH-HEMTs) can lead to poor subthreshold pinch-off characteristics and severely degrade dc and rf performance. Therefore, the use of the double heterojunction high electron mobility transistor (DH-HEMT) can significantly improve carrier confinement and reduce leakage current, so that the double heterojunction exhibits better dc characteristics than the single heterojunction. In addition, the double heterojunction has excellent high-temperature transport characteristics at high temperatures, as compared to the conventional single heterojunction. However, the average breakdown electric field strength and breakdown voltage of the present double-heterojunction device still need to be improved, and how to improve the average electric field strength and breakdown voltage of the double-heterojunction device is one of the problems to be solved in the field.
Disclosure of Invention
The invention aims to overcome the defects in the prior art, and provides a symmetrical GaN-based MIS-HEMT device and a preparation method thereof from the aspect of optimization of the device structure so as to reduce industrial difficulty, reduce damage in the device manufacturing process, improve the reliability of the device and meet the requirements of practical application.
The invention provides at least the following scheme:
a symmetrical structural GaN-based MIS-HEMT device comprises a laminated structure, a metal-insulator-semiconductor (MIS-HEMT) device and a metal-insulator-semiconductor (HEMT) device, wherein the laminated structure comprises an AlGaN buffer layer, an N-type doped AlGaN back barrier layer, a GaN channel layer, an AlN insertion layer, an AlGaN barrier layer and a GaN cap layer which are sequentially laminated on a Si substrate, and the laminated structure is provided with an arc-shaped end face; the drain electrode is positioned on the GaN cap layer and surrounds the edge of the laminated structure to form an inverted U-shaped structure; the source electrode is arranged on the GaN cap layer along the symmetrical line of the inverted U-shaped structure and is provided with an arc-shaped end face; a passivation layer pattern on the source and drain electrodes; a gate dielectric layer on the GaN cap layer and the passivation layer pattern; and the grid electrode is positioned on the grid dielectric layer between the source electrode and the drain electrode, and is surrounded along the source electrode to form an inverted U-shaped structure.
Further, the width of the gate is smaller than that of the drain.
Furthermore, the interval between the inverted U-shaped structure of the grid electrode and the inverted U-shaped structure of the drain electrode is uniform.
Further, the gate dielectric layer is Al2O3The thickness of the material is 10-20 nm; the passivation layer pattern is SiO2The thickness of the material is 80-100 nm; the thickness of the GaN cap layer is 2-6 nm.
Furthermore, the AlGaN buffer layer is doped in an N type, the molar content of Al element is 1-6%, and the thickness of the AlGaN buffer layer is 1.3-1.5 μm.
Furthermore, the AlGaN back barrier layer is doped in an N type, the molar content of Al element is 6.5-7.5%, and the thickness of the AlGaN back barrier layer is 250-350 nm.
Furthermore, the molar content of Al element in the AlGaN barrier layer is 6.5% -7.5%, and the thickness of the AlGaN barrier layer is 20-30 nm.
Furthermore, the thickness of the GaN channel layer is 15-25nm, and the thickness of the AlN insert layer is 0.8-1.2 nm.
The invention also provides a preparation method of the symmetrical GaN-based MIS-HEMT device, which comprises the following steps:
heating and pretreating a Si (111) substrate;
sequentially epitaxially growing an N-type doped AlGaN buffer layer with the molar content of Al element of 1-6%, an N-type doped AlGaN back barrier layer with the molar content of Al element of 6.5-7.5%, a grown GaN channel layer, an AlN insert layer, an AlGaN barrier layer with the molar content of Al element of 25-35% and a GaN cap layer on a pretreated silicon substrate to form an epitaxial wafer, wherein the epitaxial wafer is provided with an arc-shaped end face;
photoetching a source, a drain region, a source window and a drain window on the epitaxial wafer in sequence, then depositing metal by adopting an electron beam evaporation method, and forming a source electrode and a drain electrode after stripping and annealing, wherein the drain electrode is surrounded along the edge of the epitaxial wafer to form an inverted U-shaped structure, the source electrode is arranged along the symmetrical line of the inverted U-shaped structure, and the source electrode is provided with an arc-shaped end surface;
depositing SiO on the surface of the epitaxial wafer for forming the source electrode and the drain electrode by adopting a plasma enhanced chemical vapor deposition method2A passivation layer;
etching the SiO between the source electrode and the drain electrode2Passivation layer to form SiO wrapping the source and drain electrodes2A passivation layer pattern;
on the surface of the epitaxial wafer, O is introduced3Assisted atomic layer deposition for Al growth at high temperature2O3A gate dielectric layer;
and forming a gate window on the gate dielectric layer between the source electrode and the drain electrode, depositing metal by using an electron beam evaporation method, and stripping to form a gate, wherein the gate is surrounded along the source electrode and is in an inverted U-shaped structure.
Further, said Al2O3In the step of growing the gate dielectric, Al is grown at 15nm in a hot mode at 300 deg.C2O3A gate dielectric comprising trimethylaluminum and H2Growing 2nm Al by using O as a growth source2O3Then with trimethylaluminum and O3Growing 13nm of Al as a growth source2O3(ii) a Then at N2Annealing at 500 deg.C for 1 min in the environment。
In the preparation method of the device, the strategy of removing the chlorine-based etching residues by using the high temperature of the substrate and recovering the damage caused by etching in the AlGaN barrier layer is provided, so that the surface state of the grid electrode is obviously improved. This technique is combined with the passage of O3High quality Al with assisted Atomic Layer Deposition (ALD) deposition2O3The gate dielectric in combination provides a device with a high threshold voltage (V)TH) And drive current, as well as larger gate voltage swing. Such an enhancement-type MIS-HEMT has excellent on-state drive capability.
Compared with the prior art, the invention has at least the following beneficial effects:
the invention provides a symmetrical structure GaN-based MIS-HEMT device and a preparation method thereof. Compared with the conventional HEMT device, the symmetrical structure device has high average breakdown electric field intensity and greatly improved breakdown voltage. In addition, one end (back) of the device structure is of an arc-shaped structure, and the structure effectively reduces adverse effects of right angles in a conventional rectangular structure on electron migration, so that the normally-off symmetrical-structure high-electron-mobility transistor has a great application prospect in the aspects of high-temperature high-frequency high-power devices, high-power switches and the like. On the other hand, the preparation method of the invention improves the performance of the device, especially improves the carrier limitation and reduces the leakage current, and has more effective high-temperature conduction. The process steps are mature technologies at home and abroad at present, and the process flow is simple and the cost is low. The device manufactured by the invention has simple structure and high repeatability and reliability of the process, and improves the voltage resistance and stability of the device under the condition of ensuring the turn-off of the device. The prepared device has high threshold voltage (V)TH) And the driving current, the higher average breakdown electric field intensity and breakdown voltage, the larger grid voltage swing and the high reliability of the device.
Drawings
FIG. 1 is a 3D diagram of a symmetrical structure GaN-based MIS-HEMT device structure of the present invention.
FIG. 2 is a schematic cross-sectional view of a symmetrical structure GaN-based MIS-HEMT device of the present invention.
Fig. 3a to fig. 3e are schematic views of the process flow of the symmetrical structure GaN-based MIS-HEMT device of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings, and the described embodiments are only a part of the embodiments of the present invention, but not all of the embodiments. Based on the embodiments of the present invention, other embodiments obtained by persons of ordinary skill in the art without any creative effort belong to the protection scope of the present invention.
The present invention will be described in further detail below. As shown in fig. 1, the symmetrical-structure GaN-based MIS-HEMT device of the present invention includes a stacked structure, a drain electrode, a source electrode, a passivation layer, a gate dielectric layer, and a gate electrode.
As shown in fig. 1-2, the laminated structure has an arcuate end face. The laminated structure is formed by sequentially laminating a silicon substrate 1, an AlGaN buffer layer 2, an N-type doped AlGaN back barrier layer 3, a GaN channel layer 4, an AlN insertion layer 5, an AlGaN barrier layer 6 and a GaN cap layer 7. In this example, the silicon substrate 1 is selected as a Si (111) substrate.
The AlGaN buffer layer 2 is doped with N type, the thickness of the AlGaN buffer layer is 1.3-1.5 um, and the molar content of Al element in the AlGaN buffer layer 2 is 1-6%. The molar content of Al element in the N-type doped AlGaN back barrier layer 3 is 6.5-7.5%, and the thickness of the Al element is 250-350 nm. The thickness of the GaN channel layer 4 is 15-25 nm. The AlGaN buffer layer 2/the AlGaN back barrier layer 3/the GaN channel layer 4 form a double heterojunction structure. The AlN insert layer 5 has a thickness of 0.8 to 1.2 nm. The molar content of Al element in the AlGaN barrier layer 6 is 6.5-7.5%, and the thickness of the AlGaN barrier layer is 20-30 nm. The thickness of the GaN cap layer 7 is 2-6 nm.
The drain electrode 8 and the source electrode 9 are located on the GaN cap layer 7 in the stacked structure, and as shown in fig. 1-2, the drain electrode 8 has an inverted U-shaped structure in a top view, and is circumferentially disposed along the edge of the stacked structure. The source electrode 9 is disposed along the axial symmetry line of the drain electrode 8 and has an arc-shaped end face disposed in the same direction as the arc-shaped end face of the laminated structure. The source electrode 9 and the drain electrode 8 are uniformly spaced. The projected area of the source electrode 9 is smaller than that of the drain electrode 8. The thickness of the drain electrode 8 and the source electrode 9 is 30 to 160 nm. In one example, the drain electrode 8 and the source electrode 9 are both Ti/Al/Ni/Au composite metal layers. The thickness of each layer of metal was 0.01 μm/0.06 μm/0.03 μm/0.03. mu.m, respectively.
A passivation layer 10 is positioned on the source electrode 9 and the drain electrode 8, wrapping the source electrode 9 and the drain electrode 8 positioned on the upper surface of the stacked structure. The thickness of the passivation layer 10 is 80-100 nm. In one example, the passivation layer 10 is SiO2As a subsequent high temperature inductively coupled plasma dry etch (ICP) mask. The thickness is preferably 100 nm.
A gate dielectric layer 11 is located on the GaN cap layer 7 and the passivation layer 10 covering the upper surface of the entire stacked structure. The thickness of the gate dielectric layer 11 is 10-20 nm. In one embodiment, the gate dielectric layer 11 is made of Al2O3The thickness is preferably 15 nm.
As shown in fig. 1-2, the gate electrode 12 is located on the gate dielectric layer 11 between the source electrode 9 and the drain electrode 8, clings to the surface of the gate dielectric layer 11 on the sidewall of the source electrode 9, and is surrounded along the source electrode 9 to form an inverted U-shaped structure. The thickness of the gate 12 is 30 to 160nm, and the width thereof is smaller than that of the drain 8.
In one example, the gate 12 is a Ti/Al/Ni/Au composite metal layer. The thickness of each layer of metal was 0.01 μm/0.06 μm/0.03 μm/0.03. mu.m, respectively.
The entire device structure is symmetrical along the line of symmetry of the stacked structure.
As shown in fig. 3a to 3e, the method for manufacturing the symmetrical structure GaN-based MIS-HEMT device of the present invention includes the following steps.
In this example, a Si (111) substrate was placed in an MOCVD reaction chamber for heating and pretreatment.
And 2, sequentially epitaxially growing an N-type doped AlGaN buffer layer with the molar content of Al element of 1-6%, an N-type doped AlGaN back barrier layer with the molar content of Al element of 6.5-7.5%, a grown GaN channel layer, an AlN insert layer, an AlGaN barrier layer with the molar content of Al element of 25-35% and a GaN cap layer on the pretreated silicon substrate to form an epitaxial wafer, wherein the epitaxial wafer is shown in FIG. 3 a. The epitaxial wafer has an arc-shaped end surface.
In this example, a stacked structure of epitaxial wafers was epitaxially grown on a Si substrate using a Metal Organic Chemical Vapor Deposition (MOCVD) technique. Wherein the thickness of the AlGaN buffer layer is 1.4um, and the mol content of the Al element is preferably 5%. Al (Al)0.05Ga0.95The process conditions of the N buffer layer are as follows: the temperature was set at 1080 ℃, the pressure was set at 40Torr, the flow of ammonia gas was 1500sccm, the flow of gallium source was 90sccm, the flow of aluminum source was 4sccm, and the flow of hydrogen was 2500 sccm.
In this embodiment, the AlGaN back barrier layer has a thickness of 300nm, and the Al element is preferably contained in an amount of 7 mol%. Al (Al)0.07Ga0.93The process conditions of the N back barrier layer are as follows: the temperature was 1070 deg.C, the pressure was 40Torr, the flow of ammonia gas was 1500sccm, the flow of gallium source was 90sccm, the flow of aluminum source was 6sccm, and the flow of hydrogen gas was 2500 sccm.
In this embodiment, the thickness of the GaN channel layer is 20 nm. The process conditions are as follows: the temperature was 920 ℃, the pressure was 40Torr, the hydrogen flow was 5000sccm, the ammonia flow was 5000sccm, and the gallium source flow was 220 sccm. The AlN insert layer had a thickness of 1 nm. The process conditions are as follows: the temperature is 940 ℃, the pressure is 40Torr, the hydrogen flow is 2500sccm, the ammonia flow is 1600sccm, and the aluminum source flow is 4 sccm.
Depositing Al with a thickness of 22nm on the AlN insert layer0.3Ga0.7An N barrier layer. The process conditions are as follows: the temperature was 920 ℃, the pressure was 40Torr, the hydrogen flow was 5000sccm, the ammonia flow was 500sccm, the aluminum source flow was 10sccm, and the gallium source flow was 40 sccm.
In this embodiment, the thickness of the GaN cap layer is preferably 3 nm. The process conditions are as follows: the temperature was 920 ℃, the pressure was 40Torr, the hydrogen flow was 5000sccm, the ammonia flow was 5000sccm, and the gallium source flow was 220 sccm.
And 3, photoetching a source region, a drain region, a source window and a drain window on the epitaxial wafer in sequence, then depositing metal by adopting an electron beam evaporation method, stripping and annealing to form a source electrode and a drain electrode, wherein the drain electrode 8 is surrounded along the edge of the epitaxial wafer to form an inverted U-shaped structure, the source electrode 9 is arranged along the symmetrical line of the inverted U-shaped structure, and the source electrode is provided with an arc-shaped end face.
In this embodiment, the source and drain are made of Ti/Al/Ni/Au composite metal layers with a thickness of 0.01 μm/0.06 μm/0.03 μm, respectively, and the electron beam evaporation is performed under a vacuum degree of less than 1.8 × 10-3Pa, power range of 200-1000W, evaporation rate of
And soaking the epitaxial wafer with the evaporated ohmic contact metal in an acetone solution for 20min, then carrying out ultrasonic cleaning, washing with ultrapure water and drying with nitrogen to realize metal stripping. Subsequently, ohmic contact annealing was performed for 30s at 850 ℃ in a nitrogen atmosphere to form source and drain electrodes, as shown in fig. 3 b.
In this example, 100nm SiO was deposited by Plasma Enhanced Chemical Vapor Deposition (PECVD) at 300 deg.C2As a passivation layer.
In this example, a high temperature inductively coupled plasma dry etching system (ICP) was used to etch SiO2Passivation layer to remove SiO outside the source and drain electrodes2Passivation layer of SiO2A passivation layer pattern 10. After the etching is finished, SiO2The passivation layer wraps only the source and drain electrodes as shown in fig. 3 c. The coil power and platen power of the ICP system were set to 50W and 15W, respectively.
As shown in fig. 3d, immediately after the etching is completed, pass through O3Assisted Atomic Layer Deposition (ALD) growth of 15nm Al in a 300 deg.C thermal mode2O3Gate dielectric ofIn the first place, Trimethylaluminum (TMA) and H are used2Growing 2nm Al by using O as a growth source2O3Then using O3Substitute for H2O, i.e. with Trimethylaluminium (TMA) and O3Instead of growing 13nm of Al as a growth source2O3. Then at N2The dielectric post anneal is performed at 500 deg.C for 1 minute in ambient. Initially without the use of O3In order to avoid oxidation of AlGaN.
And 7, forming a gate window on the gate dielectric layer between the source electrode and the drain electrode, depositing metal by using an electron beam evaporation method, stripping to form a gate electrode 12, wherein the gate electrode 12 is surrounded along the source electrode to form an inverted U-shaped structure.
Forming a gate window on the gate dielectric layer between the source and drain electrodes by photoresist throwing, soft baking, exposing and developing, and then performing electron beam evaporation at vacuum degree of less than 1.8 × 10-3Pa, power range of 200-1000W, evaporation rate of
Under the condition of (1), Ti/Al/Ni/Au composite metal layers are deposited, and the thickness of each layer of metal is 0.01 mu m/0.06 mu m/0.03 mu m.
And soaking the epitaxial wafer with the evaporated composite metal layer in an acetone solution for 20min, then carrying out ultrasonic cleaning, then washing with ultrapure water and drying with nitrogen, and finally obtaining a gate pattern surrounding the source electrode, as shown in fig. 3 e. The gate electrode 12 is in close contact with the gate dielectric layer 11 on the sidewall of the source electrode 9.
And photoetching the surface of the epitaxial wafer which is formed into the source, the drain and the grid to obtain a thickened electrode pattern, and thickening the electrode by adopting electron beam evaporation to finish the manufacture of the device shown in figure 1. The above embodiments are preferred embodiments of the present invention, but the present invention is not limited to the above embodiments, and any other changes, modifications, substitutions, combinations, and simplifications which do not depart from the spirit and principle of the present invention should be construed as equivalents thereof, and all such changes, modifications, substitutions, combinations, and simplifications are intended to be included in the scope of the present invention.
Claims (10)
1. A symmetrical structure GaN-based MIS-HEMT device is characterized in that it comprises,
the laminated structure comprises an AlGaN buffer layer, an N-type doped AlGaN back barrier layer, a GaN channel layer, an AlN insert layer, an AlGaN barrier layer and a GaN cap layer which are sequentially laminated on a Si substrate, and the laminated structure is provided with an arc-shaped end face;
the drain electrode is positioned on the GaN cap layer and surrounds the edge of the laminated structure to form an inverted U-shaped structure;
the source electrode is arranged on the GaN cap layer along the symmetrical line of the inverted U-shaped structure and is provided with an arc-shaped end face;
a passivation layer pattern on the source and drain electrodes;
a gate dielectric layer on the GaN cap layer and the passivation layer pattern;
and the grid electrode is positioned on the grid dielectric layer between the source electrode and the drain electrode, and is surrounded along the source electrode to form an inverted U-shaped structure.
2. The MIS-HEMT device of claim 1, wherein the gate has a width less than the width of the drain.
3. The MIS-HEMT device of claim 1 or 2, wherein the inverted U-shaped structure of the gate and the inverted U-shaped structure of the drain are uniformly spaced.
4. A MIS-HEMT device according to claim 3, wherein the gate dielectric layer is Al2O3The thickness of the material is 10-20 nm; the passivation layer pattern is SiO2The thickness of the material is 80-100 nm; the thickness of the GaN cap layer is 2-6 nm.
5. The MIS-HEMT device according to claim 1 or 2, wherein the AlGaN buffer layer is N-doped, the molar content of Al element is 1-6%, and the thickness of the AlGaN buffer layer is 1.3-1.5 μm.
6. The device of claim 3, wherein the AlGaN back barrier layer is N-doped, has an Al element content of 6.5 to 7.5 mol% and has a thickness of 250 to 350 nm.
7. The device according to claim 3, wherein the molar content of Al element in the AlGaN barrier layer is 6.5% to 7.5%, and the thickness of the AlGaN barrier layer is 20 to 30 nm.
8. The device of claim 4, 5 or 7, wherein the GaN channel layer has a thickness of 15-25nm and the AlN insert layer has a thickness of 0.8-1.2 nm.
9. A preparation method of a symmetrical GaN-based MIS-HEMT device is characterized by comprising the following steps:
heating and pretreating a Si (111) substrate;
sequentially epitaxially growing an N-type doped AlGaN buffer layer with the molar content of Al element of 1-6%, an N-type doped AlGaN back barrier layer with the molar content of Al element of 6.5-7.5%, a grown GaN channel layer, an AlN insert layer, an AlGaN barrier layer with the molar content of Al element of 25-35% and a GaN cap layer on a pretreated silicon substrate to form an epitaxial wafer, wherein the epitaxial wafer is provided with an arc-shaped end face;
photoetching a source, a drain region, a source window and a drain window on the epitaxial wafer in sequence, then depositing metal by adopting an electron beam evaporation method, and forming a source electrode and a drain electrode after stripping and annealing, wherein the drain electrode is surrounded along the edge of the epitaxial wafer to form an inverted U-shaped structure, the source electrode is arranged along the symmetrical line of the inverted U-shaped structure, and the source electrode is provided with an arc-shaped end surface;
depositing SiO on the surface of the epitaxial wafer for forming the source electrode and the drain electrode by adopting a plasma enhanced chemical vapor deposition method2A passivation layer;
etching the SiO between the source electrode and the drain electrode2Passivation layer to form SiO wrapping the source and drain electrodes2A passivation layer pattern;
on the surface of the epitaxial wafer, O is introduced3Assisted atomic layer deposition for Al growth at high temperature2O3A gate dielectric layer;
and forming a gate window on the gate dielectric layer between the source electrode and the drain electrode, depositing metal by using an electron beam evaporation method, and stripping to form a gate, wherein the gate is surrounded along the source electrode and is in an inverted U-shaped structure.
10. The method according to claim 9, wherein the Al is2O3In the step of growing the gate dielectric, Al is grown at 15nm in a hot mode at 300 deg.C2O3A gate dielectric comprising trimethylaluminum and H2Growing 2nm Al by using O as a growth source2O3Then with trimethylaluminum and O3Growing 13nm of Al as a growth source2O3(ii) a Then at N2Annealing at 500 deg.C for 1 min.
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